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To: , , , CC: , , , , , , , Sheetal Subject: [PATCH v2 2/2] dmaengine: tegra210-adma: Add Tegra264 support Date: Mon, 12 May 2025 05:00:10 +0000 Message-ID: <20250512050010.1025259-3-sheetal@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250512050010.1025259-1-sheetal@nvidia.com> References: <20250512050010.1025259-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CC:EE_|SA1PR12MB7200:EE_ X-MS-Office365-Filtering-Correlation-Id: 5dd583de-e598-4ccd-d3b9-08dd9111f8c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?EuoyoEpIryL8J405D404vimxgHMOC8+3ohkf4y09DMP5709y9PM8IWWNde8v?= =?us-ascii?Q?3N0IUjrhajNrvYIXgsNNKDkDRmYvXuTkm015K8DHc/78XadDAzV2SguV41pN?= =?us-ascii?Q?MF4XtNfUE3KQcR+sPrJlKFBuSFL7qQ1xDHgPVwqEwfSNGVqQKjs8e419WfcB?= =?us-ascii?Q?ACAzHeADH0geXVB+/HU9bu4Vq0tm7MRqBKPWfrY2ekuSuN5No9QN6p4B1uif?= =?us-ascii?Q?ZlY05H/kjIgqoeXdERm94kFINfZmu7JzZbin1S4d6dYMnTiV6KNuXtlMfXFd?= =?us-ascii?Q?lpuTXjljRgcO1Io1Bsbcy6XJ0/5nhGqMu7Mc/26U/nSPHkbB8IFpN9BCWUXe?= =?us-ascii?Q?wwI2Ngtvhns1M9eFfBroFXw61QGfiXS48dcafC7lC9t/41gWGVtDT43P+jHN?= =?us-ascii?Q?DEYItLzs5WFWSr3+b8QQxPP5MLn0ofViPtAnJE9y6TmUzXohSJYpButeib88?= =?us-ascii?Q?hPlNV+k5OReYkGiKjDraTeS//4NxqiW/7GQW0I0w4Y7J6yBi1ZFpFdq9XPIr?= =?us-ascii?Q?6Z98rs++CbpvrAjFGAKXLoHkPZqGiGLQ2buSXyFfzgS2q8H6YuYAOfKzaLk6?= =?us-ascii?Q?ebAV+DsCYw18Teary583A7YHVtJSmEbHPzc9kOHhaGRWoRNzT+YVN2R3bUZz?= =?us-ascii?Q?floBfsHK8VOFbTeaypv5bbwklCdTQ5oRjujgHlX8bCT+BfusJ5kFuE0McVww?= =?us-ascii?Q?GCFJ9ZcBtiY/ZhsX+dBSYEa693qUDzfZdoOdK+WFg0Y0Sv8d4Lqlj8hPLvtT?= =?us-ascii?Q?LtIMfvQ/plKDFx6mQlWTdeQOIitCRAiWWn7VQ/OP1kOzKMIOi2pX5SmLaEZv?= =?us-ascii?Q?2mnZEXTD2B4QAWHx10ll1HH2ATG8m5sVY+4tN0093DOAUmj7QY0AKcd1BSdz?= =?us-ascii?Q?Wr6U3SANnxlyGr6iRq3i65sPP0+xTDca7eOsdsInCeQviPNQWG8rYLnHbTqB?= =?us-ascii?Q?PccsRl2C39NyiqP566HDOV/IugZrQbF9lWJ4QSAfBBhLAbdsXhC3Uv13C+Fh?= =?us-ascii?Q?u7g6ndukW6x6czbl/HlhJMMpYrBJidj/pDeH2xObATxqecs847a/lnQjpGhD?= =?us-ascii?Q?MigR76MDTla/awfrdDhaGUvgVUusQwsw6AvUHWp1h1dAxN5AstdKx4dHdIHX?= =?us-ascii?Q?nIIHwakWYgGv3i6I0b2YXDQA1466e0Nk23YXkN6rkUKmrcfeq18wuxEV4oQI?= =?us-ascii?Q?H+OnABMPqaWt1uxgRtQqW5jvS90lRIhixAidKYoRJuGZVkIS0Ttwl2TJWt6u?= =?us-ascii?Q?B3aDWpN6Y1HlqL1fzB6+7IhmsBjvwIePt3WIuyF4SyEmA8Stqfo19CsD++K3?= =?us-ascii?Q?AKH3OT0ll7R4YLGjKXRK/+xf3M/vVcfUJRO3Bda1SWA/Aff3ZVHAFAxjKCpE?= =?us-ascii?Q?jgJjFVgWudP2ZjbcLggAHkfcGnKyDt21vmlTHPkZ1eS4M20TCrqshtdoRA6Q?= =?us-ascii?Q?O3D68n8m06eeQnPZvbD3EmizyWo49mRmmdjsk6nNGSjBWlHtYmLSfSJoPas2?= =?us-ascii?Q?5PXspXFyGft6nW7IPK8C1wKKZFMSc4jh4JkN?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2025 05:00:53.0496 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5dd583de-e598-4ccd-d3b9-08dd9111f8c5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7200 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sheetal Add Tegra264 ADMA support with following changes: - Add soc_data for Tegra264-specific variations. - Tegra264 supports 64 channels and 10 pages, hence update the global page configuration. - In Tegra264 FIFO and outstanding request configs are moved to global registers, hence add those registers offset in adma channel struct. Also, 'has_outstanding_reqs' is removed and configuration moved to the SoC data. - Update channel direction and mode bit positions as per Tegra264. - Register offsets are updated to align with Tegra264. Signed-off-by: Sheetal --- drivers/dma/tegra210-adma.c | 185 +++++++++++++++++++++++++++++++----- 1 file changed, 160 insertions(+), 25 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index ce80ac4b1a1b..fad896ff29a2 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -27,10 +27,10 @@ =20 #define ADMA_CH_INT_CLEAR 0x1c #define ADMA_CH_CTRL 0x24 -#define ADMA_CH_CTRL_DIR(val) (((val) & 0xf) << 12) +#define ADMA_CH_CTRL_DIR(val, mask, shift) (((val) & (mask)) << (shift)) #define ADMA_CH_CTRL_DIR_AHUB2MEM 2 #define ADMA_CH_CTRL_DIR_MEM2AHUB 4 -#define ADMA_CH_CTRL_MODE_CONTINUOUS (2 << 8) +#define ADMA_CH_CTRL_MODE_CONTINUOUS(shift) (2 << (shift)) #define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1) #define ADMA_CH_CTRL_XFER_PAUSE_SHIFT 0 =20 @@ -41,15 +41,27 @@ #define ADMA_CH_CONFIG_MAX_BURST_SIZE 16 #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf) #define ADMA_CH_CONFIG_MAX_BUFS 8 -#define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4) +#define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) ((reqs) << 4) + +#define ADMA_GLOBAL_CH_CONFIG 0x400 +#define ADMA_GLOBAL_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0x7) +#define ADMA_GLOBAL_CH_CONFIG_OUTSTANDING_REQS(reqs) ((reqs) << 8) =20 #define TEGRA186_ADMA_GLOBAL_PAGE_CHGRP 0x30 #define TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ 0x70 #define TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ 0x84 +#define TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0 0x44 +#define TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1 0x48 +#define TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0 0x100 +#define TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1 0x104 +#define TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0 0x180 +#define TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1 0x184 +#define TEGRA264_ADMA_GLOBAL_PAGE_OFFSET 0x8 =20 #define ADMA_CH_FIFO_CTRL 0x2c #define ADMA_CH_TX_FIFO_SIZE_SHIFT 8 #define ADMA_CH_RX_FIFO_SIZE_SHIFT 0 +#define ADMA_GLOBAL_CH_FIFO_CTRL 0x300 =20 #define ADMA_CH_LOWER_SRC_ADDR 0x34 #define ADMA_CH_LOWER_TRG_ADDR 0x3c @@ -73,36 +85,48 @@ struct tegra_adma; * @adma_get_burst_config: Function callback used to set DMA burst size. * @global_reg_offset: Register offset of DMA global register. * @global_int_clear: Register offset of DMA global interrupt clear. + * @global_ch_fifo_base: Global channel fifo ctrl base offset + * @global_ch_config_base: Global channel config base offset * @ch_req_tx_shift: Register offset for AHUB transmit channel select. * @ch_req_rx_shift: Register offset for AHUB receive channel select. + * @ch_dir_shift: Channel direction bit position. + * @ch_mode_shift: Channel mode bit position. * @ch_base_offset: Register offset of DMA channel registers. + * @ch_tc_offset_diff: From TC register onwards offset differs for Tegra264 * @ch_fifo_ctrl: Default value for channel FIFO CTRL register. + * @ch_config: Outstanding and WRR config values * @ch_req_mask: Mask for Tx or Rx channel select. + * @ch_dir_mask: Mask for channel direction. * @ch_req_max: Maximum number of Tx or Rx channels available. * @ch_reg_size: Size of DMA channel register space. * @nr_channels: Number of DMA channels available. * @ch_fifo_size_mask: Mask for FIFO size field. * @sreq_index_offset: Slave channel index offset. * @max_page: Maximum ADMA Channel Page. - * @has_outstanding_reqs: If DMA channel can have outstanding requests. * @set_global_pg_config: Global page programming. */ struct tegra_adma_chip_data { unsigned int (*adma_get_burst_config)(unsigned int burst_size); unsigned int global_reg_offset; unsigned int global_int_clear; + unsigned int global_ch_fifo_base; + unsigned int global_ch_config_base; unsigned int ch_req_tx_shift; unsigned int ch_req_rx_shift; + unsigned int ch_dir_shift; + unsigned int ch_mode_shift; unsigned int ch_base_offset; + unsigned int ch_tc_offset_diff; unsigned int ch_fifo_ctrl; + unsigned int ch_config; unsigned int ch_req_mask; + unsigned int ch_dir_mask; unsigned int ch_req_max; unsigned int ch_reg_size; unsigned int nr_channels; unsigned int ch_fifo_size_mask; unsigned int sreq_index_offset; unsigned int max_page; - bool has_outstanding_reqs; void (*set_global_pg_config)(struct tegra_adma *tdma); }; =20 @@ -112,6 +136,7 @@ struct tegra_adma_chip_data { struct tegra_adma_chan_regs { unsigned int ctrl; unsigned int config; + unsigned int global_config; unsigned int src_addr; unsigned int trg_addr; unsigned int fifo_ctrl; @@ -150,6 +175,9 @@ struct tegra_adma_chan { /* Transfer count and position info */ unsigned int tx_buf_count; unsigned int tx_buf_pos; + + unsigned int global_ch_fifo_offset; + unsigned int global_ch_config_offset; }; =20 /* @@ -246,6 +274,29 @@ static void tegra186_adma_global_page_config(struct te= gra_adma *tdma) tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ + (tdma->ch_page_no * 0= x4), 0xffffff); } =20 +static void tegra264_adma_global_page_config(struct tegra_adma *tdma) +{ + u32 global_page_offset =3D tdma->ch_page_no * TEGRA264_ADMA_GLOBAL_PAGE_O= FFSET; + + /* If the default page (page1) is not used, then clear page1 registers */ + if (tdma->ch_page_no) { + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0, 0); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1, 0); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0, 0); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1, 0); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0, 0); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1, 0); + } + + /* Program global registers for selected page */ + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0 + global_page_offset, = 0xffffffff); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1 + global_page_offset, = 0xffffffff); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0 + global_page_offset,= 0xffffffff); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1 + global_page_offset,= 0x1); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0 + global_page_offset,= 0xffffffff); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1 + global_page_offset,= 0x1); +} + static int tegra_adma_init(struct tegra_adma *tdma) { u32 status; @@ -404,11 +455,21 @@ static void tegra_adma_start(struct tegra_adma_chan *= tdc) =20 tdc->tx_buf_pos =3D 0; tdc->tx_buf_count =3D 0; - tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc); + tdma_ch_write(tdc, ADMA_CH_TC - tdc->tdma->cdata->ch_tc_offset_diff, ch_r= egs->tc); tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); - tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr); - tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr); - tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl); + tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR - tdc->tdma->cdata->ch_tc_offse= t_diff, + ch_regs->src_addr); + tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR - tdc->tdma->cdata->ch_tc_offse= t_diff, + ch_regs->trg_addr); + + if (!tdc->tdma->cdata->global_ch_fifo_base) + tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl); + else if (tdc->global_ch_fifo_offset) + tdma_write(tdc->tdma, tdc->global_ch_fifo_offset, ch_regs->fifo_ctrl); + + if (tdc->global_ch_config_offset) + tdma_write(tdc->tdma, tdc->global_ch_config_offset, ch_regs->global_conf= ig); + tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config); =20 /* Start ADMA */ @@ -421,7 +482,8 @@ static unsigned int tegra_adma_get_residue(struct tegra= _adma_chan *tdc) { struct tegra_adma_desc *desc =3D tdc->desc; unsigned int max =3D ADMA_CH_XFER_STATUS_COUNT_MASK + 1; - unsigned int pos =3D tdma_ch_read(tdc, ADMA_CH_XFER_STATUS); + unsigned int pos =3D tdma_ch_read(tdc, ADMA_CH_XFER_STATUS - + tdc->tdma->cdata->ch_tc_offset_diff); unsigned int periods_remaining; =20 /* @@ -627,13 +689,16 @@ static int tegra_adma_set_xfer_params(struct tegra_ad= ma_chan *tdc, return -EINVAL; } =20 - ch_regs->ctrl |=3D ADMA_CH_CTRL_DIR(adma_dir) | - ADMA_CH_CTRL_MODE_CONTINUOUS | + ch_regs->ctrl |=3D ADMA_CH_CTRL_DIR(adma_dir, cdata->ch_dir_mask, + cdata->ch_dir_shift) | + ADMA_CH_CTRL_MODE_CONTINUOUS(cdata->ch_mode_shift) | ADMA_CH_CTRL_FLOWCTRL_EN; ch_regs->config |=3D cdata->adma_get_burst_config(burst_size); - ch_regs->config |=3D ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1); - if (cdata->has_outstanding_reqs) - ch_regs->config |=3D TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8); + + if (cdata->global_ch_config_base) + ch_regs->global_config |=3D cdata->ch_config; + else + ch_regs->config |=3D cdata->ch_config; =20 /* * 'sreq_index' represents the current ADMAIF channel number and as per @@ -788,12 +853,23 @@ static int __maybe_unused tegra_adma_runtime_suspend(= struct device *dev) /* skip if channel is not active */ if (!ch_reg->cmd) continue; - ch_reg->tc =3D tdma_ch_read(tdc, ADMA_CH_TC); - ch_reg->src_addr =3D tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR); - ch_reg->trg_addr =3D tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR); + ch_reg->tc =3D tdma_ch_read(tdc, ADMA_CH_TC - tdma->cdata->ch_tc_offset_= diff); + ch_reg->src_addr =3D tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR - + tdma->cdata->ch_tc_offset_diff); + ch_reg->trg_addr =3D tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR - + tdma->cdata->ch_tc_offset_diff); ch_reg->ctrl =3D tdma_ch_read(tdc, ADMA_CH_CTRL); - ch_reg->fifo_ctrl =3D tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL); + + if (tdc->global_ch_config_offset) + ch_reg->global_config =3D tdma_read(tdc->tdma, tdc->global_ch_config_of= fset); + + if (!tdc->tdma->cdata->global_ch_fifo_base) + ch_reg->fifo_ctrl =3D tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL); + else if (tdc->global_ch_fifo_offset) + ch_reg->fifo_ctrl =3D tdma_read(tdc->tdma, tdc->global_ch_fifo_offset); + ch_reg->config =3D tdma_ch_read(tdc, ADMA_CH_CONFIG); + } =20 clk_disable: @@ -832,12 +908,23 @@ static int __maybe_unused tegra_adma_runtime_resume(s= truct device *dev) /* skip if channel was not active earlier */ if (!ch_reg->cmd) continue; - tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc); - tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr); - tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr); + tdma_ch_write(tdc, ADMA_CH_TC - tdma->cdata->ch_tc_offset_diff, ch_reg->= tc); + tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR - tdma->cdata->ch_tc_offset_di= ff, + ch_reg->src_addr); + tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR - tdma->cdata->ch_tc_offset_di= ff, + ch_reg->trg_addr); tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl); - tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl); + + if (!tdc->tdma->cdata->global_ch_fifo_base) + tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl); + else if (tdc->global_ch_fifo_offset) + tdma_write(tdc->tdma, tdc->global_ch_fifo_offset, ch_reg->fifo_ctrl); + + if (tdc->global_ch_config_offset) + tdma_write(tdc->tdma, tdc->global_ch_config_offset, ch_reg->global_conf= ig); + tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config); + tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd); } =20 @@ -848,17 +935,23 @@ static const struct tegra_adma_chip_data tegra210_chi= p_data =3D { .adma_get_burst_config =3D tegra210_adma_get_burst_config, .global_reg_offset =3D 0xc00, .global_int_clear =3D 0x20, + .global_ch_fifo_base =3D 0, + .global_ch_config_base =3D 0, .ch_req_tx_shift =3D 28, .ch_req_rx_shift =3D 24, + .ch_dir_shift =3D 12, + .ch_mode_shift =3D 8, .ch_base_offset =3D 0, + .ch_tc_offset_diff =3D 0, + .ch_config =3D ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1), .ch_req_mask =3D 0xf, + .ch_dir_mask =3D 0xf, .ch_req_max =3D 10, .ch_reg_size =3D 0x80, .nr_channels =3D 22, .ch_fifo_size_mask =3D 0xf, .sreq_index_offset =3D 2, .max_page =3D 0, - .has_outstanding_reqs =3D false, .set_global_pg_config =3D NULL, }; =20 @@ -866,23 +959,56 @@ static const struct tegra_adma_chip_data tegra186_chi= p_data =3D { .adma_get_burst_config =3D tegra186_adma_get_burst_config, .global_reg_offset =3D 0, .global_int_clear =3D 0x402c, + .global_ch_fifo_base =3D 0, + .global_ch_config_base =3D 0, .ch_req_tx_shift =3D 27, .ch_req_rx_shift =3D 22, + .ch_dir_shift =3D 12, + .ch_mode_shift =3D 8, .ch_base_offset =3D 0x10000, + .ch_tc_offset_diff =3D 0, + .ch_config =3D ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1) | + TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8), .ch_req_mask =3D 0x1f, + .ch_dir_mask =3D 0xf, .ch_req_max =3D 20, .ch_reg_size =3D 0x100, .nr_channels =3D 32, .ch_fifo_size_mask =3D 0x1f, .sreq_index_offset =3D 4, .max_page =3D 4, - .has_outstanding_reqs =3D true, .set_global_pg_config =3D tegra186_adma_global_page_config, }; =20 +static const struct tegra_adma_chip_data tegra264_chip_data =3D { + .adma_get_burst_config =3D tegra186_adma_get_burst_config, + .global_reg_offset =3D 0, + .global_int_clear =3D 0x800c, + .global_ch_fifo_base =3D ADMA_GLOBAL_CH_FIFO_CTRL, + .global_ch_config_base =3D ADMA_GLOBAL_CH_CONFIG, + .ch_req_tx_shift =3D 26, + .ch_req_rx_shift =3D 20, + .ch_dir_shift =3D 10, + .ch_mode_shift =3D 7, + .ch_base_offset =3D 0x10000, + .ch_tc_offset_diff =3D 4, + .ch_config =3D ADMA_GLOBAL_CH_CONFIG_WEIGHT_FOR_WRR(1) | + ADMA_GLOBAL_CH_CONFIG_OUTSTANDING_REQS(8), + .ch_req_mask =3D 0x3f, + .ch_dir_mask =3D 7, + .ch_req_max =3D 32, + .ch_reg_size =3D 0x100, + .nr_channels =3D 64, + .ch_fifo_size_mask =3D 0x7f, + .sreq_index_offset =3D 0, + .max_page =3D 10, + .set_global_pg_config =3D tegra264_adma_global_page_config, +}; + static const struct of_device_id tegra_adma_of_match[] =3D { { .compatible =3D "nvidia,tegra210-adma", .data =3D &tegra210_chip_data }, { .compatible =3D "nvidia,tegra186-adma", .data =3D &tegra186_chip_data }, + { .compatible =3D "nvidia,tegra264-adma", .data =3D &tegra264_chip_data }, { }, }; MODULE_DEVICE_TABLE(of, tegra_adma_of_match); @@ -985,6 +1111,15 @@ static int tegra_adma_probe(struct platform_device *p= dev) =20 tdc->chan_addr =3D tdma->ch_base_addr + (cdata->ch_reg_size * i); =20 + if (tdma->base_addr) { + if (cdata->global_ch_fifo_base) + tdc->global_ch_fifo_offset =3D cdata->global_ch_fifo_base + (4 * i); + + if (cdata->global_ch_config_base) + tdc->global_ch_config_offset =3D + cdata->global_ch_config_base + (4 * i); + } + tdc->irq =3D of_irq_get(pdev->dev.of_node, i); if (tdc->irq <=3D 0) { ret =3D tdc->irq ?: -ENXIO; --=20 2.17.1