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Sun, 11 May 2025 10:27:58 -0700 (PDT) From: Da Xue To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: Da Xue , stable@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: meson-g12a: fix missing spicc clks to clk_sel Date: Sun, 11 May 2025 13:27:32 -0400 Message-Id: <20250511172732.1467671-1-da@libre.computer> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" HHI_SPICC_CLK_CNTL bits 25:23 controls spicc clk_sel. It is missing fclk_div 2 and gp0_pll which causes the spicc module to output the incorrect clocks for spicc sclk at 2.5x the expected rate. Add the missing clocks resolves this. Cc: # 6.1.x: a18c8e0: clk: meson: g12a: add Signed-off-by: Da Xue --- drivers/clk/meson/g12a.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 4f92b83965d5a..892862bf39996 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4099,8 +4099,10 @@ static const struct clk_parent_data spicc_sclk_paren= t_data[] =3D { { .hw =3D &g12a_clk81.hw }, { .hw =3D &g12a_fclk_div4.hw }, { .hw =3D &g12a_fclk_div3.hw }, + { .hw =3D &g12a_fclk_div2.hw }, { .hw =3D &g12a_fclk_div5.hw }, { .hw =3D &g12a_fclk_div7.hw }, + { .hw =3D &g12a_gp0_pll.hw, }, }; =20 static struct clk_regmap g12a_spicc0_sclk_sel =3D { --=20 2.39.5