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(fttx-pool-194.15.84.99.bambit.de [194.15.84.99]) by mxbox2.masterlogin.de (Postfix) with ESMTPSA id 98F64100500; Sun, 11 May 2025 14:19:57 +0000 (UTC) From: Frank Wunderlich To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Landen Chao , DENG Qingfang , Sean Wang , Daniel Golle , Lorenzo Bianconi , Felix Fietkau , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 06/14] arm64: dts: mediatek: mt7988: add cci node Date: Sun, 11 May 2025 16:19:22 +0200 Message-ID: <20250511141942.10284-7-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> References: <20250511141942.10284-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: beeb7784-23fa-410f-9e58-cc51116d869e Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add cci devicetree node for cpu frequency scaling. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index ab6fc09940b8..64466acb0e71 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -12,6 +12,35 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + cci: cci { + compatible =3D "mediatek,mt8183-cci"; + clocks =3D <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names =3D "cci", "intermediate"; + operating-points-v2 =3D <&cci_opp>; + }; + + cci_opp: opp-table-cci { + compatible =3D "operating-points-v2"; + opp-shared; + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + opp-microvolt =3D <850000>; + }; + opp-660000000 { + opp-hz =3D /bits/ 64 <660000000>; + opp-microvolt =3D <850000>; + }; + opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <850000>; + }; + opp-1080000000 { + opp-hz =3D /bits/ 64 <1080000000>; + opp-microvolt =3D <900000>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -25,6 +54,7 @@ cpu0: cpu@0 { <&topckgen CLK_TOP_XTAL>; clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; + mediatek,cci =3D <&cci>; }; =20 cpu1: cpu@1 { @@ -36,6 +66,7 @@ cpu1: cpu@1 { <&topckgen CLK_TOP_XTAL>; clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; + mediatek,cci =3D <&cci>; }; =20 cpu2: cpu@2 { @@ -47,6 +78,7 @@ cpu2: cpu@2 { <&topckgen CLK_TOP_XTAL>; clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; + mediatek,cci =3D <&cci>; }; =20 cpu3: cpu@3 { @@ -58,6 +90,7 @@ cpu3: cpu@3 { <&topckgen CLK_TOP_XTAL>; clock-names =3D "cpu", "intermediate"; operating-points-v2 =3D <&cluster0_opp>; + mediatek,cci =3D <&cci>; }; =20 cluster0_opp: opp-table-0 { --=20 2.43.0