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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58f2f65sm7701015f8f.55.2025.05.10.15.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 May 2025 15:44:38 -0700 (PDT) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v8 2/7] iio: accel: adxl345: add g-range configuration Date: Sat, 10 May 2025 22:44:00 +0000 Message-Id: <20250510224405.17910-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250510224405.17910-1-l.rubusch@gmail.com> References: <20250510224405.17910-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a mechanism to be able to configure and work with the available g-ranges keeping the precision of 13 digits. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 82 ++++++++++++++++++++++++++++++-- 1 file changed, 79 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index bbdc9d10d962..7c093c0241de 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -83,6 +83,13 @@ enum adxl345_odr { ADXL345_ODR_3200HZ, }; =20 +enum adxl345_range { + ADXL345_2G_RANGE =3D 0, + ADXL345_4G_RANGE, + ADXL345_8G_RANGE, + ADXL345_16G_RANGE, +}; + /* Certain features recommend 12.5 Hz - 400 Hz ODR */ static const int adxl345_odr_tbl[][2] =3D { [ADXL345_ODR_0P10HZ] =3D { 0, 97000 }, @@ -103,6 +110,25 @@ static const int adxl345_odr_tbl[][2] =3D { [ADXL345_ODR_3200HZ] =3D { 3200, 0 }, }; =20 +/* + * Full resolution frequency table: + * (g * 2 * 9.80665) / (2^(resolution) - 1) + * + * resolution :=3D 13 (full) + * g :=3D 2|4|8|16 + * + * 2g at 13bit: 0.004789 + * 4g at 13bit: 0.009578 + * 8g at 13bit: 0.019156 + * 16g at 16bit: 0.038312 + */ +static const int adxl345_fullres_range_tbl[][2] =3D { + [ADXL345_2G_RANGE] =3D { 0, 4789 }, + [ADXL345_4G_RANGE] =3D { 0, 9578 }, + [ADXL345_8G_RANGE] =3D { 0, 19156 }, + [ADXL345_16G_RANGE] =3D { 0, 38312 }, +}; + struct adxl345_state { const struct adxl345_chip_info *info; struct regmap *regmap; @@ -146,7 +172,8 @@ static struct iio_event_spec adxl345_events[] =3D { BIT(IIO_CHAN_INFO_CALIBBIAS), \ .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ BIT(IIO_CHAN_INFO_SAMP_FREQ), \ - .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ .scan_index =3D (index), \ .scan_type =3D { \ .sign =3D 's', \ @@ -446,12 +473,40 @@ static int adxl345_set_odr(struct adxl345_state *st, = enum adxl345_odr odr) FIELD_PREP(ADXL345_BW_RATE_MSK, odr)); } =20 +static int adxl345_find_range(struct adxl345_state *st, int val, int val2, + enum adxl345_range *range) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(adxl345_fullres_range_tbl); i++) { + if (val =3D=3D adxl345_fullres_range_tbl[i][0] && + val2 =3D=3D adxl345_fullres_range_tbl[i][1]) { + *range =3D i; + return 0; + } + } + + return -EINVAL; +} + +static int adxl345_set_range(struct adxl345_state *st, enum adxl345_range = range) +{ + return regmap_update_bits(st->regmap, ADXL345_REG_DATA_FORMAT, + ADXL345_DATA_FORMAT_RANGE, + FIELD_PREP(ADXL345_DATA_FORMAT_RANGE, range)); +} + static int adxl345_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, const int **vals, int *type, int *length, long mask) { switch (mask) { + case IIO_CHAN_INFO_SCALE: + *vals =3D (int *)adxl345_fullres_range_tbl; + *type =3D IIO_VAL_INT_PLUS_MICRO; + *length =3D ARRAY_SIZE(adxl345_fullres_range_tbl) * 2; + return IIO_AVAIL_LIST; case IIO_CHAN_INFO_SAMP_FREQ: *vals =3D (int *)adxl345_odr_tbl; *type =3D IIO_VAL_INT_PLUS_MICRO; @@ -470,6 +525,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, __le16 accel; unsigned int regval; enum adxl345_odr odr; + enum adxl345_range range; int ret; =20 switch (mask) { @@ -488,8 +544,12 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, *val =3D sign_extend32(le16_to_cpu(accel), 12); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - *val =3D 0; - *val2 =3D st->info->uscale; + ret =3D regmap_read(st->regmap, ADXL345_REG_DATA_FORMAT, ®val); + if (ret) + return ret; + range =3D FIELD_GET(ADXL345_DATA_FORMAT_RANGE, regval); + *val =3D adxl345_fullres_range_tbl[range][0]; + *val2 =3D adxl345_fullres_range_tbl[range][1]; return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_CALIBBIAS: ret =3D regmap_read(st->regmap, @@ -521,6 +581,7 @@ static int adxl345_write_raw(struct iio_dev *indio_dev, int val, int val2, long mask) { struct adxl345_state *st =3D iio_priv(indio_dev); + enum adxl345_range range; enum adxl345_odr odr; int ret; =20 @@ -549,6 +610,15 @@ static int adxl345_write_raw(struct iio_dev *indio_dev, if (ret) return ret; break; + case IIO_CHAN_INFO_SCALE: + ret =3D adxl345_find_range(st, val, val2, &range); + if (ret) + return ret; + + ret =3D adxl345_set_range(st, range); + if (ret) + return ret; + break; default: return -EINVAL; } @@ -741,6 +811,8 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *in= dio_dev, switch (mask) { case IIO_CHAN_INFO_CALIBBIAS: return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_SAMP_FREQ: return IIO_VAL_INT_PLUS_MICRO; default: @@ -1083,6 +1155,10 @@ int adxl345_core_probe(struct device *dev, struct re= gmap *regmap, if (ret) return ret; =20 + ret =3D adxl345_set_range(st, ADXL345_16G_RANGE); + if (ret) + return ret; + /* Reset interrupts at start up */ ret =3D regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, 0x00); if (ret) --=20 2.39.5