From nobody Fri Dec 19 20:17:56 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 926F6243969; Sat, 10 May 2025 16:07:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746893270; cv=none; b=Xd1m4McQqj6yj3I86WNA3IGtgK2AQuS9pt+Lw5Rrij1T3wdo5vEbMVsOXtIbeBfr8AOJCAXd7bMu9o7frZZVpQk6Pg5A/QTtvJW0xuIYK7MekJjAu/I+TndPpJeq7Wwn6dA57dN3jXtK5jug8IycDdOM785C2XamqdyTBYVjG38= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746893270; c=relaxed/simple; bh=COYdjABTbj/L1KY49fqz47Uudxe0ZoHw7lbgofv4Nl0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tVdkvUrpOIHS/ZLCg7+13gKrr4+v/AWkQFRwpaP+YVjKsUICmiwKc6lvcqCdJFea6/mW2eka4j6sK6wYkBjfX9wpk+K5cEViR1sNuFQLt83su+8YRco2ZryQ7LLpyq0ayqL2R0DYVLDeMFdqnaTw3HtkukGIr6ozaFGDP7b6HKg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=L7ENU4Y7; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="L7ENU4Y7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=MK Oa41nArLvMyue+KJdVlI6cChmPe7CatpXqtb1g9ZU=; b=L7ENU4Y7eCtFo/DCz1 7fBVjQUA/xQgAfDWe8uVU/vPXB0EhbaEZqqidP0N3nKdD05nsKt2NiZetytBh0r/ IaxWqhp3vAcM4siGejk50H0FEgb3anEpvqAu+vyb7vut/n6Ri8pnqp902f/83c6R R7ph7LUCwKB1Jb1+adOReax2g= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgD36iuveR9o3J32AA--.26781S3; Sun, 11 May 2025 00:07:14 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, jingoohan1@gmail.com, manivannan.sadhasivam@linaro.org Cc: cassel@kernel.org, robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [RESEND PATCH v2 1/3] PCI: dwc: Standardize link status check to return bool Date: Sun, 11 May 2025 00:07:08 +0800 Message-Id: <20250510160710.392122-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250510160710.392122-1-18255117159@163.com> References: <20250510160710.392122-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgD36iuveR9o3J32AA--.26781S3 X-Coremail-Antispam: 1Uf129KBjvAXoW3CryfuFy5Cw43uw4xKFyxAFb_yoW8Wr1xZo Z3Xw1fC3W7Wr1xXryxJ3ZIgFyUZ3ZFvFW3tFsY9rs8Za43AFn5trW3Wr15uw15uw40k34U Zw4DJwnxAr4Ivr1Un29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4RD8n5DUUUU X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxxJo2gfb9Tk2AAAsd Content-Type: text/plain; charset="utf-8" Modify link_up functions across multiple DWC PCIe controllers to return bool instead of int. Simplify conditional checks by directly returning logical evaluations. This improves code clarity and aligns with PCIe status semantics. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Manivannan Sadhasivam Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pci-dra7xx.c | 4 ++-- drivers/pci/controller/dwc/pci-exynos.c | 4 ++-- drivers/pci/controller/dwc/pci-keystone.c | 5 ++--- drivers/pci/controller/dwc/pci-meson.c | 6 +++--- drivers/pci/controller/dwc/pcie-armada8k.c | 6 +++--- drivers/pci/controller/dwc/pcie-designware.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 4 ++-- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- drivers/pci/controller/dwc/pcie-histb.c | 9 +++------ drivers/pci/controller/dwc/pcie-keembay.c | 2 +- drivers/pci/controller/dwc/pcie-kirin.c | 7 ++----- drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +- drivers/pci/controller/dwc/pcie-qcom.c | 4 ++-- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- drivers/pci/controller/dwc/pcie-spear13xx.c | 7 ++----- drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++-- drivers/pci/controller/dwc/pcie-uniphier.c | 2 +- drivers/pci/controller/dwc/pcie-visconti.c | 4 ++-- 18 files changed, 33 insertions(+), 43 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controll= er/dwc/pci-dra7xx.c index 33d6bf460ffe..58f7d04ff37f 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -118,12 +118,12 @@ static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie = *pci, u64 cpu_addr) return cpu_addr & DRA7XX_CPU_TO_BUS_ADDR; } =20 -static int dra7xx_pcie_link_up(struct dw_pcie *pci) +static bool dra7xx_pcie_link_up(struct dw_pcie *pci) { struct dra7xx_pcie *dra7xx =3D to_dra7xx_pcie(pci); u32 reg =3D dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); =20 - return !!(reg & LINK_UP); + return reg & LINK_UP; } =20 static void dra7xx_pcie_stop_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index ace736b025b1..1f0e98d07109 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -209,12 +209,12 @@ static struct pci_ops exynos_pci_ops =3D { .write =3D exynos_pcie_wr_own_conf, }; =20 -static int exynos_pcie_link_up(struct dw_pcie *pci) +static bool exynos_pcie_link_up(struct dw_pcie *pci) { struct exynos_pcie *ep =3D to_exynos_pcie(pci); u32 val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); =20 - return (val & PCIE_ELBI_XMLH_LINKUP); + return val & PCIE_ELBI_XMLH_LINKUP; } =20 static int exynos_pcie_host_init(struct dw_pcie_rp *pp) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/contro= ller/dwc/pci-keystone.c index 76a37368ae4f..968464530e3d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -492,13 +492,12 @@ static struct pci_ops ks_pcie_ops =3D { * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCI= e host * controller driver information. */ -static int ks_pcie_link_up(struct dw_pcie *pci) +static bool ks_pcie_link_up(struct dw_pcie *pci) { u32 val; =20 val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); - val &=3D PORT_LOGIC_LTSSM_STATE_MASK; - return (val =3D=3D PORT_LOGIC_LTSSM_STATE_L0); + return (val & PORT_LOGIC_LTSSM_STATE_MASK) =3D=3D PORT_LOGIC_LTSSM_STATE_= L0; } =20 static void ks_pcie_stop_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controlle= r/dwc/pci-meson.c index db9482a113e9..787469d1b396 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -335,7 +335,7 @@ static struct pci_ops meson_pci_ops =3D { .write =3D pci_generic_config_write, }; =20 -static int meson_pcie_link_up(struct dw_pcie *pci) +static bool meson_pcie_link_up(struct dw_pcie *pci) { struct meson_pcie *mp =3D to_meson_pcie(pci); struct device *dev =3D pci->dev; @@ -363,7 +363,7 @@ static int meson_pcie_link_up(struct dw_pcie *pci) dev_dbg(dev, "speed_okay\n"); =20 if (smlh_up && rdlh_up && ltssm_up && speed_okay) - return 1; + return true; =20 cnt++; =20 @@ -371,7 +371,7 @@ static int meson_pcie_link_up(struct dw_pcie *pci) } while (cnt < WAIT_LINKUP_TIMEOUT); =20 dev_err(dev, "error: wait linkup timeout\n"); - return 0; + return false; } =20 static int meson_pcie_host_init(struct dw_pcie_rp *pp) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/contr= oller/dwc/pcie-armada8k.c index b5c599ccaacf..c2650fd0d458 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -139,7 +139,7 @@ static int armada8k_pcie_setup_phys(struct armada8k_pci= e *pcie) return ret; } =20 -static int armada8k_pcie_link_up(struct dw_pcie *pci) +static bool armada8k_pcie_link_up(struct dw_pcie *pci) { u32 reg; u32 mask =3D PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; @@ -147,10 +147,10 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci) reg =3D dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG); =20 if ((reg & mask) =3D=3D mask) - return 1; + return true; =20 dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg); - return 0; + return false; } =20 static int armada8k_pcie_start_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 97d76d3dc066..b3615d125942 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -711,7 +711,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) } EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link); =20 -int dw_pcie_link_up(struct dw_pcie *pci) +bool dw_pcie_link_up(struct dw_pcie *pci) { u32 val; =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 56aafdbcdaca..4dd16aa4b39e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -462,7 +462,7 @@ struct dw_pcie_ops { size_t size, u32 val); void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, size_t size, u32 val); - int (*link_up)(struct dw_pcie *pcie); + bool (*link_up)(struct dw_pcie *pcie); enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); @@ -537,7 +537,7 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val= ); u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size); void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val); void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val= ); -int dw_pcie_link_up(struct dw_pcie *pci); +bool dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 3c6ab71c996e..ae171a545df6 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -183,7 +183,7 @@ static void rockchip_pcie_disable_ltssm(struct rockchip= _pcie *rockchip) PCIE_CLIENT_GENERAL_CON); } =20 -static int rockchip_pcie_link_up(struct dw_pcie *pci) +static bool rockchip_pcie_link_up(struct dw_pcie *pci) { struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); u32 val =3D rockchip_pcie_get_ltssm(rockchip); diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controll= er/dwc/pcie-histb.c index 1f2f4c28a949..a52071589377 100644 --- a/drivers/pci/controller/dwc/pcie-histb.c +++ b/drivers/pci/controller/dwc/pcie-histb.c @@ -151,7 +151,7 @@ static struct pci_ops histb_pci_ops =3D { .write =3D histb_pcie_wr_own_conf, }; =20 -static int histb_pcie_link_up(struct dw_pcie *pci) +static bool histb_pcie_link_up(struct dw_pcie *pci) { struct histb_pcie *hipcie =3D to_histb_pcie(pci); u32 regval; @@ -160,11 +160,8 @@ static int histb_pcie_link_up(struct dw_pcie *pci) regval =3D histb_pcie_readl(hipcie, PCIE_SYS_STAT0); status =3D histb_pcie_readl(hipcie, PCIE_SYS_STAT4); status &=3D PCIE_LTSSM_STATE_MASK; - if ((regval & PCIE_XMLH_LINK_UP) && (regval & PCIE_RDLH_LINK_UP) && - (status =3D=3D PCIE_LTSSM_STATE_ACTIVE)) - return 1; - - return 0; + return ((regval & PCIE_XMLH_LINK_UP) && (regval & PCIE_RDLH_LINK_UP) && + (status =3D=3D PCIE_LTSSM_STATE_ACTIVE)); } =20 static int histb_pcie_start_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/contro= ller/dwc/pcie-keembay.c index 278205db60a2..67dd3337b447 100644 --- a/drivers/pci/controller/dwc/pcie-keembay.c +++ b/drivers/pci/controller/dwc/pcie-keembay.c @@ -101,7 +101,7 @@ static void keembay_pcie_ltssm_set(struct keembay_pcie = *pcie, bool enable) writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); } =20 -static int keembay_pcie_link_up(struct dw_pcie *pci) +static bool keembay_pcie_link_up(struct dw_pcie *pci) { struct keembay_pcie *pcie =3D dev_get_drvdata(pci->dev); u32 val; diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controll= er/dwc/pcie-kirin.c index d0e6a3811b00..91559c8b1866 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -586,16 +586,13 @@ static void kirin_pcie_write_dbi(struct dw_pcie *pci,= void __iomem *base, kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false); } =20 -static int kirin_pcie_link_up(struct dw_pcie *pci) +static bool kirin_pcie_link_up(struct dw_pcie *pci) { struct kirin_pcie *kirin_pcie =3D to_kirin_pcie(pci); u32 val; =20 regmap_read(kirin_pcie->apb, PCIE_APB_PHY_STATUS0, &val); - if ((val & PCIE_LINKUP_ENABLE) =3D=3D PCIE_LINKUP_ENABLE) - return 1; - - return 0; + return (val & PCIE_LINKUP_ENABLE) =3D=3D PCIE_LINKUP_ENABLE; } =20 static int kirin_pcie_start_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 46b1c6d19974..b3f7f42fa852 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -261,7 +261,7 @@ static void qcom_pcie_ep_configure_tcsr(struct qcom_pci= e_ep *pcie_ep) } } =20 -static int qcom_pcie_dw_link_up(struct dw_pcie *pci) +static bool qcom_pcie_dw_link_up(struct dw_pcie *pci) { struct qcom_pcie_ep *pcie_ep =3D to_pcie_ep(pci); u32 reg; diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index dc98ae63362d..ba0dd1717a58 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1221,12 +1221,12 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pc= ie *pcie) return 0; } =20 -static int qcom_pcie_link_up(struct dw_pcie *pci) +static bool qcom_pcie_link_up(struct dw_pcie *pci) { u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u16 val =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); =20 - return !!(val & PCI_EXP_LNKSTA_DLLLA); + return val & PCI_EXP_LNKSTA_DLLLA; } =20 static int qcom_pcie_host_init(struct dw_pcie_rp *pp) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index fc872dd35029..ccb94f4a215f 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -87,7 +87,7 @@ struct rcar_gen4_pcie { #define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw) =20 /* Common */ -static int rcar_gen4_pcie_link_up(struct dw_pcie *dw) +static bool rcar_gen4_pcie_link_up(struct dw_pcie *dw) { struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); u32 val, mask; diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/cont= roller/dwc/pcie-spear13xx.c index ff986ced56b2..01794a9d3ad2 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -110,15 +110,12 @@ static void spear13xx_pcie_enable_interrupts(struct s= pear13xx_pcie *spear13xx_pc MSI_CTRL_INT, &app_reg->int_mask); } =20 -static int spear13xx_pcie_link_up(struct dw_pcie *pci) +static bool spear13xx_pcie_link_up(struct dw_pcie *pci) { struct spear13xx_pcie *spear13xx_pcie =3D to_spear13xx_pcie(pci); struct pcie_app_reg __iomem *app_reg =3D spear13xx_pcie->app_base; =20 - if (readl(&app_reg->app_status_1) & XMLH_LINK_UP) - return 1; - - return 0; + return readl(&app_reg->app_status_1) & XMLH_LINK_UP; } =20 static int spear13xx_pcie_host_init(struct dw_pcie_rp *pp) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 5103995cd6c7..55c47318e65a 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1027,12 +1027,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie = *pci) return 0; } =20 -static int tegra_pcie_dw_link_up(struct dw_pcie *pci) +static bool tegra_pcie_dw_link_up(struct dw_pcie *pci) { struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); u32 val =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); =20 - return !!(val & PCI_EXP_LNKSTA_DLLLA); + return val & PCI_EXP_LNKSTA_DLLLA; } =20 static void tegra_pcie_dw_stop_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/contr= oller/dwc/pcie-uniphier.c index 5757ca3803c9..9d05b3a0579e 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -135,7 +135,7 @@ static int uniphier_pcie_wait_rc(struct uniphier_pcie *= pcie) return 0; } =20 -static int uniphier_pcie_link_up(struct dw_pcie *pci) +static bool uniphier_pcie_link_up(struct dw_pcie *pci) { struct uniphier_pcie *pcie =3D to_uniphier_pcie(pci); u32 val, mask; diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/contr= oller/dwc/pcie-visconti.c index 318c278e65c8..cdeac6177143 100644 --- a/drivers/pci/controller/dwc/pcie-visconti.c +++ b/drivers/pci/controller/dwc/pcie-visconti.c @@ -121,13 +121,13 @@ static u32 visconti_mpu_readl(struct visconti_pcie *p= cie, u32 reg) return readl_relaxed(pcie->mpu_base + reg); } =20 -static int visconti_pcie_link_up(struct dw_pcie *pci) +static bool visconti_pcie_link_up(struct dw_pcie *pci) { struct visconti_pcie *pcie =3D dev_get_drvdata(pci->dev); void __iomem *addr =3D pcie->ulreg_base; u32 val =3D readl_relaxed(addr + PCIE_UL_REG_V_PHY_ST_02); =20 - return !!(val & PCIE_UL_S_L0); + return val & PCIE_UL_S_L0; } =20 static int visconti_pcie_start_link(struct dw_pcie *pci) --=20 2.25.1 From nobody Fri Dec 19 20:17:56 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DC50D131E2D; Sat, 10 May 2025 16:07:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746893258; cv=none; b=DoR/yZw448fDqFGHTyElKIdJ27H7aejAwYny0+yeedzpkR5CDSAXHHMH/a0Yj4wI5PxKC7HVWcB3Pyme6lvYHWwiqEYcCjkthf7pSz2GHP6TzqBbcFfjkk8J+hgoTv9RX8CV6fXvaWUsTemrDbM4G0AN2d6lSMA+DY8Jtp4W7UM= ARC-Message-Signature: i=1; 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charset="utf-8" Update ls_g4_pcie_link_up() to return bool and simplify the LTSSM state check. Align function signature in pcie-mobiveil.h to match the change, ensuring consistency across the Mobiveil PCIe driver. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Manivannan Sadhasivam Reviewed-by: Niklas Cassel --- drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c | 9 ++------- drivers/pci/controller/mobiveil/pcie-mobiveil.h | 2 +- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c b/drive= rs/pci/controller/mobiveil/pcie-layerscape-gen4.c index 5af22bee913b..1cf014051296 100644 --- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c @@ -53,18 +53,13 @@ static inline void ls_g4_pcie_pf_writel(struct ls_g4_pc= ie *pcie, iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); } =20 -static int ls_g4_pcie_link_up(struct mobiveil_pcie *pci) +static bool ls_g4_pcie_link_up(struct mobiveil_pcie *pci) { struct ls_g4_pcie *pcie =3D to_ls_g4_pcie(pci); u32 state; =20 state =3D ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); - state =3D state & PF_DBG_LTSSM_MASK; - - if (state =3D=3D PF_DBG_LTSSM_L0) - return 1; - - return 0; + return (state & PF_DBG_LTSSM_MASK) =3D=3D PF_DBG_LTSSM_L0; } =20 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/= controller/mobiveil/pcie-mobiveil.h index e63abb887ee3..662f17f9bf65 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -160,7 +160,7 @@ struct mobiveil_root_port { }; =20 struct mobiveil_pab_ops { - int (*link_up)(struct mobiveil_pcie *pcie); + bool (*link_up)(struct mobiveil_pcie *pcie); }; =20 struct mobiveil_pcie { --=20 2.25.1 From nobody Fri Dec 19 20:17:56 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2996D3A8F7; Sat, 10 May 2025 16:07:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="PGysKsT5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Hq qdK6+riiyILhRulkBMgu4uU7kcJMGEIBbmscsRpQ0=; b=PGysKsT5ERoK8btQi7 66imDiC6sMwwV9IfWPpD/wg7vmTnXG/QXss8kQ2NztHTOzdHOlcHFQFWNoCGTaVS mVvexXxSm92VQ2Pr2FZhSh8kWVbKTh6yfWd9Dxtq6hKyUEYc8jeHc9DfB27mEh3a cmPv4CwMWeI6ekZSRy5smQP7A= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgD36iuveR9o3J32AA--.26781S5; Sun, 11 May 2025 00:07:16 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, jingoohan1@gmail.com, manivannan.sadhasivam@linaro.org Cc: cassel@kernel.org, robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [RESEND PATCH v2 3/3] PCI: cadence: Simplify j721e link status check Date: Sun, 11 May 2025 00:07:10 +0800 Message-Id: <20250510160710.392122-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250510160710.392122-1-18255117159@163.com> References: <20250510160710.392122-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgD36iuveR9o3J32AA--.26781S5 X-Coremail-Antispam: 1Uf129KBjvdXoWruryDKrWxAr1kJF15ZFW5ZFb_yoWkJFX_ZF 1FvF4IyFsrurZIkFyayFWayFyrAay2va12ga93t3WfAFyxGr4UAF1UZrWDWa4xua15AFn8 Aw1qqFn8AryqvjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7xRi-tI7UUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDxJJo2gfd4Y4tQACs+ Content-Type: text/plain; charset="utf-8" Replace explicit if-else condition with direct return statement in j721e_pcie_link_up(). This reduces code verbosity while maintaining the same logic for detecting PCIe link completion. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Manivannan Sadhasivam Reviewed-by: Niklas Cassel --- drivers/pci/controller/cadence/pci-j721e.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/contr= oller/cadence/pci-j721e.c index ef1cfdae33bb..bea1944a7eb2 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -153,11 +153,7 @@ static bool j721e_pcie_link_up(struct cdns_pcie *cdns_= pcie) u32 reg; =20 reg =3D j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); - reg &=3D LINK_STATUS; - if (reg =3D=3D LINK_UP_DL_COMPLETED) - return true; - - return false; + return (reg & LINK_STATUS) =3D=3D LINK_UP_DL_COMPLETED; } =20 static const struct cdns_pcie_ops j721e_pcie_ops =3D { --=20 2.25.1