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Fri, 09 May 2025 08:36:02 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 1/2] arm64: dts: renesas: r9a09g057: Add GBETH nodes Date: Fri, 9 May 2025 16:35:58 +0100 Message-ID: <20250509153559.326603-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509153559.326603-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250509153559.326603-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Renesas RZ/V2H(P) SoC is equipped with 2x Synopsys DesignWare Ethernet Quality-of-Service IP block version 5.20. Add GBETH nodes to R9A09G057 RZ/V2H(P) SoC DTSI. Signed-off-by: Lad Prabhakar --- v1->v2: - Added missing power-domains property to the GBETH nodes. - Fixed interrupt number 745 to 775 in eth0 node. - Added snps,rx-sched-sp property to mtl_rx_setup1 --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 197 +++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index 18ab5639b301..69964b313e38 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -701,6 +701,203 @@ sdhi2_vqmmc: vqmmc-regulator { status =3D "disabled"; }; }; + + eth0: ethernet@15c30000 { + compatible =3D "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", + "snps,dwmac-5.20"; + reg =3D <0 0x15c30000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3"; + clocks =3D <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, + <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180"; + resets =3D <&cpg 0xb0>; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <128>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup0>; + snps,mtl-tx-config =3D <&mtl_tx_setup0>; + snps,txpbl =3D <32>; + snps,rxpbl =3D <32>; + status =3D "disabled"; + + mtl_rx_setup0: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + }; + + mtl_tx_setup0: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + }; + }; + }; + + eth1: ethernet@15c40000 { + compatible =3D "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", + "snps,dwmac-5.20"; + reg =3D <0 0x15c40000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3"; + clocks =3D <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, + <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180"; + resets =3D <&cpg 0xb1>; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <128>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup1>; + snps,mtl-tx-config =3D <&mtl_tx_setup1>; + snps,txpbl =3D <32>; + snps,rxpbl =3D <32>; + status =3D "disabled"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; 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Fri, 09 May 2025 08:36:04 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:40e3:34f3:a241:140c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ec912sm3550781f8f.23.2025.05.09.08.36.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 May 2025 08:36:03 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 2/2] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable GBETH Date: Fri, 9 May 2025 16:35:59 +0100 Message-ID: <20250509153559.326603-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509153559.326603-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250509153559.326603-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Enable the GBETH nodes on the RZ/V2H Evaluation Kit. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2: - No change. --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 063eca0ba3e2..6b12bdc3eff9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -16,6 +16,8 @@ / { compatible =3D "renesas,rzv2h-evk", "renesas,r9a09g057h44", "renesas,r9a0= 9g057"; =20 aliases { + ethernet0 =3D ð0; + ethernet1 =3D ð1; i2c0 =3D &i2c0; i2c1 =3D &i2c1; i2c2 =3D &i2c2; @@ -78,6 +80,68 @@ &audio_extal_clk { clock-frequency =3D <22579200>; }; =20 +ð0 { + pinctrl-0 =3D <ð0_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + rxc-skew-psec =3D <0>; + txc-skew-psec =3D <0>; + rxdv-skew-psec =3D <0>; + txdv-skew-psec =3D <0>; + rxd0-skew-psec =3D <0>; + rxd1-skew-psec =3D <0>; + rxd2-skew-psec =3D <0>; + rxd3-skew-psec =3D <0>; + txd0-skew-psec =3D <0>; + txd1-skew-psec =3D <0>; + txd2-skew-psec =3D <0>; + txd3-skew-psec =3D <0>; + }; + }; +}; + +ð1 { + pinctrl-0 =3D <ð1_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + rxc-skew-psec =3D <0>; + txc-skew-psec =3D <0>; + rxdv-skew-psec =3D <0>; + txdv-skew-psec =3D <0>; + rxd0-skew-psec =3D <0>; + rxd1-skew-psec =3D <0>; + rxd2-skew-psec =3D <0>; + rxd3-skew-psec =3D <0>; + txd0-skew-psec =3D <0>; + txd1-skew-psec =3D <0>; + txd2-skew-psec =3D <0>; + txd3-skew-psec =3D <0>; + }; + }; +}; + &gpu { status =3D "okay"; mali-supply =3D <®_0p8v>; @@ -172,6 +236,16 @@ &ostm7 { }; =20 &pinctrl { + eth0_pins: eth0 { + pins =3D "ET0_TXC_TXCLK"; + output-enable; + }; + + eth1_pins: eth0 { + pins =3D "ET1_TXC_TXCLK"; + output-enable; + }; + i2c0_pins: i2c0 { pinmux =3D , /* I2C0_SDA */ ; /* I2C0_SCL */ --=20 2.49.0