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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v6 03/14] cxl/pci: Add comments to cxl_hdm_decode_init() Date: Fri, 9 May 2025 17:06:48 +0200 Message-ID: <20250509150700.2817697-4-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250509150700.2817697-1-rrichter@amd.com> References: <20250509150700.2817697-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4D:EE_|PH8PR12MB8607:EE_ X-MS-Office365-Filtering-Correlation-Id: 7b096d34-13fc-4672-52ce-08dd8f0b420f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?IYCeXnd07HGdVJJcJuLsbMIOoLOoKh2e1Kd891ihJm+n7sPRGab9EeQRvm2L?= =?us-ascii?Q?M40Q4j/GSGZ0/pt9Pfu+RJ1Mi4Fada/jSlqBjo0IDIiz7Rug8N4lx0/VEi4o?= =?us-ascii?Q?ZVt9Ux97YqvXyX9gq7987j9NWJBCLjDZ0ZiLmto5g4w8NC1ZEggXOEreGetM?= =?us-ascii?Q?IdDkLbIGJ5HdcemOC5se7PGAHIBeCGxP/8QGT5Z8GWLk3BvOljz0Vs/m+miC?= =?us-ascii?Q?KJxdYi123WaO3hNmyqrZpIH//JV5oRbaTUWpRr+IDbBEhezYUKki8X2XcQkm?= =?us-ascii?Q?x0LN4CCvRWsZPHJHmNoNOF78xSmQFaCkWqaKe8YR3TOxEqQwQSTQwmXaBdln?= =?us-ascii?Q?QTWPgISA2oah/bGZYsnZReu0Lg31Zydm/uuWN/VD386dpnzoQxS7g2V1uIBL?= =?us-ascii?Q?OaE5yoBlqxK1pu4IaInhKHR0Yvo2gN4JY329qhjBlpF9UplX7TzO4vCOnNRJ?= =?us-ascii?Q?jm4PVagpsSI2hAZo583z1J3dkxQy5Au3SVnmKsE4As68VtqcnajkYDGGqT2j?= =?us-ascii?Q?rmcdIPjni7zs4lVNGdU7sl0eIVRUwrbTO7K6itGGC49Znbu1lLpxgZt9BshN?= =?us-ascii?Q?kw6/jmSSqxydUUrYM6isw6+AixbbW8fTFagSaPTogqHO8n/M8fU+tACwFT/r?= =?us-ascii?Q?hq0pULk5ku3Ip2D8KeVHmQ5G5d8IWX10p1GDtz3Aoz84g++3KFQpNkvY/0zM?= =?us-ascii?Q?54jVnVKFrhM3vvuYEY+pV9QSSh4PcMC657o5Pe3ITTdJerZJXhz3PzUZ7OjH?= =?us-ascii?Q?85fSl8WlgZ16eYDIwAUS2I8jjeJDdQu2dd89NPVNWFJmUZ0iqb/Kygn0ehzX?= =?us-ascii?Q?juS2XeCXeIUKrDJQ9dIhI9bjGLr8SjtkcQk+UorlTA4MX8rUgBZ8Afq45k3D?= =?us-ascii?Q?IPrXuapUv6VC07LYXzv2DzAHw7sf5ToX1jI3MwyzIJa6HMVj2X6Qvl9KU6DC?= =?us-ascii?Q?6qkIwnfyTDKtD/LVId6miAmO/HG+ZeXfc9zNzhYQEJOwMhnukbD/fOASJrh4?= =?us-ascii?Q?6QqNfDQxTcJ53c+wTYjqT051ryJTqVxiHeu25mR8Si7DSmo9PFA8wCry5QsX?= =?us-ascii?Q?mtjuK2c0Y9MxMYmMmWvlRAdGmzEETF76UbT++CKgnXXcNdZJHfne3d3/Fsd/?= =?us-ascii?Q?UeKSLKcr+4ETM9Liz1pKxI2oaJTdQCiDTpNzrvFAbg63cDzvKHIiVDjSdfES?= =?us-ascii?Q?wh8kEohfoTRmsCVDaE4ao5x/VElFP0o+bFbo38o3+bueB7tNYfJNqLCPryrD?= =?us-ascii?Q?P0yXC1kO+fyvOb5OJplpSRrgUfiXhVaTWNnBf2VY59k3e6qxs34lSjNpx9Lg?= =?us-ascii?Q?mN6hlPw2/Kf3kYYEjGzcOnuvTNh1uoEdywAQNPGwQMrsZldQSzL/5WWTBla0?= =?us-ascii?Q?7+kWWRrKzFVSTOc/KCotkysiJeD1QQF5xK8Pj7h9SeChSZvOrW2aBM8D5Mnn?= =?us-ascii?Q?VlWsW14JFvE6INwKbmQYcOhv2mJZnYKljKEcPQELykJ2j9Gj1jTZ/ior85rh?= =?us-ascii?Q?ulZwE4t2CmRx3hnzdKM+HclH2pYWII0UDXEC?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2025 15:07:47.1738 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b096d34-13fc-4672-52ce-08dd8f0b420f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8607 Content-Type: text/plain; charset="utf-8" There are various configuration cases of HDM decoder registers causing different code paths. Add comments to cxl_hdm_decode_init() to better explain them. Signed-off-by: Robert Richter Reviewed-by: Gregory Price Reviewed-by: Jonathan Cameron Reviewed-by: Alison Schofield Reviewed-by: Fabio M. De Francesco Reviewed-by: Dave Jiang Tested-by: Gregory Price --- drivers/cxl/core/pci.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 159674c1c71f..b50551601c2e 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -416,9 +416,19 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, s= truct cxl_hdm *cxlhdm, if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled)) return devm_cxl_enable_mem(&port->dev, cxlds); =20 + /* + * If the HDM Decoder Capability does not exist and DVSEC was + * not setup, the DVSEC based emulation cannot be used. + */ if (!hdm) return -ENODEV; =20 + /* The HDM Decoder Capability exists but is globally disabled. */ + + /* + * If the DVSEC CXL Range registers are not enabled, just + * enable and use the HDM Decoder Capability registers. + */ if (!info->mem_enabled) { rc =3D devm_cxl_enable_hdm(&port->dev, cxlhdm); if (rc) @@ -427,6 +437,18 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, s= truct cxl_hdm *cxlhdm, return devm_cxl_enable_mem(&port->dev, cxlds); } =20 + /* + * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base + * [High,Low] when HDM operation is enabled the range register values + * are ignored by the device, but the spec also recommends matching the + * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges + * are expected even though Linux does not require or maintain that + * match. Check if at least one DVSEC range is enabled and allowed by + * the platform. That is, the DVSEC range must be covered by a locked + * platform window (CFMWS). Fail otherwise as the endpoint's decoders + * cannot be used. + */ + root =3D to_cxl_port(port->dev.parent); while (!is_cxl_root(root) && is_cxl_port(root->dev.parent)) root =3D to_cxl_port(root->dev.parent); @@ -454,15 +476,6 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, s= truct cxl_hdm *cxlhdm, return -ENXIO; } =20 - /* - * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base - * [High,Low] when HDM operation is enabled the range register values - * are ignored by the device, but the spec also recommends matching the - * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges - * are expected even though Linux does not require or maintain that - * match. If at least one DVSEC range is enabled and allowed, skip HDM - * Decoder Capability Enable. - */ return 0; } EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, "CXL"); --=20 2.39.5