From nobody Thu Dec 18 05:22:27 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7DCD2918F7; Fri, 9 May 2025 13:43:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746798221; cv=none; b=hItI50GBb3i65hWopJOOPRGJ8/jcqTVhmJz6eCpZimpr14wECmbS+nrpDdRUk0qAwIsWHMbOfd7Ks6+27FeFUilLP4l65br7uzG5cCmMmLSTrXA/zo0ncyjZT8w4jINsgos4sC5SEINPb5DVaAiDowuXhq0Cn4+BuC021kyEESw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746798221; c=relaxed/simple; bh=25wuGjcEnHJs0CyN6DJPzJhibjHc2PUKQ1DFfOxJ0YA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hOsFiWArAe7WTGQQsnBmlxlbeVjhUICblH9YHuOc2VA1SRSKphgz/EFaBFfoiiYNn3V8Dz+J87EMPkz3mZKNxgrEH+0v6J+gqb4XvTBqHNr16scpnB27MVLm0eN96bnKrF/R6w0V7gBgB2LA81zmxSSwKaHI6v0GvXd2otPDehU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bxqIDJic; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bxqIDJic" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746798218; x=1778334218; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=25wuGjcEnHJs0CyN6DJPzJhibjHc2PUKQ1DFfOxJ0YA=; b=bxqIDJicNhdCvVZkIyZhWIRMyomya4vIgDifGxkd6+olOmQaUcfpn8yV fdk803OAx8g7U0hAMHEk9UzTAXU+7cdvz4tOY7kDzfELfi1+/sFjj9XGG C+rdtLho45PZJAsQzwdZsiTVhhb7WmDmWDLZ20qt18tqWvQAmSt3pQdve T3eDdFADWO3yxrb59JKd6KlV5WA4xQXjfzP81ZpFNyA7hJ1Q+mVkT8ekE MoGChxsRl9nCgM/aKCKdALz3QLdh7Ku1vKijyMcHCM0DDF+L5zvbi4KzO zkydxhxt2OhHdLyTetTVRfdzuxnME78MRRuWYMA2aUclCFgogvSCtdrhW A==; X-CSE-ConnectionGUID: MddWisOYTPOazrwlZXnIMg== X-CSE-MsgGUID: 5rSqC4bySK6cCFfXJLR25g== X-IronPort-AV: E=McAfee;i="6700,10204,11427"; a="48532834" X-IronPort-AV: E=Sophos;i="6.15,275,1739865600"; d="scan'208";a="48532834" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2025 06:43:35 -0700 X-CSE-ConnectionGUID: M7DyZD8GS+uY5LHlXx30ig== X-CSE-MsgGUID: dOLnAt2vT+mBd4TcwLDx1A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,275,1739865600"; d="scan'208";a="136323175" Received: from irvmail002.ir.intel.com ([10.43.11.120]) by orviesa009.jf.intel.com with ESMTP; 09 May 2025 06:43:28 -0700 Received: from mglak.igk.intel.com (mglak.igk.intel.com [10.237.112.146]) by irvmail002.ir.intel.com (Postfix) with ESMTP id 4DD4534311; Fri, 9 May 2025 14:43:26 +0100 (IST) From: Larysa Zaremba To: intel-wired-lan@lists.osuosl.org, Tony Nguyen Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Przemek Kitszel , Jiri Pirko , Tatyana Nikolova , Andrew Lunn , Alexander Lobakin , Michael Ellerman , Maciej Fijalkowski , Lee Trager , Madhavan Srinivasan , Larysa Zaremba , Sridhar Samudrala , Jacob Keller , Michal Swiatkowski , Mateusz Polchlopek , Ahmed Zaki , netdev@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, "Karlsson, Magnus" , Emil Tantilov , Madhu Chittim , Josh Hay , Milena Olech , pavan.kumar.linga@intel.com, "Singhai, Anjali" , Phani R Burra Subject: [PATCH iwl-next v3 03/15] libie: add PCI device initialization helpers to libie Date: Fri, 9 May 2025 15:43:00 +0200 Message-ID: <20250509134319.66631-4-larysa.zaremba@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250509134319.66631-1-larysa.zaremba@intel.com> References: <20250509134319.66631-1-larysa.zaremba@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Phani R Burra Add memory related support functions for drivers to access MMIO space and allocate/free dma buffers. Reviewed-by: Maciej Fijalkowski Signed-off-by: Phani R Burra Co-developed-by: Victor Raj Signed-off-by: Victor Raj Co-developed-by: Sridhar Samudrala Signed-off-by: Sridhar Samudrala Co-developed-by: Pavan Kumar Linga Signed-off-by: Pavan Kumar Linga Co-developed-by: Larysa Zaremba Signed-off-by: Larysa Zaremba --- drivers/net/ethernet/intel/libie/Kconfig | 6 + drivers/net/ethernet/intel/libie/Makefile | 4 + drivers/net/ethernet/intel/libie/pci.c | 184 ++++++++++++++++++++++ include/linux/intel/libie/pci.h | 54 +++++++ 4 files changed, 248 insertions(+) create mode 100644 drivers/net/ethernet/intel/libie/pci.c create mode 100644 include/linux/intel/libie/pci.h diff --git a/drivers/net/ethernet/intel/libie/Kconfig b/drivers/net/etherne= t/intel/libie/Kconfig index e6072758e3d8..e54a9ed24882 100644 --- a/drivers/net/ethernet/intel/libie/Kconfig +++ b/drivers/net/ethernet/intel/libie/Kconfig @@ -14,3 +14,9 @@ config LIBIE_ADMINQ help Helper functions used by Intel Ethernet drivers for administration queue command interface (aka adminq). + +config LIBIE_PCI + tristate + help + Helper functions for management of PCI resources belonging + to networking devices. diff --git a/drivers/net/ethernet/intel/libie/Makefile b/drivers/net/ethern= et/intel/libie/Makefile index e98f00b865d3..5f648d312a2a 100644 --- a/drivers/net/ethernet/intel/libie/Makefile +++ b/drivers/net/ethernet/intel/libie/Makefile @@ -8,3 +8,7 @@ libie-y :=3D rx.o obj-$(CONFIG_LIBIE_ADMINQ) +=3D libie_adminq.o =20 libie_adminq-y :=3D adminq.o + +obj-$(CONFIG_LIBIE_PCI) +=3D libie_pci.o + +libie_pci-y :=3D pci.o diff --git a/drivers/net/ethernet/intel/libie/pci.c b/drivers/net/ethernet/= intel/libie/pci.c new file mode 100644 index 000000000000..727ce7b200a5 --- /dev/null +++ b/drivers/net/ethernet/intel/libie/pci.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2025 Intel Corporation */ + +#include + +/** + * libie_find_mmio_region - find if MMIO region is present in the list + * @mmio_list: list that contains MMIO region info + * @offset: MMIO region start offset + * @bar_idx: BAR index where the offset to search + * + * Return: MMIO region pointer or NULL if the region info is not present. + */ +static struct libie_pci_mmio_region * +libie_find_mmio_region(const struct list_head *mmio_list, + resource_size_t offset, int bar_idx) +{ + struct libie_pci_mmio_region *mr; + + list_for_each_entry(mr, mmio_list, list) + if (mr->bar_idx =3D=3D bar_idx && mr->offset =3D=3D offset) + return mr; + + return NULL; +} + +/** + * __libie_pci_get_mmio_addr - get the MMIO virtual address + * @mmio_info: contains list of MMIO regions + * @offset: register offset of find + * @num_args: number of additional arguments present + * + * This function finds the virtual address of a register offset by iterati= ng + * through the non-linear MMIO regions that are mapped by the driver. + * + * Return: valid MMIO virtual address or NULL. + */ +void __iomem *__libie_pci_get_mmio_addr(struct libie_mmio_info *mmio_info, + resource_size_t offset, + int num_args, ...) +{ + struct libie_pci_mmio_region *mr; + int bar_idx =3D 0; + va_list args; + + if (num_args) { + va_start(args, num_args); + bar_idx =3D va_arg(args, int); + va_end(args); + } + + list_for_each_entry(mr, &mmio_info->mmio_list, list) + if (bar_idx =3D=3D mr->bar_idx && offset >=3D mr->offset && + offset < mr->offset + mr->size) { + offset -=3D mr->offset; + + return mr->addr + offset; + } + + return NULL; +} +EXPORT_SYMBOL_NS_GPL(__libie_pci_get_mmio_addr, "LIBIE_PCI"); + +/** + * __libie_pci_map_mmio_region - map PCI device MMIO region + * @mmio_info: struct to store the mapped MMIO region + * @offset: MMIO region start offset + * @size: MMIO region size + * @num_args: number of additional arguments present + * + * Return: true on success, false on memory map failure. + */ +bool __libie_pci_map_mmio_region(struct libie_mmio_info *mmio_info, + resource_size_t offset, + resource_size_t size, int num_args, ...) +{ + struct pci_dev *pdev =3D mmio_info->pdev; + struct libie_pci_mmio_region *mr; + resource_size_t pa; + void __iomem *va; + int bar_idx =3D 0; + va_list args; + + if (num_args) { + va_start(args, num_args); + bar_idx =3D va_arg(args, int); + va_end(args); + } + + mr =3D libie_find_mmio_region(&mmio_info->mmio_list, offset, bar_idx); + if (mr) { + pci_warn(pdev, "Mapping of BAR%u with offset %llu already exists\n", + bar_idx, (unsigned long long)offset); + return true; + } + + pa =3D pci_resource_start(pdev, bar_idx) + offset; + va =3D ioremap(pa, size); + if (!va) { + pci_err(pdev, "Failed to allocate BAR%u region\n", bar_idx); + return false; + } + + mr =3D kvzalloc(sizeof(*mr), GFP_KERNEL); + if (!mr) { + iounmap(va); + return false; + } + + mr->addr =3D va; + mr->offset =3D offset; + mr->size =3D size; + mr->bar_idx =3D bar_idx; + + list_add_tail(&mr->list, &mmio_info->mmio_list); + + return true; +} +EXPORT_SYMBOL_NS_GPL(__libie_pci_map_mmio_region, "LIBIE_PCI"); + +/** + * libie_pci_unmap_all_mmio_regions - unmap all PCI device MMIO regions + * @mmio_info: contains list of MMIO regions to unmap + */ +void libie_pci_unmap_all_mmio_regions(struct libie_mmio_info *mmio_info) +{ + struct libie_pci_mmio_region *mr, *tmp; + + list_for_each_entry_safe(mr, tmp, &mmio_info->mmio_list, list) { + iounmap(mr->addr); + list_del(&mr->list); + kfree(mr); + } +} +EXPORT_SYMBOL_NS_GPL(libie_pci_unmap_all_mmio_regions, "LIBIE_PCI"); + +/** + * libie_pci_init_dev - enable and reserve PCI regions of the device + * @pdev: PCI device information + * + * Return: %0 on success, -%errno on failure. + */ +int libie_pci_init_dev(struct pci_dev *pdev) +{ + int err; + + err =3D pci_enable_device(pdev); + if (err) + return err; + + err =3D pci_request_mem_regions(pdev, pci_name(pdev)); + if (err) + goto disable_dev; + + err =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (err) + goto rel_regions; + + pci_set_master(pdev); + + return 0; + +rel_regions: + pci_release_regions(pdev); +disable_dev: + pci_disable_device(pdev); + + return err; +} +EXPORT_SYMBOL_NS_GPL(libie_pci_init_dev, "LIBIE_PCI"); + +/** + * libie_pci_deinit_dev - disable and release the PCI regions of the device + * @pdev: PCI device information + */ +void libie_pci_deinit_dev(struct pci_dev *pdev) +{ + pci_disable_device(pdev); + pci_release_regions(pdev); +} +EXPORT_SYMBOL_NS_GPL(libie_pci_deinit_dev, "LIBIE_PCI"); + +MODULE_DESCRIPTION("Common Ethernet PCI library"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/intel/libie/pci.h b/include/linux/intel/libie/pc= i.h new file mode 100644 index 000000000000..4601205adc22 --- /dev/null +++ b/include/linux/intel/libie/pci.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (C) 2025 Intel Corporation */ + +#ifndef __LIBIE_PCI_H +#define __LIBIE_PCI_H + +#include + +/** + * struct libie_pci_mmio_region - structure for MMIO region info + * @list: used to add a MMIO region to the list of MMIO regions in + * libie_mmio_info + * @addr: virtual address of MMIO region start + * @offset: start offset of the MMIO region + * @size: size of the MMIO region + * @bar_idx: BAR index to which the MMIO region belongs to + */ +struct libie_pci_mmio_region { + struct list_head list; + void __iomem *addr; + resource_size_t offset; + resource_size_t size; + u16 bar_idx; +}; + +/** + * struct libie_mmio_info - contains list of MMIO regions + * @pdev: PCI device pointer + * @mmio_list: list of MMIO regions + */ +struct libie_mmio_info { + struct pci_dev *pdev; + struct list_head mmio_list; +}; + +#define libie_pci_map_mmio_region(mmio_info, offset, size, ...) \ + __libie_pci_map_mmio_region(mmio_info, offset, size, \ + COUNT_ARGS(__VA_ARGS__), ##__VA_ARGS__) + +#define libie_pci_get_mmio_addr(mmio_info, offset, ...) \ + __libie_pci_get_mmio_addr(mmio_info, offset, \ + COUNT_ARGS(__VA_ARGS__), ##__VA_ARGS__) + +bool __libie_pci_map_mmio_region(struct libie_mmio_info *mmio_info, + resource_size_t offset, resource_size_t size, + int num_args, ...); +void __iomem *__libie_pci_get_mmio_addr(struct libie_mmio_info *mmio_info, + resource_size_t region_offset, + int num_args, ...); +void libie_pci_unmap_all_mmio_regions(struct libie_mmio_info *mmio_info); +int libie_pci_init_dev(struct pci_dev *pdev); +void libie_pci_deinit_dev(struct pci_dev *pdev); + +#endif /* __LIBIE_PCI_H */ --=20 2.47.0