From nobody Wed Dec 17 10:46:32 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 206EB29114C; Fri, 9 May 2025 12:53:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746795181; cv=none; b=mMjBzT4LslKnLQO72d5liz1zL74XzLjimk9xOp9heUiMrDkB7XWibf9UV0KNR6CSKazzR3/LzvOIZ4MEfH5C/yd+uJ5q9dBBFf/NrXvkLpX4BLXqw0wXPz+QXfCZWNiZGVX3AQCJiuYXdlabfZWLQYJ85GY7ad4WZQ9eimfbPmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746795181; c=relaxed/simple; bh=csIdm8rOheD5HAvRthwznu0vhK7n7Z3LIFwPSQSRI1s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aKHw5bffHk07Xn8gQVP9nXJPmPDxpxTa4+eWwoZr7kj7wNb33dhRJV9v9lWGTpN1aizo+zeCUUxuCniZ8zqfruevuJIQ13S9lBck4T5NJpKZ5cn6zyrscjVYX5MYvi+AtcQC5CSHB5hDKOO+2OBE954viBjd7eajZwiF2ZCV+38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WQRZ+6L+; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WQRZ+6L+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746795181; x=1778331181; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=csIdm8rOheD5HAvRthwznu0vhK7n7Z3LIFwPSQSRI1s=; b=WQRZ+6L+WxE/D3fmpHeasN3w/rbPY1HGrUH7vVCcGZjArxhQ+KQUHM3C iWLZ6BR9qVpzI3hC0SmPQldsmj0ybudhMdtj8VyTUZkwFdqhmwOhp0nAm 1x+NaPypItiukZyrdTMijGXPQR9/0sx/6g4oDac9NEWK8lzxy/k4fxmYm oWYJatmhWcxf2aUMgMzyF6q6kMXaQwMEWYZQi8A1kbs7qwSDldTXjSN0g hQRkbMv19ZAEk3ARoyGBU5fn5/fWmDc/Y15sCbtuKJ02w/KYCptja4uyS N9qy3YWYtntrNlmz+5Y9eNFY0Dn3Vg9C7J9/Sc4L0LYp47Ky+MK9E8GAL w==; X-CSE-ConnectionGUID: 70Msj5VuTOi9c7GPy5TVfg== X-CSE-MsgGUID: d4IuYnWlRP6E8jJZtFdUfA== X-IronPort-AV: E=McAfee;i="6700,10204,11427"; a="66027329" X-IronPort-AV: E=Sophos;i="6.15,275,1739865600"; d="scan'208";a="66027329" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2025 05:53:00 -0700 X-CSE-ConnectionGUID: Ow6u/R7kRumMYC+TPWEIeg== X-CSE-MsgGUID: m/DTKirER0O4Zu5qyQQJEA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,275,1739865600"; d="scan'208";a="141828297" Received: from amlin-018-114.igk.intel.com ([10.102.18.114]) by fmviesa004.fm.intel.com with ESMTP; 09 May 2025 05:52:56 -0700 From: Arkadiusz Kubalewski To: donald.hunter@gmail.com, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, jiri@resnulli.us, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, andrew+netdev@lunn.ch, aleksandr.loktionov@intel.com Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org, linux-rdma@vger.kernel.org, Arkadiusz Kubalewski , Milena Olech Subject: [PATCH net-next v2 3/3] ice: add Reference SYNC dpll pins Date: Fri, 9 May 2025 14:46:51 +0200 Message-Id: <20250509124651.1227098-4-arkadiusz.kubalewski@intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250509124651.1227098-1-arkadiusz.kubalewski@intel.com> References: <20250509124651.1227098-1-arkadiusz.kubalewski@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement Reference SYNC input pin get/set callbacks, allow user space control over dpll pin pairs capable of Reference SYNC support. Reviewed-by: Milena Olech Signed-off-by: Arkadiusz Kubalewski --- v2: - improve commit message. --- .../net/ethernet/intel/ice/ice_adminq_cmd.h | 2 + drivers/net/ethernet/intel/ice/ice_dpll.c | 186 ++++++++++++++++++ 2 files changed, 188 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/= ethernet/intel/ice/ice_adminq_cmd.h index bdee499f991a..7fd0f0091d36 100644 --- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h +++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h @@ -2288,6 +2288,8 @@ struct ice_aqc_get_cgu_abilities { u8 rsvd[3]; }; =20 +#define ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN BIT(7) + /* Set CGU input config (direct 0x0C62) */ struct ice_aqc_set_cgu_input_config { u8 input_idx; diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index bce3ad6ca2a6..98f0c86f41fc 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -12,6 +12,19 @@ #define ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT 25 #define ICE_DPLL_PIN_GEN_RCLK_FREQ 1953125 =20 +#define ICE_SR_PFA_DPLL_DEFAULTS 0x152 +#define ICE_DPLL_PFA_REF_SYNC_TYPE 0x2420 +#define ICE_DPLL_PFA_REF_SYNC_TYPE2 0x2424 +#define ICE_DPLL_PFA_END 0xFFFF +#define ICE_DPLL_PFA_HEADER_LEN 4 +#define ICE_DPLL_PFA_ENTRY_LEN 3 +#define ICE_DPLL_PFA_MAILBOX_REF_SYNC_PIN_S 4 +#define ICE_DPLL_PFA_MASK_OFFSET 1 +#define ICE_DPLL_PFA_VALUE_OFFSET 2 + +#define ICE_DPLL_E810C_SFP_NC_PINS 2 +#define ICE_DPLL_E810C_SFP_NC_START 4 + /** * enum ice_dpll_pin_type - enumerate ice pin types: * @ICE_DPLL_PIN_INVALID: invalid pin type @@ -1314,6 +1327,89 @@ ice_dpll_input_esync_get(const struct dpll_pin *pin,= void *pin_priv, return 0; } =20 +/** + * ice_dpll_input_ref_sync_set - callback for setting reference sync featu= re + * @pin: pointer to a pin + * @pin_priv: private data pointer passed on pin registration + * @ref_pin: pin pointer for reference sync pair + * @ref_pin_priv: private data pointer of ref_pin + * @state: requested state for reference sync for pin pair + * @extack: error reporting + * + * Dpll subsystem callback. Handler for setting reference sync frequency + * feature for input pin. + * + * Context: Acquires and releases pf->dplls.lock + * Return: + * * 0 - success + * * negative - error + */ +static int +ice_dpll_input_ref_sync_set(const struct dpll_pin *pin, void *pin_priv, + const struct dpll_pin *ref_pin, void *ref_pin_priv, + const enum dpll_pin_state state, + struct netlink_ext_ack *extack) +{ + struct ice_dpll_pin *p =3D pin_priv; + struct ice_pf *pf =3D p->pf; + u8 flags_en =3D 0; + int ret; + + if (ice_dpll_is_reset(pf, extack)) + return -EBUSY; + mutex_lock(&pf->dplls.lock); + + if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) + flags_en =3D ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN; + if (state =3D=3D DPLL_PIN_STATE_CONNECTED) + flags_en |=3D ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN; + ret =3D ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, flags_en, 0, 0); + if (!ret) + ret =3D ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_INPUT, + extack); + mutex_unlock(&pf->dplls.lock); + + return ret; +} + +/** + * ice_dpll_input_ref_sync_get - callback for getting reference sync config + * @pin: pointer to a pin + * @pin_priv: private data pointer passed on pin registration + * @ref_pin: pin pointer for reference sync pair + * @ref_pin_priv: private data pointer of ref_pin + * @state: on success holds reference sync state for pin pair + * @extack: error reporting + * + * Dpll subsystem callback. Handler for setting reference sync frequency + * feature for input pin. + * + * Context: Acquires and releases pf->dplls.lock + * Return: + * * 0 - success + * * negative - error + */ +static int +ice_dpll_input_ref_sync_get(const struct dpll_pin *pin, void *pin_priv, + const struct dpll_pin *ref_pin, void *ref_pin_priv, + enum dpll_pin_state *state, + struct netlink_ext_ack *extack) +{ + struct ice_dpll_pin *p =3D pin_priv; + struct ice_pf *pf =3D p->pf; + + if (ice_dpll_is_reset(pf, extack)) + return -EBUSY; + mutex_lock(&pf->dplls.lock); + if (p->flags[0] & ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN) + *state =3D DPLL_PIN_STATE_CONNECTED; + else + *state =3D DPLL_PIN_STATE_DISCONNECTED; + mutex_unlock(&pf->dplls.lock); + + return 0; +} + /** * ice_dpll_rclk_state_on_pin_set - set a state on rclk pin * @pin: pointer to a pin @@ -1440,6 +1536,8 @@ static const struct dpll_pin_ops ice_dpll_input_ops = =3D { .phase_offset_get =3D ice_dpll_phase_offset_get, .esync_set =3D ice_dpll_input_esync_set, .esync_get =3D ice_dpll_input_esync_get, + .ref_sync_set =3D ice_dpll_input_ref_sync_set, + .ref_sync_get =3D ice_dpll_input_ref_sync_get, }; =20 static const struct dpll_pin_ops ice_dpll_output_ops =3D { @@ -1619,6 +1717,91 @@ static void ice_dpll_periodic_work(struct kthread_wo= rk *work) msecs_to_jiffies(500)); } =20 +/** + * ice_dpll_init_ref_sync_inputs - initialize reference sync pin pairs + * @pf: pf private structure + * + * Read DPLL TLV capabilities and initialize reference sync pin pairs in + * dpll subsystem. + * + * Return: + * * 0 - success or nothing to do (no ref-sync tlv are present) + * * negative - AQ failure + */ +static int ice_dpll_init_ref_sync_inputs(struct ice_pf *pf) +{ + struct ice_dpll_pin *inputs =3D pf->dplls.inputs; + struct ice_hw *hw =3D &pf->hw; + u16 addr, len, end, hdr; + int ret; + + ret =3D ice_get_pfa_module_tlv(hw, &hdr, &len, ICE_SR_PFA_DPLL_DEFAULTS); + if (ret) { + dev_err(ice_pf_to_dev(pf), + "Failed to read PFA dpll defaults TLV ret=3D%d\n", ret); + return ret; + } + end =3D hdr + len; + + for (addr =3D hdr + ICE_DPLL_PFA_HEADER_LEN; addr < end; + addr +=3D ICE_DPLL_PFA_ENTRY_LEN) { + unsigned long bit, ul_mask, offset; + u16 pin, mask, buf; + bool valid =3D false; + + ret =3D ice_read_sr_word(hw, addr, &buf); + if (ret) + return ret; + + switch (buf) { + case ICE_DPLL_PFA_REF_SYNC_TYPE: + case ICE_DPLL_PFA_REF_SYNC_TYPE2: + { + u16 mask_addr =3D addr + ICE_DPLL_PFA_MASK_OFFSET; + u16 val_addr =3D addr + ICE_DPLL_PFA_VALUE_OFFSET; + + ret =3D ice_read_sr_word(hw, mask_addr, &mask); + if (ret) + return ret; + ret =3D ice_read_sr_word(hw, val_addr, &pin); + if (ret) + return ret; + if (buf =3D=3D ICE_DPLL_PFA_REF_SYNC_TYPE) + pin >>=3D ICE_DPLL_PFA_MAILBOX_REF_SYNC_PIN_S; + valid =3D true; + break; + } + case ICE_DPLL_PFA_END: + addr =3D end; + break; + default: + continue; + } + if (!valid) + continue; + + ul_mask =3D mask; + offset =3D 0; + for_each_set_bit(bit, &ul_mask, BITS_PER_TYPE(u16)) { + int i, j; + + if (hw->device_id =3D=3D ICE_DEV_ID_E810C_SFP && + pin > ICE_DPLL_E810C_SFP_NC_START) + offset =3D -ICE_DPLL_E810C_SFP_NC_PINS; + i =3D pin + offset; + j =3D bit + offset; + if (i < 0 || j < 0) + return -ERANGE; + ret =3D dpll_pin_ref_sync_pair_add(inputs[i].pin, + inputs[j].pin); + if (ret) + return ret; + } + } + + return 0; +} + /** * ice_dpll_release_pins - release pins resources from dpll subsystem * @pins: pointer to pins array @@ -1936,6 +2119,9 @@ static int ice_dpll_init_pins(struct ice_pf *pf, bool= cgu) if (ret) return ret; if (cgu) { + ret =3D ice_dpll_init_ref_sync_inputs(pf); + if (ret) + goto deinit_inputs; ret =3D ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs, pf->dplls.num_inputs, pf->dplls.num_outputs, --=20 2.38.1