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Fri, 9 May 2025 06:50:34 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v5 08/10] dt-bindings: iio: adc: add ad4080 Date: Fri, 9 May 2025 13:50:17 +0300 Message-ID: <20250509105019.8887-9-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509105019.8887-1-antoniu.miclaus@analog.com> References: <20250509105019.8887-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: pzDibyhkoaPuDTgWboEFxaQ4i_4QCNyN X-Proofpoint-ORIG-GUID: pzDibyhkoaPuDTgWboEFxaQ4i_4QCNyN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA5MDEwNCBTYWx0ZWRfX6kOXwB8lbWcF SQTF7xqOFTRuaEdXVtq4gXFnczr5zfxqEnWCQdQqIergyrQ4AA4pWGukj1nt8Vk32k8dPchYxXV 3SRvgVCjvxTdbA20VQS75pb4nOKKeXWD+OJXElWMaEC1EXTSBPhUGpvGGNl2/cgK73IT9DyhS4U fJ4Xh4ZeE8R23FlkmayOsUJLJytgLg7ZuWGZKA3TpSGlVQ9SEXib+HUtXFqBRIwzcLfOY9wu3kb 4ucw3ZRFDHKmg8R2fuXYdB0SbHfOipy3gf6gMFFaYgyBOVqo1nhQoWd8OniO3SUJ8YyUIjja76E OFOL+I0jPxUtgj9IMYf6hq16dlvzujP7eU2/R7xqDFEDKdqU/CobbZ3KmPR950r5To4R+j8X6Ia ortWoQOfR/VDwx8sSg1GG7CTLY3SzhZPzUYXT/S1MuCzEt+88yHDCcNgm8KRcbMF3+hrFnne X-Authority-Analysis: v=2.4 cv=eeE9f6EH c=1 sm=1 tr=0 ts=681dddff cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=dt9VzEwgFbYA:10 a=gEfo2CItAAAA:8 a=gAnH3GRIAAAA:8 a=VwQbUJbxAAAA:8 a=P3hoaKw3YfnMoAj370EA:9 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-09_04,2025-05-08_04,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 bulkscore=0 priorityscore=1501 malwarescore=0 phishscore=0 spamscore=0 mlxscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505090104 Content-Type: text/plain; charset="utf-8" Add devicetree bindings for ad4080 family. Reviewed-by: Rob Herring (Arm) Signed-off-by: Antoniu Miclaus --- no changes in v5. .../bindings/iio/adc/adi,ad4080.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4080.ya= ml diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4080.yaml new file mode 100644 index 000000000000..ed849ba1b77b --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2025 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4080.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4080 20-Bit, 40 MSPS, Differential SAR ADC + +maintainers: + - Antoniu Miclaus + +description: | + The AD4080 is a high speed, low noise, low distortion, 20-bit, Easy Driv= e, + successive approximation register (SAR) analog-to-digital converter (ADC= ). + Maintaining high performance (signal-to-noise and distortion (SINAD) rat= io + > 90 dBFS) at signal frequencies in excess of 1 MHz enables the AD4080 to + service a wide variety of precision, wide bandwidth data acquisition + applications. + + https://www.analog.com/media/en/technical-documentation/data-sheets/ad40= 80.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4080 + + reg: + maxItems: 1 + + spi-max-frequency: + description: Configuration of the SPI bus. + maximum: 50000000 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: cnv + + vdd33-supply: true + + vdd11-supply: true + + vddldo-supply: true + + iovdd-supply: true + + vrefin-supply: true + + io-backends: + maxItems: 1 + + adi,lvds-cnv-enable: + description: Enable the LVDS signal type on the CNV pin. Default is CM= OS. + type: boolean + + adi,num-lanes: + description: + Number of lanes on which the data is sent on the output (DA, DB pins= ). + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + default: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - vdd33-supply + - vrefin-supply + +additionalProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4080"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + vdd33-supply =3D <&vdd33>; + vddldo-supply =3D <&vddldo>; + vrefin-supply =3D <&vrefin>; + clocks =3D <&cnv>; + clock-names =3D "cnv"; + io-backends =3D <&iio_backend>; + }; + }; +... --=20 2.49.0