From nobody Tue Dec 16 14:57:54 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 964CE27A127; Fri, 9 May 2025 09:19:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746782395; cv=none; b=IQpk2fCqC2EmYqdtkvjI7ALxrQwV2zfjhoFJaDokGC5TwVPiydWd27RpaZQa9KM83AANKqbqUrlVwEAOhhL4Ur14oLgcrTcDwVvnS0sDYaQJBfrRLbqhp5SdEkwcBOTv8coMaYcxLPal2im/SH9g3TPD88EERpFQfse311Xj2A8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746782395; c=relaxed/simple; bh=ZmvBu6pK4R5J2b2dO+dgBez3gf/jvMjoBba3I3sEE/U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QbCiWRgmYWzQs6W8GgxWHCuDsNuknTDXIu9apE9F1pGhJo1/dYf4frkHeYg2Igq80uPtYo0yYtc6IFgt9cqGXcx1eVUeoY+Vda0SaFxaL0OFc5/qHRInNuoS5prnJRpIsoksAJQAB2pS9q2Sblw8cZCw0oHsF6gELddKbBpnHk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=RSgkL3b5; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="RSgkL3b5" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5499JkdE1360996 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 9 May 2025 04:19:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746782386; bh=u/nC/XdwxLZLIjaNaHB9iaXgqC7KbPwX+cIM97tewmg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RSgkL3b5YDjkmKfvKdLidrvw5DWNr/X8k43w4m7v5mUG7eC39G+1Fb0zTK0rtV2Wx nxqBRZDs7PYdV12DT60+IlCwi3IQq44Yqq2pGiDSy3x6lE7+DxmS3+kZOqkfnBdmUC zPq3CKiswrRZsc1xf/wjqz/LkIzoiApo6ks+uSFA= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5499JkPa123937 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 9 May 2025 04:19:46 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 9 May 2025 04:19:45 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 9 May 2025 04:19:45 -0500 Received: from abhilash-HP.dhcp.ti.com (abhilash-hp.dhcp.ti.com [172.24.227.115]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5499JL7v070287; Fri, 9 May 2025 04:19:42 -0500 From: Yemike Abhilash Chandra To: , , , , , CC: , , , , , , , Subject: [PATCH v3 4/4] arm64: dts: ti: k3-j722s-evm: Add overlay for TEVI OV5640 Date: Fri, 9 May 2025 14:49:11 +0530 Message-ID: <20250509091911.2442934-5-y-abhilashchandra@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250509091911.2442934-1-y-abhilashchandra@ti.com> References: <20250509091911.2442934-1-y-abhilashchandra@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Vaishnav Achath TechNexion TEVI OV5640 camera is a 5MP camera that can be used with J722S EVM through the 22-pin CSI-RX connector. Add a reference overlay for quad TEVI OV5640 modules on J722S EVM. Signed-off-by: Vaishnav Achath Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar --- Changelog: Changes in v3: - Add make file entries in alpha sorted order - Correct copyright year in tevi-OV5640 overlay arch/arm64/boot/dts/ti/Makefile | 4 + .../k3-j722s-evm-csi2-quad-tevi-ov5640.dtso | 323 ++++++++++++++++++ 2 files changed, 327 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov56= 40.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 281a282fcbfb..c6171de9fe88 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -133,6 +133,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-beagley-ai.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo =20 # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb @@ -228,6 +229,8 @@ k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-= board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs :=3D k3-j722s-evm.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo +k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs :=3D k3-j722s-evm.dtb \ + k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo k3-j742s2-evm-usb0-type-a-dtbs :=3D k3-j742s2-evm.dtb \ k3-j784s4-j742s2-evm-usb0-type-a.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs :=3D k3-j784s4-evm.dtb \ @@ -267,6 +270,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \ + k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \ k3-j742s2-evm-usb0-type-a.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso= b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso new file mode 100644 index 000000000000..575113d7b481 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DT Overlay for 4 x TEVI OV5640 MIPI Camera module on J722S-EVM board. + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + cam0_reset_pins_default: cam0-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x03c, PIN_OUTPUT, 7) /* (R22) GPIO0_15 */ + >; + }; + + cam1_reset_pins_default: cam1-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x044, PIN_OUTPUT, 7) /* (R26) GPIO0_17 */ + >; + }; + + cam2_reset_pins_default: cam2-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x04c, PIN_OUTPUT, 7) /* (T25) GPIO0_19 */ + >; + }; + + cam3_reset_pins_default: cam3-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x054, PIN_OUTPUT, 7) /* (T21) GPIO0_21 */ + >; + }; +}; + +&{/} { + clk_ov5640_fixed: clock-24000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + reg_2p8v: regulator-2p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "2P8V"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <&vsys_3v3_exp>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "1P8V"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vsys_3v3_exp>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "3P3V"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vsys_3v3_exp>; + regulator-always-on; + }; +}; + +&csi01_mux { + idle-state =3D <1>; +}; + +&csi23_mux { + idle-state =3D <1>; +}; + +&pca9543_0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + ov5640_0: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + AVDD-supply =3D <®_2p8v>; + DOVDD-supply =3D <®_1p8v>; + DVDD-supply =3D <®_3p3v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam0_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 15 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint =3D <&csi2rx0_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + ov5640_1: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + AVDD-supply =3D <®_2p8v>; + DOVDD-supply =3D <®_1p8v>; + DVDD-supply =3D <®_3p3v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam1_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 17 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint =3D <&csi2rx1_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; +}; + +&pca9543_1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + ov5640_2: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + AVDD-supply =3D <®_2p8v>; + DOVDD-supply =3D <®_1p8v>; + DVDD-supply =3D <®_3p3v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam2_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 19 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam2: endpoint { + remote-endpoint =3D <&csi2rx2_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + ov5640_3: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + AVDD-supply =3D <®_2p8v>; + DOVDD-supply =3D <®_1p8v>; + DVDD-supply =3D <®_3p3v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam3_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam3: endpoint { + remote-endpoint =3D <&csi2rx3_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam0>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam1>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam2>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx3 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi3_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx3_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam3>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status =3D "okay"; +}; + +&dphy0 { + status =3D "okay"; +}; + +&ti_csi2rx1 { + status =3D "okay"; +}; + +&dphy1 { + status =3D "okay"; +}; + +&ti_csi2rx2 { + status =3D "okay"; +}; + +&dphy2 { + status =3D "okay"; +}; + +&ti_csi2rx3 { + status =3D "okay"; +}; + +&dphy3 { + status =3D "okay"; +}; --=20 2.34.1