From nobody Tue Feb 10 22:00:01 2026 Received: from mail-sh.amlogic.com (unknown [58.32.228.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DBDF27702E; Fri, 9 May 2025 07:50:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=58.32.228.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746777007; cv=none; b=oVJ/7Yu+SxorMP2KaScJV+oHBAHgv0Cm4p75/efNPpeOojJvRF8p68sEciNmmsOBRQs+hZFrFCCMe4NkN8TJhXq/teDmWpdxUBALMGCrI5yX9rIv4HUpAleBtbOdoorKuXPXOXQkbWgdNwAH4dr0OGyZWyR/FGryNmuCTJki0Sk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746777007; c=relaxed/simple; bh=DCkwb3MGH1rD+L63eUkoHikAjee+p+jCURZczTdB6fk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=D6Y/xgzF0X4l6V5jokrfus59lIsC8qRL9wHA7m5tWvCarxrQdka+MbwrzhQDXgsEtNufyYxo0W3eRjts/FUgaf0vD6aS7TiRC1FYkRKQSbJ9tlRSJEkirwbsnkA2TrkEdrB5Hb39wasdW+B6GdqAiOHTZw8vJY+KsdX4zkrUn9Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=58.32.228.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.39; Fri, 9 May 2025 15:49:57 +0800 From: Jian Hu To: Jerome Brunet , Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , "Stephen Boyd" , Michael Turquette , "Dmitry Rokosov" , robh+dt , Rob Herring CC: Jian Hu , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: [PATCH v3 6/6] clk: meson: t7: add t7 clock peripherals controller driver Date: Fri, 9 May 2025 07:48:24 +0000 Message-ID: <20250509074825.1933254-7-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250509074825.1933254-1-jian.hu@amlogic.com> References: <20250509074825.1933254-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Peripheral clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu --- drivers/clk/meson/Kconfig | 13 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/t7-peripherals.c | 2359 ++++++++++++++++++++++++++++ 3 files changed, 2373 insertions(+) create mode 100644 drivers/clk/meson/t7-peripherals.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 8bb4f26a86ed..e32faa24c760 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -216,4 +216,17 @@ config COMMON_CLK_T7_PLL device, AKA T7. PLLs are required by most peripheral to operate Say Y if you are a T7 based device. =20 +config COMMON_CLK_T7_PERIPHERALS + tristate "Amlogic T7 SoC peripherals clock controller support" + depends on ARM64 + default y + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + select COMMON_CLK_MESON_DUALDIV + imply COMMON_CLK_SCMI + imply COMMON_CLK_T7_PLL + help + Support for the Peripherals clock controller on Amlogic A311D2 based + device, AKA T7. Peripherals are required by most peripheral to operate + Say Y if you are a T7 based device. endmenu diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 646257694c34..6fef3188af30 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) +=3D meson8b.o meson8-dd= r.o obj-$(CONFIG_COMMON_CLK_S4_PLL) +=3D s4-pll.o obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) +=3D s4-peripherals.o obj-$(CONFIG_COMMON_CLK_T7_PLL) +=3D t7-pll.o +obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) +=3D t7-peripherals.o diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peri= pherals.c new file mode 100644 index 000000000000..9a0681183eee --- /dev/null +++ b/drivers/clk/meson/t7-peripherals.c @@ -0,0 +1,2359 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2024 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + */ + +#include +#include +#include "clk-dualdiv.h" +#include "clk-regmap.h" +#include "meson-clkc-utils.h" +#include + +#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x8 +#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0xc +#define CLKCTRL_RTC_CTRL 0x10 +#define CLKCTRL_SYS_CLK_CTRL0 0x40 +#define CLKCTRL_SYS_CLK_EN0_REG0 0x44 +#define CLKCTRL_SYS_CLK_EN0_REG1 0x48 +#define CLKCTRL_SYS_CLK_EN0_REG2 0x4c +#define CLKCTRL_SYS_CLK_EN0_REG3 0x50 +#define CLKCTRL_CECA_CTRL0 0x88 +#define CLKCTRL_CECA_CTRL1 0x8c +#define CLKCTRL_CECB_CTRL0 0x90 +#define CLKCTRL_CECB_CTRL1 0x94 +#define CLKCTRL_SC_CLK_CTRL 0x98 +#define CLKCTRL_DSPA_CLK_CTRL0 0x9c +#define CLKCTRL_DSPB_CLK_CTRL0 0xa0 +#define CLKCTRL_CLK12_24_CTRL 0xa8 +#define CLKCTRL_ANAKIN_CLK_CTRL 0xac +#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL 0x10c +#define CLKCTRL_MIPI_ISP_CLK_CTRL 0x110 +#define CLKCTRL_TS_CLK_CTRL 0x158 +#define CLKCTRL_MALI_CLK_CTRL 0x15c +#define CLKCTRL_ETH_CLK_CTRL 0x164 +#define CLKCTRL_NAND_CLK_CTRL 0x168 +#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c +#define CLKCTRL_SPICC_CLK_CTRL 0x174 +#define CLKCTRL_SAR_CLK_CTRL0 0x17c +#define CLKCTRL_PWM_CLK_AB_CTRL 0x180 +#define CLKCTRL_PWM_CLK_CD_CTRL 0x184 +#define CLKCTRL_PWM_CLK_EF_CTRL 0x188 +#define CLKCTRL_PWM_CLK_AO_AB_CTRL 0x1a0 +#define CLKCTRL_PWM_CLK_AO_CD_CTRL 0x1a4 +#define CLKCTRL_PWM_CLK_AO_EF_CTRL 0x1a8 +#define CLKCTRL_PWM_CLK_AO_GH_CTRL 0x1ac +#define CLKCTRL_SPICC_CLK_CTRL1 0x1c0 +#define CLKCTRL_SPICC_CLK_CTRL2 0x1c4 + +static struct clk_regmap t7_rtc_32k_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_rtc_32k_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static const struct meson_clk_dualdiv_param t7_clk_32k_div_table[] =3D { + { + .n1 =3D 733, .m1 =3D 8, + .n2 =3D 732, .m2 =3D 11, + .dual =3D 1, + }, + {} +}; + +static struct clk_regmap t7_rtc_32k_div =3D { + .data =3D &(struct meson_clk_dualdiv_data){ + .n1 =3D { + .reg_off =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D CLKCTRL_RTC_BY_OSCIN_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D CLKCTRL_RTC_BY_OSCIN_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D t7_clk_32k_div_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_rtc_32k_div", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_rtc_32k_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_rtc_32k_force_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_RTC_BY_OSCIN_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_rtc_32k_force_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_rtc_32k_div.hw, + &t7_rtc_32k_in.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_rtc_32k_out =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_rtc_32k_out", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_rtc_32k_force_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_rtc_32k_mux0_0 =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_RTC_CTRL, + .mask =3D 0x1, + .shift =3D 0, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_rtc_32k_mux0_0", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .hw =3D &t7_rtc_32k_out.hw }, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_rtc_32k_mux0_1 =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_RTC_CTRL, + .mask =3D 0x1, + .shift =3D 0, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_rtc_32k_mux0_1", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "pad", }, + { .fw_name =3D "xtal", }, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_rtc =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_RTC_CTRL, + .mask =3D 0x1, + .shift =3D 1, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_rtc", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_rtc_32k_mux0_0.hw, + &t7_rtc_32k_mux0_1.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_ceca_32k_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_CECA_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_ceca_32k_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_ceca_32k_div =3D { + .data =3D &(struct meson_clk_dualdiv_data){ + .n1 =3D { + .reg_off =3D CLKCTRL_CECA_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D CLKCTRL_CECA_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D CLKCTRL_CECA_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D CLKCTRL_CECA_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D CLKCTRL_CECA_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D t7_clk_32k_div_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_ceca_32k_div", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_ceca_32k_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_ceca_32k_sel_pre =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_CECA_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_ceca_32k_sel_pre", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_ceca_32k_div.hw, + &t7_ceca_32k_in.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_ceca_32k_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_CECA_CTRL1, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_ceca_32k_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_ceca_32k_sel_pre.hw, + &t7_rtc.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_ceca_32k_out =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_CECA_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_ceca_32k_out", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_ceca_32k_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_cecb_32k_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_CECB_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_cecb_32k_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_cecb_32k_div =3D { + .data =3D &(struct meson_clk_dualdiv_data){ + .n1 =3D { + .reg_off =3D CLKCTRL_CECB_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D CLKCTRL_CECB_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D CLKCTRL_CECB_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D CLKCTRL_CECB_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D CLKCTRL_CECB_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D t7_clk_32k_div_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_cecb_32k_div", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_cecb_32k_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_cecb_32k_sel_pre =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_CECB_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_cecb_32k_sel_pre", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_cecb_32k_div.hw, + &t7_cecb_32k_in.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_cecb_32k_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_CECB_CTRL1, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_cecb_32k_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_cecb_32k_sel_pre.hw, + &t7_rtc.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_cecb_32k_out =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_CECB_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_cecb_32k_out", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_cecb_32k_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* Smartcard Clock */ +static const struct clk_parent_data t7_sc_parents[] =3D { + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "xtal", }, +}; + +static struct clk_regmap t7_sc_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_SC_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_sc_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_sc_parents, + .num_parents =3D ARRAY_SIZE(t7_sc_parents), + }, +}; + +static struct clk_regmap t7_sc_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_SC_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_sc_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_sc_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sc =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_SC_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_sc", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_sc_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * The DSPA/B IP is clocked by two identical clocks (dspa/b_a and dspa/b_b) + * muxed by a glitch-free switch. + */ +static const struct clk_parent_data t7_dsp_ab_parent_data[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "hifi", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv7", }, + { .hw =3D &t7_rtc.hw }, +}; + +static struct clk_regmap t7_dspa_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_dspa_a_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_dsp_ab_parent_data, + .num_parents =3D ARRAY_SIZE(t7_dsp_ab_parent_data), + }, +}; + +static struct clk_regmap t7_dspa_a_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .shift =3D 0, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_dspa_a_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspa_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspa_a =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .bit_idx =3D 13, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_dspa_a", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspa_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspa_b_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 26, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_dspa_b_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_dsp_ab_parent_data, + .num_parents =3D ARRAY_SIZE(t7_dsp_ab_parent_data), + }, +}; + +static struct clk_regmap t7_dspa_b_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .shift =3D 16, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_dspa_b_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspa_b_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspa_b =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .bit_idx =3D 29, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_dspa_b", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspa_b_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspa =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_dspa", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspa_a.hw, + &t7_dspa_b.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspb_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_DSPB_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_dspb_a_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_dsp_ab_parent_data, + .num_parents =3D ARRAY_SIZE(t7_dsp_ab_parent_data), + }, +}; + +static struct clk_regmap t7_dspb_a_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_DSPB_CLK_CTRL0, + .shift =3D 0, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_dspb_a_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspb_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspb_a =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_DSPB_CLK_CTRL0, + .bit_idx =3D 13, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_dspb_a", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspb_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspb_b_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_DSPB_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 26, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_dspb_b_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_dsp_ab_parent_data, + .num_parents =3D ARRAY_SIZE(t7_dsp_ab_parent_data), + }, +}; + +static struct clk_regmap t7_dspb_b_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_DSPB_CLK_CTRL0, + .shift =3D 16, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_dspb_b_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspb_b_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspb_b =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_DSPB_CLK_CTRL0, + .bit_idx =3D 29, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_dspb_b", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspb_b_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_dspb =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_DSPB_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_dspb", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_dspb_a.hw, + &t7_dspb_b.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_clk_24m =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_CLK12_24_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_24m", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor t7_clk_24m_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_24m_div2", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_clk_24m.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_clk_12m =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_CLK12_24_CTRL, + .bit_idx =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_12m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_clk_24m_div2.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_fdiv2_divn_pre =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_CLK12_24_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_fdiv2_divn_pre", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_fdiv2_divn =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_CLK12_24_CTRL, + .bit_idx =3D 12, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_fdiv2_divn", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_fdiv2_divn_pre.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * The NNA IP is clocked by two identical clocks (anakin_0 and anakin_1) + * muxed by a glitch-free switch. + */ +static const struct clk_parent_data t7_anakin_parent_data[] =3D { + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "vid_pll0", }, + { .fw_name =3D "mpll1", }, + { .fw_name =3D "mpll2", }, + { .fw_name =3D "fdiv2p5", }, +}; + +static struct clk_regmap t7_anakin_0_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_ANAKIN_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_anakin_0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_anakin_parent_data, + .num_parents =3D ARRAY_SIZE(t7_anakin_parent_data), + }, +}; + +static struct clk_regmap t7_anakin_0_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_ANAKIN_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_anakin_0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_anakin_0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_anakin_0 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_ANAKIN_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_anakin_0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &t7_anakin_0_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_anakin_1_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_ANAKIN_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_anakin_1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_anakin_parent_data, + .num_parents =3D ARRAY_SIZE(t7_anakin_parent_data), + }, +}; + +static struct clk_regmap t7_anakin_1_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_ANAKIN_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_anakin_1_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_anakin_1_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_anakin_1 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_ANAKIN_CLK_CTRL, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_anakin_1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_anakin_1_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_anakin =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_ANAKIN_CLK_CTRL, + .mask =3D 1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_anakin_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_anakin_0.hw, + &t7_anakin_1.hw + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT + }, +}; + +static struct clk_regmap t7_anakin_clk =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_ANAKIN_CLK_CTRL, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_anakin_clk", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_anakin.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT + }, +}; + +static const struct clk_parent_data t7_mipi_csi_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "gp1", }, + { .fw_name =3D "mpll1", }, + { .fw_name =3D "mpll2", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, +}; + +static struct clk_regmap t7_mipi_csi_phy0_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mipi_csi_phy0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_mipi_csi_parents, + .num_parents =3D ARRAY_SIZE(t7_mipi_csi_parents), + }, +}; + +static struct clk_regmap t7_mipi_csi_phy0_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mipi_csi_phy0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mipi_csi_phy0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mipi_csi_phy0 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_mipi_csi_phy0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mipi_csi_phy0_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mipi_csi_phy1_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mipi_csi_phy1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_mipi_csi_parents, + .num_parents =3D ARRAY_SIZE(t7_mipi_csi_parents), + }, +}; + +static struct clk_regmap t7_mipi_csi_phy1_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mipi_csi_phy1_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mipi_csi_phy1_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mipi_csi_phy1 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_mipi_csi_phy1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mipi_csi_phy1_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mipi_csi_phy =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mipi_csi_phy", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mipi_csi_phy0.hw, + &t7_mipi_csi_phy1.hw + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data t7_mipi_isp_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "mpll2", }, + { .fw_name =3D "mpll3", }, + { .fw_name =3D "gp1", }, +}; + +static struct clk_regmap t7_mipi_isp_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_MIPI_ISP_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mipi_isp_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_mipi_isp_parents, + .num_parents =3D ARRAY_SIZE(t7_mipi_isp_parents), + }, +}; + +static struct clk_regmap t7_mipi_isp_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_MIPI_ISP_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mipi_isp_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mipi_isp_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mipi_isp =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_MIPI_ISP_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_mipi_isp", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mipi_isp_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_ts_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_TS_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_ts_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_ts =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_TS_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_ts", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_ts_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) + * muxed by a glitch-free switch. + */ +static const struct clk_parent_data t7_mali_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "gp0", }, + { .fw_name =3D "gp1", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, +}; + +static struct clk_regmap t7_mali_0_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_MALI_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mali_0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_mali_parents, + .num_parents =3D ARRAY_SIZE(t7_mali_parents), + }, +}; + +static struct clk_regmap t7_mali_0_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_MALI_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mali_0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mali_0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mali_0 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_MALI_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mali_0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mali_0_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mali_1_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_MALI_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mali_1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_mali_parents, + .num_parents =3D ARRAY_SIZE(t7_mali_parents), + }, +}; + +static struct clk_regmap t7_mali_1_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_MALI_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mali_1_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mali_1_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mali_1 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_MALI_CLK_CTRL, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mali_1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mali_1_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_mali =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_MALI_CLK_CTRL, + .mask =3D 1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_mali", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_mali_0.hw, + &t7_mali_1.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static u32 t7_eth_rmii_table[] =3D { 0, 7 }; + +static const struct clk_parent_data t7_eth_rmii_parents[] =3D { + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "rmii_pad", }, +}; + +static struct clk_regmap t7_eth_rmii_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_ETH_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + .table =3D t7_eth_rmii_table + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_eth_rmii_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_eth_rmii_parents, + .num_parents =3D ARRAY_SIZE(t7_eth_rmii_parents), + }, +}; + +static struct clk_regmap t7_eth_rmii_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_ETH_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_eth_rmii_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_eth_rmii_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_eth_rmii =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_ETH_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_eth_rmii", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_eth_rmii_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor t7_fdiv2_div8 =3D { + .mult =3D 1, + .div =3D 8, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_fdiv2_div8", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap t7_eth_125m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_ETH_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_eth_125m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_fdiv2_div8.hw + }, + .num_parents =3D 1, + }, +}; + +static const struct clk_parent_data t7_sd_emmc_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "hifi", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "mpll2", }, + { .fw_name =3D "mpll3", }, + { .fw_name =3D "gp0", }, +}; + +static struct clk_regmap t7_sd_emmc_c_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_NAND_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_sd_emmc_c_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_sd_emmc_parents, + .num_parents =3D ARRAY_SIZE(t7_sd_emmc_parents), + }, +}; + +static struct clk_regmap t7_sd_emmc_c_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_NAND_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_sd_emmc_c_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_sd_emmc_c_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sd_emmc_c =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_NAND_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_sd_emmc_c", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_sd_emmc_c_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sd_emmc_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_SD_EMMC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_sd_emmc_a_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_sd_emmc_parents, + .num_parents =3D ARRAY_SIZE(t7_sd_emmc_parents), + }, +}; + +static struct clk_regmap t7_sd_emmc_a_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_SD_EMMC_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_sd_emmc_a_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_sd_emmc_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sd_emmc_a =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_SD_EMMC_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_sd_emmc_a", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_sd_emmc_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sd_emmc_b_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_SD_EMMC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_sd_emmc_b_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D t7_sd_emmc_parents, + .num_parents =3D ARRAY_SIZE(t7_sd_emmc_parents), + }, +}; + +static struct clk_regmap t7_sd_emmc_b_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLKCTRL_SD_EMMC_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "t7_sd_emmc_b_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_sd_emmc_b_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_sd_emmc_b =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_SD_EMMC_CLK_CTRL, + .bit_idx =3D 23, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_sd_emmc_b", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_sd_emmc_b_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define SPI_PWM_CLK_MUX(_name, _reg, _mask, _shift, _parent_data) { \ + .data =3D &(struct clk_regmap_mux_data) { \ + .offset =3D _reg, \ + .mask =3D _mask, \ + .shift =3D _shift, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name "_sel", \ + .ops =3D &clk_regmap_mux_ops, \ + .parent_data =3D _parent_data, \ + .num_parents =3D ARRAY_SIZE(_parent_data), \ + }, \ +} + +#define SPI_PWM_CLK_DIV(_name, _reg, _shift, _width, _parent) { \ + .data =3D &(struct clk_regmap_div_data) { \ + .offset =3D _reg, \ + .shift =3D _shift, \ + .width =3D _width, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name "_div", \ + .ops =3D &clk_regmap_divider_ops, \ + .parent_hws =3D (const struct clk_hw *[]) { \ + &_parent.hw \ + }, \ + .num_parents =3D 1, \ + .flags =3D CLK_SET_RATE_PARENT, \ + }, \ +} + +#define SPI_PWM_CLK_GATE(_name, _reg, _bit, _parent) { \ + .data =3D &(struct clk_regmap_gate_data) { \ + .offset =3D _reg, \ + .bit_idx =3D _bit, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_hws =3D (const struct clk_hw *[]) { \ + &_parent.hw \ + }, \ + .num_parents =3D 1, \ + .flags =3D CLK_SET_RATE_PARENT, \ + }, \ +} + +static const struct clk_parent_data t7_spicc_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "sys", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "gp1", }, +}; + +static struct clk_regmap t7_spicc0_sel =3D + SPI_PWM_CLK_MUX(t7_spicc0, CLKCTRL_SPICC_CLK_CTRL, 0x7, 7, t7_spicc_paren= ts); +static struct clk_regmap t7_spicc0_div =3D + SPI_PWM_CLK_DIV(t7_spicc0, CLKCTRL_SPICC_CLK_CTRL, 0, 6, t7_spicc0_sel); +static struct clk_regmap t7_spicc0 =3D + SPI_PWM_CLK_GATE(t7_spicc0, CLKCTRL_SPICC_CLK_CTRL, 6, t7_spicc0_div); + +static struct clk_regmap t7_spicc1_sel =3D + SPI_PWM_CLK_MUX(t7_spicc1, CLKCTRL_SPICC_CLK_CTRL, 0x7, 23, t7_spicc_pare= nts); +static struct clk_regmap t7_spicc1_div =3D + SPI_PWM_CLK_DIV(t7_spicc1, CLKCTRL_SPICC_CLK_CTRL, 16, 6, t7_spicc1_sel); +static struct clk_regmap t7_spicc1 =3D + SPI_PWM_CLK_GATE(t7_spicc1, CLKCTRL_SPICC_CLK_CTRL, 22, t7_spicc1_div); + +static struct clk_regmap t7_spicc2_sel =3D + SPI_PWM_CLK_MUX(t7_spicc2, CLKCTRL_SPICC_CLK_CTRL1, 0x7, 7, t7_spicc_pare= nts); +static struct clk_regmap t7_spicc2_div =3D + SPI_PWM_CLK_DIV(t7_spicc2, CLKCTRL_SPICC_CLK_CTRL1, 0, 6, t7_spicc2_sel); +static struct clk_regmap t7_spicc2 =3D + SPI_PWM_CLK_GATE(t7_spicc2, CLKCTRL_SPICC_CLK_CTRL1, 6, t7_spicc2_div); + +static struct clk_regmap t7_spicc3_sel =3D + SPI_PWM_CLK_MUX(t7_spicc3, CLKCTRL_SPICC_CLK_CTRL1, 0x7, 23, t7_spicc_par= ents); +static struct clk_regmap t7_spicc3_div =3D + SPI_PWM_CLK_DIV(t7_spicc3, CLKCTRL_SPICC_CLK_CTRL1, 16, 6, t7_spicc3_sel); +static struct clk_regmap t7_spicc3 =3D + SPI_PWM_CLK_GATE(t7_spicc3, CLKCTRL_SPICC_CLK_CTRL1, 22, t7_spicc3_div); + +static struct clk_regmap t7_spicc4_sel =3D + SPI_PWM_CLK_MUX(t7_spicc4, CLKCTRL_SPICC_CLK_CTRL2, 0x7, 7, t7_spicc_pare= nts); +static struct clk_regmap t7_spicc4_div =3D + SPI_PWM_CLK_DIV(t7_spicc4, CLKCTRL_SPICC_CLK_CTRL2, 0, 6, t7_spicc4_sel); +static struct clk_regmap t7_spicc4 =3D + SPI_PWM_CLK_GATE(t7_spicc4, CLKCTRL_SPICC_CLK_CTRL2, 6, t7_spicc4_div); + +static struct clk_regmap t7_spicc5_sel =3D + SPI_PWM_CLK_MUX(t7_spicc5, CLKCTRL_SPICC_CLK_CTRL2, 0x7, 23, t7_spicc_par= ents); +static struct clk_regmap t7_spicc5_div =3D + SPI_PWM_CLK_DIV(t7_spicc5, CLKCTRL_SPICC_CLK_CTRL2, 16, 6, t7_spicc5_sel); +static struct clk_regmap t7_spicc5 =3D + SPI_PWM_CLK_GATE(t7_spicc5, CLKCTRL_SPICC_CLK_CTRL2, 22, t7_spicc5_div); + +static struct clk_regmap t7_saradc_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_SAR_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_saradc_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .fw_name =3D "sys", }, + }, + .num_parents =3D 2, + }, +}; + +static struct clk_regmap t7_saradc_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_SAR_CLK_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_saradc_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_saradc_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap t7_saradc =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_SAR_CLK_CTRL0, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_saradc", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &t7_saradc_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data t7_pwm_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "vid_pll0", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, +}; + +static struct clk_regmap t7_pwm_a_sel =3D + SPI_PWM_CLK_MUX(t7_pwm, CLKCTRL_PWM_CLK_AB_CTRL, 0x3, 9, t7_pwm_parents); +static struct clk_regmap t7_pwm_a_div =3D + SPI_PWM_CLK_DIV(t7_pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8, t7_pwm_a_sel); +static struct clk_regmap t7_pwm_a =3D + SPI_PWM_CLK_GATE(t7_pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8, t7_pwm_a_div); + +static struct clk_regmap t7_pwm_b_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 0x3, 25, t7_pwm_parent= s); +static struct clk_regmap t7_pwm_b_div =3D + SPI_PWM_CLK_DIV(t7_pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8, t7_pwm_b_sel); +static struct clk_regmap t7_pwm_b =3D + SPI_PWM_CLK_GATE(t7_pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24, t7_pwm_b_div); + +static struct clk_regmap t7_pwm_c_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0x3, 9, t7_pwm_parents= ); +static struct clk_regmap t7_pwm_c_div =3D + SPI_PWM_CLK_DIV(t7_pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8, t7_pwm_c_sel); +static struct clk_regmap t7_pwm_c =3D + SPI_PWM_CLK_GATE(t7_pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8, t7_pwm_c_div); + +static struct clk_regmap t7_pwm_d_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 0x3, 25, t7_pwm_parent= s); +static struct clk_regmap t7_pwm_d_div =3D + SPI_PWM_CLK_DIV(t7_pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8, t7_pwm_d_sel); +static struct clk_regmap t7_pwm_d =3D + SPI_PWM_CLK_GATE(t7_pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24, t7_pwm_d_div); + +static struct clk_regmap t7_pwm_e_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0x3, 9, t7_pwm_parents= ); +static struct clk_regmap t7_pwm_e_div =3D + SPI_PWM_CLK_DIV(t7_pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8, t7_pwm_e_sel); +static struct clk_regmap t7_pwm_e =3D + SPI_PWM_CLK_GATE(t7_pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8, t7_pwm_e_div); + +static struct clk_regmap t7_pwm_f_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 0x3, 25, t7_pwm_parent= s); +static struct clk_regmap t7_pwm_f_div =3D + SPI_PWM_CLK_DIV(t7_pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8, t7_pwm_f_sel); +static struct clk_regmap t7_pwm_f =3D + SPI_PWM_CLK_GATE(t7_pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24, t7_pwm_f_div); + +static struct clk_regmap t7_pwm_ao_a_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0x3, 9, t7_pwm_p= arents); +static struct clk_regmap t7_pwm_ao_a_div =3D + SPI_PWM_CLK_DIV(t7_pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0, 8, t7_pwm_ao_= a_sel); +static struct clk_regmap t7_pwm_ao_a =3D + SPI_PWM_CLK_GATE(t7_pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 8, t7_pwm_ao_a_= div); + +static struct clk_regmap t7_pwm_ao_b_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0x3, 25, t7_pwm_= parents); +static struct clk_regmap t7_pwm_ao_b_div =3D + SPI_PWM_CLK_DIV(t7_pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 16, 8, t7_pwm_ao= _b_sel); +static struct clk_regmap t7_pwm_ao_b =3D + SPI_PWM_CLK_GATE(t7_pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 24, t7_pwm_ao_b= _div); + +static struct clk_regmap t7_pwm_ao_c_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0x3, 9, t7_pwm_p= arents); +static struct clk_regmap t7_pwm_ao_c_div =3D + SPI_PWM_CLK_DIV(t7_pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0, 8, t7_pwm_ao_= c_sel); +static struct clk_regmap t7_pwm_ao_c =3D + SPI_PWM_CLK_GATE(t7_pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 8, t7_pwm_ao_c_= div); + +static struct clk_regmap t7_pwm_ao_d_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0x3, 25, t7_pwm_= parents); +static struct clk_regmap t7_pwm_ao_d_div =3D + SPI_PWM_CLK_DIV(t7_pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 16, 8, t7_pwm_ao= _d_sel); +static struct clk_regmap t7_pwm_ao_d =3D + SPI_PWM_CLK_GATE(t7_pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 24, t7_pwm_ao_d= _div); + +static struct clk_regmap t7_pwm_ao_e_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0x3, 9, t7_pwm_p= arents); +static struct clk_regmap t7_pwm_ao_e_div =3D + SPI_PWM_CLK_DIV(t7_pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0, 8, t7_pwm_ao_= e_sel); +static struct clk_regmap t7_pwm_ao_e =3D + SPI_PWM_CLK_GATE(t7_pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 8, t7_pwm_ao_e_= div); + +static struct clk_regmap t7_pwm_ao_f_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0x3, 25, t7_pwm_= parents); +static struct clk_regmap t7_pwm_ao_f_div =3D + SPI_PWM_CLK_DIV(t7_pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 16, 8, t7_pwm_ao= _f_sel); +static struct clk_regmap t7_pwm_ao_f =3D + SPI_PWM_CLK_GATE(t7_pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 24, t7_pwm_ao_f= _div); + +static struct clk_regmap t7_pwm_ao_g_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0x3, 9, t7_pwm_p= arents); +static struct clk_regmap t7_pwm_ao_g_div =3D + SPI_PWM_CLK_DIV(t7_pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0, 8, t7_pwm_ao_= g_sel); +static struct clk_regmap t7_pwm_ao_g =3D + SPI_PWM_CLK_GATE(t7_pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 8, t7_pwm_ao_g_= div); + +static struct clk_regmap t7_pwm_ao_h_sel =3D + SPI_PWM_CLK_MUX(t7_pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0x3, 25, t7_pwm_= parents); +static struct clk_regmap t7_pwm_ao_h_div =3D + SPI_PWM_CLK_DIV(t7_pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 16, 8, t7_pwm_ao= _h_sel); +static struct clk_regmap t7_pwm_ao_h =3D + SPI_PWM_CLK_GATE(t7_pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 24, t7_pwm_ao_h= _div); + +#define MESON_GATE(_name, _reg, _bit) MESON_PCLK_V2(_name, _reg, _bit, sy= s) + +static MESON_GATE(t7_sys_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0); +static MESON_GATE(t7_sys_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1); +static MESON_GATE(t7_sys_mipi_dsi_a, CLKCTRL_SYS_CLK_EN0_REG0, 2); +static MESON_GATE(t7_sys_mipi_dsi_b, CLKCTRL_SYS_CLK_EN0_REG0, 3); +static MESON_GATE(t7_sys_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4); +static MESON_GATE(t7_sys_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6); +static MESON_GATE(t7_sys_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13); +static MESON_GATE(t7_sys_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14); +static MESON_GATE(t7_sys_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16); +static MESON_GATE(t7_sys_gdc, CLKCTRL_SYS_CLK_EN0_REG0, 17); +static MESON_GATE(t7_sys_deswarp, CLKCTRL_SYS_CLK_EN0_REG0, 18); +static MESON_GATE(t7_sys_ampipe_nand, CLKCTRL_SYS_CLK_EN0_REG0, 19); +static MESON_GATE(t7_sys_ampipe_eth, CLKCTRL_SYS_CLK_EN0_REG0, 20); +static MESON_GATE(t7_sys_am2axi0, CLKCTRL_SYS_CLK_EN0_REG0, 21); +static MESON_GATE(t7_sys_am2axi1, CLKCTRL_SYS_CLK_EN0_REG0, 22); +static MESON_GATE(t7_sys_am2axi2, CLKCTRL_SYS_CLK_EN0_REG0, 23); +static MESON_GATE(t7_sys_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24); +static MESON_GATE(t7_sys_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25); +static MESON_GATE(t7_sys_sdemmcc, CLKCTRL_SYS_CLK_EN0_REG0, 26); +static MESON_GATE(t7_sys_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27); +static MESON_GATE(t7_sys_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28); +static MESON_GATE(t7_sys_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29); +static MESON_GATE(t7_sys_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30); +static MESON_GATE(t7_sys_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31); +static MESON_GATE(t7_sys_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0); +static MESON_GATE(t7_sys_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3); +static MESON_GATE(t7_sys_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5); +static MESON_GATE(t7_sys_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6); +static MESON_GATE(t7_sys_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7); +static MESON_GATE(t7_sys_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8); +static MESON_GATE(t7_sys_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9); +static MESON_GATE(t7_sys_uart_f, CLKCTRL_SYS_CLK_EN0_REG1, 10); +static MESON_GATE(t7_sys_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11); +static MESON_GATE(t7_sys_spicc2, CLKCTRL_SYS_CLK_EN0_REG1, 12); +static MESON_GATE(t7_sys_spicc3, CLKCTRL_SYS_CLK_EN0_REG1, 13); +static MESON_GATE(t7_sys_spicc4, CLKCTRL_SYS_CLK_EN0_REG1, 14); +static MESON_GATE(t7_sys_ts_a73, CLKCTRL_SYS_CLK_EN0_REG1, 15); +static MESON_GATE(t7_sys_ts_a53, CLKCTRL_SYS_CLK_EN0_REG1, 16); +static MESON_GATE(t7_sys_spicc5, CLKCTRL_SYS_CLK_EN0_REG1, 17); +static MESON_GATE(t7_sys_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20); +static MESON_GATE(t7_sys_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21); +static MESON_GATE(t7_sys_spicc1, CLKCTRL_SYS_CLK_EN0_REG1, 22); +static MESON_GATE(t7_sys_pcie, CLKCTRL_SYS_CLK_EN0_REG1, 24); +static MESON_GATE(t7_sys_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26); +static MESON_GATE(t7_sys_pcie_phy, CLKCTRL_SYS_CLK_EN0_REG1, 27); +static MESON_GATE(t7_sys_i2c_ao_a, CLKCTRL_SYS_CLK_EN0_REG1, 28); +static MESON_GATE(t7_sys_i2c_ao_b, CLKCTRL_SYS_CLK_EN0_REG1, 29); +static MESON_GATE(t7_sys_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30); +static MESON_GATE(t7_sys_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31); +static MESON_GATE(t7_sys_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0); +static MESON_GATE(t7_sys_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1); +static MESON_GATE(t7_sys_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2); +static MESON_GATE(t7_sys_i2c_m_f, CLKCTRL_SYS_CLK_EN0_REG2, 3); +static MESON_GATE(t7_sys_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4); +static MESON_GATE(t7_sys_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5); +static MESON_GATE(t7_sys_hdmirx_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 8); +static MESON_GATE(t7_sys_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11); +static MESON_GATE(t7_sys_mipi_isp_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 17); +static MESON_GATE(t7_sys_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18); +static MESON_GATE(t7_sys_pclk_sys_apb, CLKCTRL_SYS_CLK_EN0_REG2, 19); +static MESON_GATE(t7_sys_a73pclk_apb, CLKCTRL_SYS_CLK_EN0_REG2, 20); +static MESON_GATE(t7_sys_dspa, CLKCTRL_SYS_CLK_EN0_REG2, 21); +static MESON_GATE(t7_sys_dspb, CLKCTRL_SYS_CLK_EN0_REG2, 22); +static MESON_GATE(t7_sys_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25); +static MESON_GATE(t7_sys_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28); +static MESON_GATE(t7_sys_ts_gpu, CLKCTRL_SYS_CLK_EN0_REG2, 31); +static MESON_GATE(t7_sys_ts_nna, CLKCTRL_SYS_CLK_EN0_REG3, 0); +static MESON_GATE(t7_sys_ts_vpu, CLKCTRL_SYS_CLK_EN0_REG3, 1); +static MESON_GATE(t7_sys_ts_hevc, CLKCTRL_SYS_CLK_EN0_REG3, 2); +static MESON_GATE(t7_sys_pwm_ao_ab, CLKCTRL_SYS_CLK_EN0_REG3, 3); +static MESON_GATE(t7_sys_pwm_ao_cd, CLKCTRL_SYS_CLK_EN0_REG3, 4); +static MESON_GATE(t7_sys_pwm_ao_ef, CLKCTRL_SYS_CLK_EN0_REG3, 5); +static MESON_GATE(t7_sys_pwm_ao_gh, CLKCTRL_SYS_CLK_EN0_REG3, 6); +static MESON_GATE(t7_sys_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7); +static MESON_GATE(t7_sys_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8); +static MESON_GATE(t7_sys_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9); + +/* + * sys_gic provides the clock for GIC(Generic Interrupt Controller). + * After clock is disabled, The GIC cannot work properly. At present, the = driver + * used by our GIC is the public driver in kernel, and there is no managem= ent + * clock in the driver. + */ +static struct clk_regmap t7_sys_gic =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_SYS_CLK_EN0_REG2, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "t7_sys_gic", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "sys", + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + }, +}; + +/* Array of all clocks registered by this provider */ +static struct clk_hw *t7_periphs_hw_clks[] =3D { + [CLKID_RTC_32K_IN] =3D &t7_rtc_32k_in.hw, + [CLKID_RTC_32K_DIV] =3D &t7_rtc_32k_div.hw, + [CLKID_RTC_32K_FORCE_SEL] =3D &t7_rtc_32k_force_sel.hw, + [CLKID_RTC_32K_OUT] =3D &t7_rtc_32k_out.hw, + [CLKID_RTC_32K_MUX0_0] =3D &t7_rtc_32k_mux0_0.hw, + [CLKID_RTC_32K_MUX0_1] =3D &t7_rtc_32k_mux0_1.hw, + [CLKID_RTC] =3D &t7_rtc.hw, + [CLKID_CECB_32K_IN] =3D &t7_cecb_32k_in.hw, + [CLKID_CECB_32K_DIV] =3D &t7_cecb_32k_div.hw, + [CLKID_CECB_32K_SEL_PRE] =3D &t7_cecb_32k_sel_pre.hw, + [CLKID_CECB_32K_SEL] =3D &t7_cecb_32k_sel.hw, + [CLKID_CECA_32K_IN] =3D &t7_ceca_32k_in.hw, + [CLKID_CECA_32K_DIV] =3D &t7_ceca_32k_div.hw, + [CLKID_CECA_32K_SEL_PRE] =3D &t7_ceca_32k_sel_pre.hw, + [CLKID_CECA_32K_SEL] =3D &t7_ceca_32k_sel.hw, + [CLKID_CECA_32K] =3D &t7_ceca_32k_out.hw, + [CLKID_CECB_32K] =3D &t7_cecb_32k_out.hw, + [CLKID_SC_SEL] =3D &t7_sc_sel.hw, + [CLKID_SC_DIV] =3D &t7_sc_div.hw, + [CLKID_SC] =3D &t7_sc.hw, + [CLKID_DSPA_A_SEL] =3D &t7_dspa_a_sel.hw, + [CLKID_DSPA_A_DIV] =3D &t7_dspa_a_div.hw, + [CLKID_DSPA_A] =3D &t7_dspa_a.hw, + [CLKID_DSPA_B_SEL] =3D &t7_dspa_b_sel.hw, + [CLKID_DSPA_B_DIV] =3D &t7_dspa_b_div.hw, + [CLKID_DSPA_B] =3D &t7_dspa_b.hw, + [CLKID_DSPA] =3D &t7_dspa.hw, + [CLKID_DSPB_A_SEL] =3D &t7_dspb_a_sel.hw, + [CLKID_DSPB_A_DIV] =3D &t7_dspb_a_div.hw, + [CLKID_DSPB_A] =3D &t7_dspb_a.hw, + [CLKID_DSPB_B_SEL] =3D &t7_dspb_b_sel.hw, + [CLKID_DSPB_B_DIV] =3D &t7_dspb_b_div.hw, + [CLKID_DSPB_B] =3D &t7_dspb_b.hw, + [CLKID_DSPB] =3D &t7_dspb.hw, + [CLKID_CLK_24M] =3D &t7_clk_24m.hw, + [CLKID_CLK_24M_DIV2] =3D &t7_clk_24m_div2.hw, + [CLKID_CLK_12M] =3D &t7_clk_12m.hw, + [CLKID_ANAKIN_0_SEL] =3D &t7_anakin_0_sel.hw, + [CLKID_ANAKIN_0_DIV] =3D &t7_anakin_0_div.hw, + [CLKID_ANAKIN_0] =3D &t7_anakin_0.hw, + [CLKID_ANAKIN_1_SEL] =3D &t7_anakin_1_sel.hw, + [CLKID_ANAKIN_1_DIV] =3D &t7_anakin_1_div.hw, + [CLKID_ANAKIN_1] =3D &t7_anakin_1.hw, + [CLKID_ANAKIN] =3D &t7_anakin.hw, + [CLKID_ANAKIN_CLK] =3D &t7_anakin_clk.hw, + [CLKID_FCLK_DIV2_DIVN_PRE] =3D &t7_fdiv2_divn_pre.hw, + [CLKID_FCLK_DIV2_DIVN] =3D &t7_fdiv2_divn.hw, + [CLKID_MIPI_CSI_PHY_0_SEL] =3D &t7_mipi_csi_phy0_sel.hw, + [CLKID_MIPI_CSI_PHY_0_DIV] =3D &t7_mipi_csi_phy0_div.hw, + [CLKID_MIPI_CSI_PHY_0] =3D &t7_mipi_csi_phy0.hw, + [CLKID_MIPI_CSI_PHY_1_SEL] =3D &t7_mipi_csi_phy1_sel.hw, + [CLKID_MIPI_CSI_PHY_1_DIV] =3D &t7_mipi_csi_phy1_div.hw, + [CLKID_MIPI_CSI_PHY_1] =3D &t7_mipi_csi_phy1.hw, + [CLKID_MIPI_CSI_PHY] =3D &t7_mipi_csi_phy.hw, + [CLKID_MIPI_ISP_SEL] =3D &t7_mipi_isp_sel.hw, + [CLKID_MIPI_ISP_DIV] =3D &t7_mipi_isp_div.hw, + [CLKID_MIPI_ISP] =3D &t7_mipi_isp.hw, + [CLKID_TS_DIV] =3D &t7_ts_div.hw, + [CLKID_TS] =3D &t7_ts.hw, + [CLKID_MALI_0_SEL] =3D &t7_mali_0_sel.hw, + [CLKID_MALI_0_DIV] =3D &t7_mali_0_div.hw, + [CLKID_MALI_0] =3D &t7_mali_0.hw, + [CLKID_MALI_1_SEL] =3D &t7_mali_1_sel.hw, + [CLKID_MALI_1_DIV] =3D &t7_mali_1_div.hw, + [CLKID_MALI_1] =3D &t7_mali_1.hw, + [CLKID_MALI] =3D &t7_mali.hw, + [CLKID_ETH_RMII_SEL] =3D &t7_eth_rmii_sel.hw, + [CLKID_ETH_RMII_DIV] =3D &t7_eth_rmii_div.hw, + [CLKID_ETH_RMII] =3D &t7_eth_rmii.hw, + [CLKID_FCLK_DIV2_DIV8] =3D &t7_fdiv2_div8.hw, + [CLKID_ETH_125M] =3D &t7_eth_125m.hw, + [CLKID_SD_EMMC_C_SEL] =3D &t7_sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] =3D &t7_sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] =3D &t7_sd_emmc_c.hw, + [CLKID_SD_EMMC_A_SEL] =3D &t7_sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] =3D &t7_sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] =3D &t7_sd_emmc_a.hw, + [CLKID_SD_EMMC_B_SEL] =3D &t7_sd_emmc_b_sel.hw, + [CLKID_SD_EMMC_B_DIV] =3D &t7_sd_emmc_b_div.hw, + [CLKID_SD_EMMC_B] =3D &t7_sd_emmc_b.hw, + [CLKID_SPICC0_SEL] =3D &t7_spicc0_sel.hw, + [CLKID_SPICC0_DIV] =3D &t7_spicc0_div.hw, + [CLKID_SPICC0] =3D &t7_spicc0.hw, + [CLKID_SPICC1_SEL] =3D &t7_spicc1_sel.hw, + [CLKID_SPICC1_DIV] =3D &t7_spicc1_div.hw, + [CLKID_SPICC1] =3D &t7_spicc1.hw, + [CLKID_SPICC2_SEL] =3D &t7_spicc2_sel.hw, + [CLKID_SPICC2_DIV] =3D &t7_spicc2_div.hw, + [CLKID_SPICC2] =3D &t7_spicc2.hw, + [CLKID_SPICC3_SEL] =3D &t7_spicc3_sel.hw, + [CLKID_SPICC3_DIV] =3D &t7_spicc3_div.hw, + [CLKID_SPICC3] =3D &t7_spicc3.hw, + [CLKID_SPICC4_SEL] =3D &t7_spicc4_sel.hw, + [CLKID_SPICC4_DIV] =3D &t7_spicc4_div.hw, + [CLKID_SPICC4] =3D &t7_spicc4.hw, + [CLKID_SPICC5_SEL] =3D &t7_spicc5_sel.hw, + [CLKID_SPICC5_DIV] =3D &t7_spicc5_div.hw, + [CLKID_SPICC5] =3D &t7_spicc5.hw, + [CLKID_SARADC_SEL] =3D &t7_saradc_sel.hw, + [CLKID_SARADC_DIV] =3D &t7_saradc_div.hw, + [CLKID_SARADC] =3D &t7_saradc.hw, + [CLKID_PWM_A_SEL] =3D &t7_pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &t7_pwm_a_div.hw, + [CLKID_PWM_A] =3D &t7_pwm_a.hw, + [CLKID_PWM_B_SEL] =3D &t7_pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &t7_pwm_b_div.hw, + [CLKID_PWM_B] =3D &t7_pwm_b.hw, + [CLKID_PWM_C_SEL] =3D &t7_pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &t7_pwm_c_div.hw, + [CLKID_PWM_C] =3D &t7_pwm_c.hw, + [CLKID_PWM_D_SEL] =3D &t7_pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &t7_pwm_d_div.hw, + [CLKID_PWM_D] =3D &t7_pwm_d.hw, + [CLKID_PWM_E_SEL] =3D &t7_pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &t7_pwm_e_div.hw, + [CLKID_PWM_E] =3D &t7_pwm_e.hw, + [CLKID_PWM_F_SEL] =3D &t7_pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &t7_pwm_f_div.hw, + [CLKID_PWM_F] =3D &t7_pwm_f.hw, + [CLKID_PWM_AO_A_SEL] =3D &t7_pwm_ao_a_sel.hw, + [CLKID_PWM_AO_A_DIV] =3D &t7_pwm_ao_a_div.hw, + [CLKID_PWM_AO_A] =3D &t7_pwm_ao_a.hw, + [CLKID_PWM_AO_B_SEL] =3D &t7_pwm_ao_b_sel.hw, + [CLKID_PWM_AO_B_DIV] =3D &t7_pwm_ao_b_div.hw, + [CLKID_PWM_AO_B] =3D &t7_pwm_ao_b.hw, + [CLKID_PWM_AO_C_SEL] =3D &t7_pwm_ao_c_sel.hw, + [CLKID_PWM_AO_C_DIV] =3D &t7_pwm_ao_c_div.hw, + [CLKID_PWM_AO_C] =3D &t7_pwm_ao_c.hw, + [CLKID_PWM_AO_D_SEL] =3D &t7_pwm_ao_d_sel.hw, + [CLKID_PWM_AO_D_DIV] =3D &t7_pwm_ao_d_div.hw, + [CLKID_PWM_AO_D] =3D &t7_pwm_ao_d.hw, + [CLKID_PWM_AO_E_SEL] =3D &t7_pwm_ao_e_sel.hw, + [CLKID_PWM_AO_E_DIV] =3D &t7_pwm_ao_e_div.hw, + [CLKID_PWM_AO_E] =3D &t7_pwm_ao_e.hw, + [CLKID_PWM_AO_F_SEL] =3D &t7_pwm_ao_f_sel.hw, + [CLKID_PWM_AO_F_DIV] =3D &t7_pwm_ao_f_div.hw, + [CLKID_PWM_AO_F] =3D &t7_pwm_ao_f.hw, + [CLKID_PWM_AO_G_SEL] =3D &t7_pwm_ao_g_sel.hw, + [CLKID_PWM_AO_G_DIV] =3D &t7_pwm_ao_g_div.hw, + [CLKID_PWM_AO_G] =3D &t7_pwm_ao_g.hw, + [CLKID_PWM_AO_H_SEL] =3D &t7_pwm_ao_h_sel.hw, + [CLKID_PWM_AO_H_DIV] =3D &t7_pwm_ao_h_div.hw, + [CLKID_PWM_AO_H] =3D &t7_pwm_ao_h.hw, + [CLKID_SYS_DDR] =3D &t7_sys_ddr.hw, + [CLKID_SYS_DOS] =3D &t7_sys_dos.hw, + [CLKID_SYS_MIPI_DSI_A] =3D &t7_sys_mipi_dsi_a.hw, + [CLKID_SYS_MIPI_DSI_B] =3D &t7_sys_mipi_dsi_b.hw, + [CLKID_SYS_ETHPHY] =3D &t7_sys_ethphy.hw, + [CLKID_SYS_MALI] =3D &t7_sys_mali.hw, + [CLKID_SYS_AOCPU] =3D &t7_sys_aocpu.hw, + [CLKID_SYS_AUCPU] =3D &t7_sys_aucpu.hw, + [CLKID_SYS_CEC] =3D &t7_sys_cec.hw, + [CLKID_SYS_GDC] =3D &t7_sys_gdc.hw, + [CLKID_SYS_DESWARP] =3D &t7_sys_deswarp.hw, + [CLKID_SYS_AMPIPE_NAND] =3D &t7_sys_ampipe_nand.hw, + [CLKID_SYS_AMPIPE_ETH] =3D &t7_sys_ampipe_eth.hw, + [CLKID_SYS_AM2AXI0] =3D &t7_sys_am2axi0.hw, + [CLKID_SYS_AM2AXI1] =3D &t7_sys_am2axi1.hw, + [CLKID_SYS_AM2AXI2] =3D &t7_sys_am2axi2.hw, + [CLKID_SYS_SD_EMMC_A] =3D &t7_sys_sdemmca.hw, + [CLKID_SYS_SD_EMMC_B] =3D &t7_sys_sdemmcb.hw, + [CLKID_SYS_SD_EMMC_C] =3D &t7_sys_sdemmcc.hw, + [CLKID_SYS_SMARTCARD] =3D &t7_sys_smartcard.hw, + [CLKID_SYS_ACODEC] =3D &t7_sys_acodec.hw, + [CLKID_SYS_SPIFC] =3D &t7_sys_spifc.hw, + [CLKID_SYS_MSR_CLK] =3D &t7_sys_msr_clk.hw, + [CLKID_SYS_IR_CTRL] =3D &t7_sys_ir_ctrl.hw, + [CLKID_SYS_AUDIO] =3D &t7_sys_audio.hw, + [CLKID_SYS_ETH] =3D &t7_sys_eth.hw, + [CLKID_SYS_UART_A] =3D &t7_sys_uart_a.hw, + [CLKID_SYS_UART_B] =3D &t7_sys_uart_b.hw, + [CLKID_SYS_UART_C] =3D &t7_sys_uart_c.hw, + [CLKID_SYS_UART_D] =3D &t7_sys_uart_d.hw, + [CLKID_SYS_UART_E] =3D &t7_sys_uart_e.hw, + [CLKID_SYS_UART_F] =3D &t7_sys_uart_f.hw, + [CLKID_SYS_AIFIFO] =3D &t7_sys_aififo.hw, + [CLKID_SYS_SPICC2] =3D &t7_sys_spicc2.hw, + [CLKID_SYS_SPICC3] =3D &t7_sys_spicc3.hw, + [CLKID_SYS_SPICC4] =3D &t7_sys_spicc4.hw, + [CLKID_SYS_TS_A73] =3D &t7_sys_ts_a73.hw, + [CLKID_SYS_TS_A53] =3D &t7_sys_ts_a53.hw, + [CLKID_SYS_SPICC5] =3D &t7_sys_spicc5.hw, + [CLKID_SYS_G2D] =3D &t7_sys_g2d.hw, + [CLKID_SYS_SPICC0] =3D &t7_sys_spicc0.hw, + [CLKID_SYS_SPICC1] =3D &t7_sys_spicc1.hw, + [CLKID_SYS_PCIE] =3D &t7_sys_pcie.hw, + [CLKID_SYS_USB] =3D &t7_sys_usb.hw, + [CLKID_SYS_PCIE_PHY] =3D &t7_sys_pcie_phy.hw, + [CLKID_SYS_I2C_AO_A] =3D &t7_sys_i2c_ao_a.hw, + [CLKID_SYS_I2C_AO_B] =3D &t7_sys_i2c_ao_b.hw, + [CLKID_SYS_I2C_M_A] =3D &t7_sys_i2c_m_a.hw, + [CLKID_SYS_I2C_M_B] =3D &t7_sys_i2c_m_b.hw, + [CLKID_SYS_I2C_M_C] =3D &t7_sys_i2c_m_c.hw, + [CLKID_SYS_I2C_M_D] =3D &t7_sys_i2c_m_d.hw, + [CLKID_SYS_I2C_M_E] =3D &t7_sys_i2c_m_e.hw, + [CLKID_SYS_I2C_M_F] =3D &t7_sys_i2c_m_f.hw, + [CLKID_SYS_HDMITX_APB] =3D &t7_sys_hdmitx_apb.hw, + [CLKID_SYS_I2C_S_A] =3D &t7_sys_i2c_s_a.hw, + [CLKID_SYS_HDMIRX_PCLK] =3D &t7_sys_hdmirx_pclk.hw, + [CLKID_SYS_MMC_APB] =3D &t7_sys_mmc_apb.hw, + [CLKID_SYS_MIPI_ISP_PCLK] =3D &t7_sys_mipi_isp_pclk.hw, + [CLKID_SYS_RSA] =3D &t7_sys_rsa.hw, + [CLKID_SYS_PCLK_SYS_APB] =3D &t7_sys_pclk_sys_apb.hw, + [CLKID_SYS_A73PCLK_APB] =3D &t7_sys_a73pclk_apb.hw, + [CLKID_SYS_DSPA] =3D &t7_sys_dspa.hw, + [CLKID_SYS_DSPB] =3D &t7_sys_dspb.hw, + [CLKID_SYS_VPU_INTR] =3D &t7_sys_vpu_intr.hw, + [CLKID_SYS_SAR_ADC] =3D &t7_sys_sar_adc.hw, + [CLKID_SYS_GIC] =3D &t7_sys_gic.hw, + [CLKID_SYS_TS_GPU] =3D &t7_sys_ts_gpu.hw, + [CLKID_SYS_TS_NNA] =3D &t7_sys_ts_nna.hw, + [CLKID_SYS_TS_VPU] =3D &t7_sys_ts_vpu.hw, + [CLKID_SYS_TS_HEVC] =3D &t7_sys_ts_hevc.hw, + [CLKID_SYS_PWM_AB] =3D &t7_sys_pwm_ab.hw, + [CLKID_SYS_PWM_CD] =3D &t7_sys_pwm_cd.hw, + [CLKID_SYS_PWM_EF] =3D &t7_sys_pwm_ef.hw, + [CLKID_SYS_PWM_AO_AB] =3D &t7_sys_pwm_ao_ab.hw, + [CLKID_SYS_PWM_AO_CD] =3D &t7_sys_pwm_ao_cd.hw, + [CLKID_SYS_PWM_AO_EF] =3D &t7_sys_pwm_ao_ef.hw, + [CLKID_SYS_PWM_AO_GH] =3D &t7_sys_pwm_ao_gh.hw, +}; + +/* Convenience table to populate regmap in .probe */ +static struct clk_regmap *const t7_periphs_regmaps[] =3D { + &t7_rtc_32k_in, + &t7_rtc_32k_div, + &t7_rtc_32k_force_sel, + &t7_rtc_32k_out, + &t7_rtc_32k_mux0_0, + &t7_rtc_32k_mux0_1, + &t7_rtc, + &t7_cecb_32k_in, + &t7_cecb_32k_div, + &t7_cecb_32k_sel_pre, + &t7_cecb_32k_sel, + &t7_ceca_32k_in, + &t7_ceca_32k_div, + &t7_ceca_32k_sel_pre, + &t7_ceca_32k_sel, + &t7_ceca_32k_out, + &t7_cecb_32k_out, + &t7_sc_sel, + &t7_sc_div, + &t7_sc, + &t7_dspa_a_sel, + &t7_dspa_a_div, + &t7_dspa_a, + &t7_dspa_b_sel, + &t7_dspa_b_div, + &t7_dspa_b, + &t7_dspa, + &t7_dspb_a_sel, + &t7_dspb_a_div, + &t7_dspb_a, + &t7_dspb_b_sel, + &t7_dspb_b_div, + &t7_dspb_b, + &t7_dspb, + &t7_clk_24m, + &t7_clk_12m, + &t7_anakin_0_sel, + &t7_anakin_0_div, + &t7_anakin_0, + &t7_anakin_1_sel, + &t7_anakin_1_div, + &t7_anakin_1, + &t7_anakin, + &t7_anakin_clk, + &t7_fdiv2_divn_pre, + &t7_fdiv2_divn, + &t7_mipi_csi_phy0_sel, + &t7_mipi_csi_phy0_div, + &t7_mipi_csi_phy0, + &t7_mipi_csi_phy1_sel, + &t7_mipi_csi_phy1_div, + &t7_mipi_csi_phy1, + &t7_mipi_csi_phy, + &t7_mipi_isp_sel, + &t7_mipi_isp_div, + &t7_mipi_isp, + &t7_ts_div, + &t7_ts, + &t7_mali_0_sel, + &t7_mali_0_div, + &t7_mali_0, + &t7_mali_1_sel, + &t7_mali_1_div, + &t7_mali_1, + &t7_mali, + &t7_eth_rmii_sel, + &t7_eth_rmii_div, + &t7_eth_rmii, + &t7_eth_125m, + &t7_sd_emmc_c_sel, + &t7_sd_emmc_c_div, + &t7_sd_emmc_c, + &t7_sd_emmc_a_sel, + &t7_sd_emmc_a_div, + &t7_sd_emmc_a, + &t7_sd_emmc_b_sel, + &t7_sd_emmc_b_div, + &t7_sd_emmc_b, + &t7_spicc0_sel, + &t7_spicc0_div, + &t7_spicc0, + &t7_spicc1_sel, + &t7_spicc1_div, + &t7_spicc1, + &t7_spicc2_sel, + &t7_spicc2_div, + &t7_spicc2, + &t7_spicc3_sel, + &t7_spicc3_div, + &t7_spicc3, + &t7_spicc4_sel, + &t7_spicc4_div, + &t7_spicc4, + &t7_spicc5_sel, + &t7_spicc5_div, + &t7_spicc5, + &t7_saradc_sel, + &t7_saradc_div, + &t7_saradc, + &t7_pwm_a_sel, + &t7_pwm_a_div, + &t7_pwm_a, + &t7_pwm_b_sel, + &t7_pwm_b_div, + &t7_pwm_b, + &t7_pwm_c_sel, + &t7_pwm_c_div, + &t7_pwm_c, + &t7_pwm_d_sel, + &t7_pwm_d_div, + &t7_pwm_d, + &t7_pwm_e_sel, + &t7_pwm_e_div, + &t7_pwm_e, + &t7_pwm_f_sel, + &t7_pwm_f_div, + &t7_pwm_f, + &t7_pwm_ao_a_sel, + &t7_pwm_ao_a_div, + &t7_pwm_ao_a, + &t7_pwm_ao_b_sel, + &t7_pwm_ao_b_div, + &t7_pwm_ao_b, + &t7_pwm_ao_c_sel, + &t7_pwm_ao_c_div, + &t7_pwm_ao_c, + &t7_pwm_ao_d_sel, + &t7_pwm_ao_d_div, + &t7_pwm_ao_d, + &t7_pwm_ao_e_sel, + &t7_pwm_ao_e_div, + &t7_pwm_ao_e, + &t7_pwm_ao_f_sel, + &t7_pwm_ao_f_div, + &t7_pwm_ao_f, + &t7_pwm_ao_g_sel, + &t7_pwm_ao_g_div, + &t7_pwm_ao_g, + &t7_pwm_ao_h_sel, + &t7_pwm_ao_h_div, + &t7_pwm_ao_h, + &t7_pwm_ao_h, + &t7_sys_ddr, + &t7_sys_dos, + &t7_sys_mipi_dsi_a, + &t7_sys_mipi_dsi_b, + &t7_sys_ethphy, + &t7_sys_mali, + &t7_sys_aocpu, + &t7_sys_aucpu, + &t7_sys_cec, + &t7_sys_gdc, + &t7_sys_deswarp, + &t7_sys_ampipe_nand, + &t7_sys_ampipe_eth, + &t7_sys_am2axi0, + &t7_sys_am2axi1, + &t7_sys_am2axi2, + &t7_sys_sdemmca, + &t7_sys_sdemmcb, + &t7_sys_sdemmcc, + &t7_sys_smartcard, + &t7_sys_acodec, + &t7_sys_spifc, + &t7_sys_msr_clk, + &t7_sys_ir_ctrl, + &t7_sys_audio, + &t7_sys_eth, + &t7_sys_uart_a, + &t7_sys_uart_b, + &t7_sys_uart_c, + &t7_sys_uart_d, + &t7_sys_uart_e, + &t7_sys_uart_f, + &t7_sys_aififo, + &t7_sys_spicc2, + &t7_sys_spicc3, + &t7_sys_spicc4, + &t7_sys_ts_a73, + &t7_sys_ts_a53, + &t7_sys_spicc5, + &t7_sys_g2d, + &t7_sys_spicc0, + &t7_sys_spicc1, + &t7_sys_pcie, + &t7_sys_usb, + &t7_sys_pcie_phy, + &t7_sys_i2c_ao_a, + &t7_sys_i2c_ao_b, + &t7_sys_i2c_m_a, + &t7_sys_i2c_m_b, + &t7_sys_i2c_m_c, + &t7_sys_i2c_m_d, + &t7_sys_i2c_m_e, + &t7_sys_i2c_m_f, + &t7_sys_hdmitx_apb, + &t7_sys_i2c_s_a, + &t7_sys_hdmirx_pclk, + &t7_sys_mmc_apb, + &t7_sys_mipi_isp_pclk, + &t7_sys_rsa, + &t7_sys_pclk_sys_apb, + &t7_sys_a73pclk_apb, + &t7_sys_dspa, + &t7_sys_dspb, + &t7_sys_vpu_intr, + &t7_sys_sar_adc, + &t7_sys_gic, + &t7_sys_ts_gpu, + &t7_sys_ts_nna, + &t7_sys_ts_vpu, + &t7_sys_ts_hevc, + &t7_sys_pwm_ab, + &t7_sys_pwm_cd, + &t7_sys_pwm_ef, + &t7_sys_pwm_ao_ab, + &t7_sys_pwm_ao_cd, + &t7_sys_pwm_ao_ef, + &t7_sys_pwm_ao_gh, +}; + +static const struct regmap_config t7_periphs_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D CLKCTRL_SPICC_CLK_CTRL2 +}; + +static struct meson_clk_hw_data t7_periphs_clks =3D { + .hws =3D t7_periphs_hw_clks, + .num =3D ARRAY_SIZE(t7_periphs_hw_clks), +}; + +static int amlogic_t7_periphs_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + void __iomem *base; + struct regmap *map; + int i, ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + map =3D devm_regmap_init_mmio(dev, base, &t7_periphs_regmap_cfg); + if (IS_ERR(map)) + return PTR_ERR(map); + + /* Populate regmap for the regmap backed clocks */ + for (i =3D 0; i < ARRAY_SIZE(t7_periphs_regmaps); i++) + t7_periphs_regmaps[i]->map =3D map; + + for (i =3D 0; i < t7_periphs_clks.num; i++) { + ret =3D devm_clk_hw_register(dev, t7_periphs_clks.hws[i]); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &t7_periphs_clk= s); +} + +static const struct of_device_id t7_periphs_clkc_match_table[] =3D { + { .compatible =3D "amlogic,t7-peripherals-clkc", }, + {} +}; +MODULE_DEVICE_TABLE(of, t7_periphs_clkc_match_table); + +static struct platform_driver t7_periphs_clkc_driver =3D { + .probe =3D amlogic_t7_periphs_probe, + .driver =3D { + .name =3D "t7-peripherals-clkc", + .of_match_table =3D t7_periphs_clkc_match_table, + }, +}; + +MODULE_DESCRIPTION("Amlogic T7 Peripherals Clock Controller driver"); +module_platform_driver(t7_periphs_clkc_driver); +MODULE_AUTHOR("Jian Hu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.47.1