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[73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 006d021491bc7-60842b096desm303745eaf.30.2025.05.08.20.16.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 20:16:14 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, akpm@linux-foundation.org, ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, tmgross@umich.edu, gregkh@linuxfoundation.org, rafael@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, raag.jadav@intel.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, me@kloenk.dev, andrewjballance@gmail.com, fujita.tomonori@gmail.com, daniel.almeida@collabora.com Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 01/11] rust: helpers: io: use macro to generate io accessor functions Date: Thu, 8 May 2025 22:15:14 -0500 Message-ID: <20250509031524.2604087-2-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fiona Behrens Generate the `rust_helper_read{b,w,l,q}`, `rust_helper_write{b,w,l,q}` and the relaxed version using a C macro. This removes a lot of redundant code and is in preparation for pio functions which uses a similar C macro. Signed-off-by: Fiona Behrens Signed-off-by: Andrew Ballance --- rust/helpers/io.c | 104 +++++++++++++--------------------------------- 1 file changed, 28 insertions(+), 76 deletions(-) diff --git a/rust/helpers/io.c b/rust/helpers/io.c index 15ea187c5466..525af02f209e 100644 --- a/rust/helpers/io.c +++ b/rust/helpers/io.c @@ -12,90 +12,42 @@ void rust_helper_iounmap(void __iomem *addr) iounmap(addr); } =20 -u8 rust_helper_readb(const void __iomem *addr) -{ - return readb(addr); -} - -u16 rust_helper_readw(const void __iomem *addr) -{ - return readw(addr); -} - -u32 rust_helper_readl(const void __iomem *addr) -{ - return readl(addr); -} - +#define define_rust_mmio_read_helper(name, type) \ + type rust_helper_##name(void __iomem *addr) \ + { \ + return name(addr); \ + } + +#define define_rust_mmio_write_helper(name, type) \ + void rust_helper_##name(type value, void __iomem *addr) \ + { \ + name(value, addr); \ + } + +define_rust_mmio_read_helper(readb, u8); +define_rust_mmio_read_helper(readw, u16); +define_rust_mmio_read_helper(readl, u32); #ifdef CONFIG_64BIT -u64 rust_helper_readq(const void __iomem *addr) -{ - return readq(addr); -} +define_rust_mmio_read_helper(readq, u64); #endif =20 -void rust_helper_writeb(u8 value, void __iomem *addr) -{ - writeb(value, addr); -} - -void rust_helper_writew(u16 value, void __iomem *addr) -{ - writew(value, addr); -} - -void rust_helper_writel(u32 value, void __iomem *addr) -{ - writel(value, addr); -} - +define_rust_mmio_write_helper(writeb, u8); +define_rust_mmio_write_helper(writew, u16); +define_rust_mmio_write_helper(writel, u32); #ifdef CONFIG_64BIT -void rust_helper_writeq(u64 value, void __iomem *addr) -{ - writeq(value, addr); -} +define_rust_mmio_write_helper(writeq, u64); #endif =20 -u8 rust_helper_readb_relaxed(const void __iomem *addr) -{ - return readb_relaxed(addr); -} - -u16 rust_helper_readw_relaxed(const void __iomem *addr) -{ - return readw_relaxed(addr); -} - -u32 rust_helper_readl_relaxed(const void __iomem *addr) -{ - return readl_relaxed(addr); -} - +define_rust_mmio_read_helper(readb_relaxed, u8); +define_rust_mmio_read_helper(readw_relaxed, u16); +define_rust_mmio_read_helper(readl_relaxed, u32); #ifdef CONFIG_64BIT -u64 rust_helper_readq_relaxed(const void __iomem *addr) -{ - return readq_relaxed(addr); -} +define_rust_mmio_read_helper(readq_relaxed, u64); #endif =20 -void rust_helper_writeb_relaxed(u8 value, void __iomem *addr) -{ - writeb_relaxed(value, addr); -} - -void rust_helper_writew_relaxed(u16 value, void __iomem *addr) -{ - writew_relaxed(value, addr); -} - -void rust_helper_writel_relaxed(u32 value, void __iomem *addr) -{ - writel_relaxed(value, addr); -} - +define_rust_mmio_write_helper(writeb_relaxed, u8); +define_rust_mmio_write_helper(writew_relaxed, u16); +define_rust_mmio_write_helper(writel_relaxed, u32); #ifdef CONFIG_64BIT -void rust_helper_writeq_relaxed(u64 value, void __iomem *addr) -{ - writeq_relaxed(value, addr); -} +define_rust_mmio_write_helper(writeq_relaxed, u64); #endif --=20 2.49.0 From nobody Sun Feb 8 07:58:51 2026 Received: from mail-oo1-f45.google.com (mail-oo1-f45.google.com [209.85.161.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9804B64A8F; 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[73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 006d021491bc7-60842b096desm303745eaf.30.2025.05.08.20.16.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 20:16:19 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, akpm@linux-foundation.org, ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, tmgross@umich.edu, gregkh@linuxfoundation.org, rafael@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, raag.jadav@intel.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, me@kloenk.dev, andrewjballance@gmail.com, fujita.tomonori@gmail.com, daniel.almeida@collabora.com Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 02/11] rust: io: Replace Io with MMIo using IoAccess trait Date: Thu, 8 May 2025 22:15:15 -0500 Message-ID: <20250509031524.2604087-3-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fiona Behrens Replace the Io struct with a new MMIo struct that uses the different traits (`IoAccess`, `IoAccess64`, `IoAccessRelaxed` and `IoAccess64Relaxed). This allows to later implement PortIo and a generic Io framework. Signed-off-by: Fiona Behrens Co-developed-by: Andrew Ballance Signed-off-by: Andrew Ballance --- rust/kernel/io.rs | 443 +++++++++++++++++++++++++++------------------- 1 file changed, 259 insertions(+), 184 deletions(-) diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 72d80a6f131e..19bbf802027c 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -7,6 +7,211 @@ use crate::error::{code::EINVAL, Result}; use crate::{bindings, build_assert}; =20 +/// Private macro to define the [`IoAccess`] functions. +macro_rules! define_io_access_function { + (@read_derived $(#[$attr:meta])* $name_unchecked:ident, $vis:vis $name= :ident, $try_vis:vis $try_name:ident, $type_name:ty) =3D> { + /// Read data from a give offset known at compile time. + /// + /// Bound checks are perfomed on compile time, hence if the offset is = not known at compile + /// time, the build will fail. + $(#[$attr])* + #[inline] + $vis fn $name(&self, offset: usize) -> $type_name { + build_assert!(offset_valid::<$type_name>(offset, SIZE)); + + // SAFETY: offset checked to be valid above. + unsafe { self.$name_unchecked(offset) } + } + + /// Read data from a given offset. + /// + /// Bound checks are performed on runtime, it fails if the offset (plu= s type size) is + /// out of bounds. + $(#[$attr])* + #[inline] + $try_vis fn $try_name(&self, offset: usize) -> Result<$type_name> { + if !(offset_valid::<$type_name>(offset, self.maxsize())) { + return Err(EINVAL); + } + + // SAFETY: offset checked to be valid above. + Ok(unsafe { self.$name_unchecked(offset) }) + } + }; + (@read $(#[$attr:meta])* $name_unchecked:ident, $name:ident, $try_name= :ident, $type_name:ty) =3D> { + /// Read data from a given offset without doing any bound checks. + /// The offset is relative to the base address of Self. + /// + /// # Safety + /// + /// The offset has to be valid for self. + $(#[$attr])* + unsafe fn $name_unchecked(&self, offset: usize) -> $type_name; + + define_io_access_function!(@read_derived $(#[$attr])* $name_unchecked,= $name, $try_name, $type_name); + }; + (@read $($(#[$attr:meta])* $name_unchecked:ident, $name:ident, $try_na= me:ident, $type_name:ty;)+) =3D> { + $( + define_io_access_function!(@read $(#[$attr])* $name_unchecked, $na= me, $try_name, $type_name); + )* + }; + (@write_derived $(#[$attr:meta])* $name_unchecked:ident, $vis:vis $nam= e:ident, $try_vis:vis $try_name:ident, $type_name:ty) =3D> { + /// Write data to a given offset known at compile time. + /// Bound checks are performed on compile time, hence if the offset is= not known at compile + /// time, the build will fail. + $(#[$attr])* + #[inline] + $vis fn $name(&self, value: $type_name, offset: usize) { + build_assert!(offset_valid::<$type_name>(offset, SIZE)); + + // SAFETY: offset checked to be valid above. + unsafe { self.$name_unchecked(value, offset) } + } + + /// Write data to a given offset. + /// + /// Bound checks are performed on runtime, it fails if the offset (plu= s the type size) is + /// out of bounds. + $(#[$attr])* + #[inline] + $try_vis fn $try_name(&self, value: $type_name, offset: usize) -> Resu= lt { + if !(offset_valid::<$type_name>(offset, self.maxsize())) { + return Err(EINVAL); + } + + // SAFETY: offset checked to be valid above. + Ok(unsafe { self.$name_unchecked(value, offset) }) + } + }; + (@write $(#[$attr:meta])* $name_unchecked:ident, $name:ident, $try_nam= e:ident, $type_name:ty) =3D> { + /// Write data to a given offset without doing any bound checks. + /// The offset is relative to the base address of self. + /// + /// # Safety + /// + /// The offset has to be valid for Self. + $(#[$attr])* + unsafe fn $name_unchecked(&self, value: $type_name, offset: usize); + + define_io_access_function!(@write_derived $(#[$attr])* $name_unchecked= , $name, $try_name, $type_name); + }; + (@write $($(#[$attr:meta])* $name_unchecked:ident, $name:ident, $try_n= ame:ident, $type_name:ty;)+) =3D> { + $( + define_io_access_function!(@write $(#[$attr])* $name_unchecked, $n= ame, $try_name, $type_name); + )* + }; +} + +/// Private macro to generate accessor functions that call the correct C f= unctions given as `fn_c`. +/// +/// This Takes either `@read` or `@write` to generate a single read or wri= te accessor function. +/// +/// This also can take a list of read write pairs to generate both at the = same time. +macro_rules! impl_accessor_fn { + (@read $(#[$attr:meta])* $vis:vis $fn_rust:ident, $fn_c:ident, $type_n= ame:ty) =3D> { + $(#[$attr])* + $vis unsafe fn $fn_rust(&self, offset: usize) -> $type_name { + // SAFETY: by the safety requirement of the function `self.addr() = + offset` is valid to read + // TODO: once MSRV is >=3D 1.79.0 replace `+` with `unchecked_add` + unsafe { bindings::$fn_c((self.addr() + offset) as _) as _ } + } + }; + (@write $(#[$attr:meta])* $vis:vis $fn_rust:ident, $fn_c:ident, $type_= name:ty) =3D> { + $(#[$attr])* + $vis unsafe fn $fn_rust(&self, value: $type_name, offset: usize) { + // SAFETY: + // by the safety requirement of the function `self.addr() + offset= ` is valid to write + // TODO: once MSRV is >=3D 1.79.0 replace `+` with `unchecked_add` + unsafe { bindings::$fn_c(value, (self.addr() + offset) as _) as _ } + } + }; + ( + $( + $(#[$attr:meta])* + $vis_read:vis $fn_rust_read:ident, $fn_c_read:ident, + $vis_write:vis $fn_rust_write:ident, $fn_c_write:ident, + $type_name:ty $(;)? + )+ + ) =3D> { + $( + impl_accessor_fn!(@read $(#[$attr])* $vis_read $fn_rust_read, $fn_= c_read, $type_name); + impl_accessor_fn!(@write $(#[$attr])* $vis_write $fn_rust_write, $= fn_c_write, $type_name); + )+ + }; +} + +/// Check if the offset is valid to still support the type U in the given = size +const fn offset_valid(offset: usize, size: usize) -> bool { + let type_size =3D core::mem::size_of::(); + if let Some(end) =3D offset.checked_add(type_size) { + end <=3D size && offset % type_size =3D=3D 0 + } else { + false + } +} + +/// Io Access functions. +/// +/// # Safety +/// +/// `SIZE` and `maxsize()` has to always be valid to add to the base addre= ss. +pub unsafe trait IoAccess { + /// Returns the maximum size of the accessed IO area. + fn maxsize(&self) -> usize; + + /// Returns the base address of the accessed IO area. + fn addr(&self) -> usize; + + define_io_access_function!(@read + read8_unchecked, read8, try_read8, u8; + read16_unchecked, read16, try_read16, u16; + read32_unchecked, read32, try_read32, u32; + ); + + define_io_access_function!(@write + write8_unchecked, write8, try_write8, u8; + write16_unchecked, write16, try_write16, u16; + write32_unchecked, write32, try_write32, u32; + ); +} + +/// Extending trait of [`IoAccess`] offering 64 bit functions. +#[cfg(CONFIG_64BIT)] +pub trait IoAccess64: IoAccess { + define_io_access_function!(@read read64_unchecked, read64, try_read64,= u64); + define_io_access_function!(@write write64_unchecked, write64, try_writ= e64, u64); +} + +/// Io Relaxed Access functions. +/// +/// Similar to [`IoAccess`] but using relaxed memory boundries. For [`Port= Io`] (when [`Io`] +/// is a PortIo address) this just calls the functions from [`IoAccess`]. +pub trait IoAccessRelaxed: IoAccess { + define_io_access_function!(@read + read8_relaxed_unchecked, read8_relaxed, try_read8_relaxed, u8; + read16_relaxed_unchecked, read16_relaxed, try_read16_relaxed, u16; + read32_relaxed_unchecked, read32_relaxed, try_read32_relaxed, u32; + ); + + define_io_access_function!(@write + write8_relaxed_unchecked, write8_relaxed, try_write8_relaxed, u8; + write16_relaxed_unchecked, write16_relaxed, try_write16_relaxed, u= 16; + write32_relaxed_unchecked, write32_relaxed, try_write32_relaxed, u= 32; + ); +} + +/// Extending trait of [`IoAccessRelaxed`] offering 64 bit functions. +#[cfg(CONFIG_64BIT)] +pub trait IoAccess64Relaxed: IoAccess { + define_io_access_function!(@read + read64_relaxed_unchecked, read64_relaxed, try_read64_relaxed, u64; + ); + + define_io_access_function!(@write + write64_relaxed_unchecked, write64_relaxed, try_write64_relaxed, u= 64; + ); +} + /// Raw representation of an MMIO region. /// /// By itself, the existence of an instance of this structure does not pro= vide any guarantees that @@ -43,218 +248,88 @@ pub fn maxsize(&self) -> usize { } } =20 -/// IO-mapped memory, starting at the base address @addr and spanning @max= len bytes. +/// IO-mapped memory, starting at the base address [`addr`] and spanning [= `maxsize`] bytes. /// /// The creator (usually a subsystem / bus such as PCI) is responsible for= creating the -/// mapping, performing an additional region request etc. -/// -/// # Invariant -/// -/// `addr` is the start and `maxsize` the length of valid I/O mapped memor= y region of size -/// `maxsize`. -/// -/// # Examples -/// -/// ```no_run -/// # use kernel::{bindings, io::{Io, IoRaw}}; -/// # use core::ops::Deref; +/// mapping, performing an additional region request, etc. /// -/// // See also [`pci::Bar`] for a real example. -/// struct IoMem(IoRaw); +/// # Invariants /// -/// impl IoMem { -/// /// # Safety -/// /// -/// /// [`paddr`, `paddr` + `SIZE`) must be a valid MMIO region that i= s mappable into the CPUs -/// /// virtual address space. -/// unsafe fn new(paddr: usize) -> Result{ -/// // SAFETY: By the safety requirements of this function [`paddr= `, `paddr` + `SIZE`) is -/// // valid for `ioremap`. -/// let addr =3D unsafe { bindings::ioremap(paddr as _, SIZE as _)= }; -/// if addr.is_null() { -/// return Err(ENOMEM); -/// } +/// [`addr`] is the start and [`maxsize`] the length of valid I/O mapped m= emory region of +/// size [`maxsize`]. /// -/// Ok(IoMem(IoRaw::new(addr as _, SIZE)?)) -/// } -/// } +/// [`addr`] is valid to access with the C [`read`]/[`write`] family of fu= nctions. /// -/// impl Drop for IoMem { -/// fn drop(&mut self) { -/// // SAFETY: `self.0.addr()` is guaranteed to be properly mapped= by `Self::new`. -/// unsafe { bindings::iounmap(self.0.addr() as _); }; -/// } -/// } -/// -/// impl Deref for IoMem { -/// type Target =3D Io; -/// -/// fn deref(&self) -> &Self::Target { -/// // SAFETY: The memory range stored in `self` has been properly= mapped in `Self::new`. -/// unsafe { Io::from_raw(&self.0) } -/// } -/// } -/// -///# fn no_run() -> Result<(), Error> { -/// // SAFETY: Invalid usage for example purposes. -/// let iomem =3D unsafe { IoMem::<{ core::mem::size_of::() }>::new(0= xBAAAAAAD)? }; -/// iomem.write32(0x42, 0x0); -/// assert!(iomem.try_write32(0x42, 0x0).is_ok()); -/// assert!(iomem.try_write32(0x42, 0x4).is_err()); -/// # Ok(()) -/// # } -/// ``` +/// [`addr`]: IoAccess::addr +/// [`maxsize`]: IoAccess::maxsize +/// [`read`]: https://docs.kernel.org/driver-api/device-io.html#difference= s-between-i-o-access-functions +/// [`write`]: https://docs.kernel.org/driver-api/device-io.html#differenc= es-between-i-o-access-functions #[repr(transparent)] -pub struct Io(IoRaw); - -macro_rules! define_read { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident -> $type_= name:ty) =3D> { - /// Read IO data from a given offset known at compile time. - /// - /// Bound checks are performed on compile time, hence if the offse= t is not known at compile - /// time, the build will fail. - $(#[$attr])* - #[inline] - pub fn $name(&self, offset: usize) -> $type_name { - let addr =3D self.io_addr_assert::<$type_name>(offset); - - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(addr as _) } - } - - /// Read IO data from a given offset. - /// - /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is - /// out of bounds. - $(#[$attr])* - pub fn $try_name(&self, offset: usize) -> Result<$type_name> { - let addr =3D self.io_addr::<$type_name>(offset)?; - - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - Ok(unsafe { bindings::$c_fn(addr as _) }) - } - }; -} - -macro_rules! define_write { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident <- $type_= name:ty) =3D> { - /// Write IO data from a given offset known at compile time. - /// - /// Bound checks are performed on compile time, hence if the offse= t is not known at compile - /// time, the build will fail. - $(#[$attr])* - #[inline] - pub fn $name(&self, value: $type_name, offset: usize) { - let addr =3D self.io_addr_assert::<$type_name>(offset); - - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(value, addr as _, ) } - } +pub struct MMIo(IoRaw); =20 - /// Write IO data from a given offset. - /// - /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is - /// out of bounds. - $(#[$attr])* - pub fn $try_name(&self, value: $type_name, offset: usize) -> Resul= t { - let addr =3D self.io_addr::<$type_name>(offset)?; - - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(value, addr as _) } - Ok(()) - } - }; -} - -impl Io { - /// Converts an `IoRaw` into an `Io` instance, providing the accessors= to the MMIO mapping. +impl MMIo { + /// Convert a [`IoRaw`] into an [`MMIo`] instance, providing the acces= sors to the MMIO mapping. /// /// # Safety /// - /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size - /// `maxsize`. - pub unsafe fn from_raw(raw: &IoRaw) -> &Self { - // SAFETY: `Io` is a transparent wrapper around `IoRaw`. - unsafe { &*core::ptr::from_ref(raw).cast() } - } - - /// Returns the base address of this mapping. + /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of + /// size `maxsize`. #[inline] - pub fn addr(&self) -> usize { - self.0.addr() - } - - /// Returns the maximum size of this mapping. - #[inline] - pub fn maxsize(&self) -> usize { - self.0.maxsize() + pub unsafe fn from_raw(raw: IoRaw) -> Self { + Self(raw) } =20 + /// Convert a ref to [`IoRaw`] into an [`MMIo`] instance, providing th= e accessors to the + /// MMIo mapping. + /// + /// # Safety + /// + /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of + /// size `maxsize`. #[inline] - const fn offset_valid(offset: usize, size: usize) -> bool { - let type_size =3D core::mem::size_of::(); - if let Some(end) =3D offset.checked_add(type_size) { - end <=3D size && offset % type_size =3D=3D 0 - } else { - false - } + pub unsafe fn from_raw_ref(raw: &IoRaw) -> &Self { + // SAFETY: `MMIo` is a transparent wrapper around `IoRaw`. + unsafe { &*core::ptr::from_ref(raw).cast() } } +} =20 +// SAFETY: as per invariant `raw` is valid +unsafe impl IoAccess for MMIo { #[inline] - fn io_addr(&self, offset: usize) -> Result { - if !Self::offset_valid::(offset, self.maxsize()) { - return Err(EINVAL); - } - - // Probably no need to check, since the safety requirements of `Se= lf::new` guarantee that - // this can't overflow. - self.addr().checked_add(offset).ok_or(EINVAL) + fn maxsize(&self) -> usize { + self.0.maxsize() } =20 #[inline] - fn io_addr_assert(&self, offset: usize) -> usize { - build_assert!(Self::offset_valid::(offset, SIZE)); - - self.addr() + offset + fn addr(&self) -> usize { + self.0.addr() } =20 - define_read!(read8, try_read8, readb -> u8); - define_read!(read16, try_read16, readw -> u16); - define_read!(read32, try_read32, readl -> u32); - define_read!( - #[cfg(CONFIG_64BIT)] - read64, - try_read64, - readq -> u64 + impl_accessor_fn!( + read8_unchecked, readb, write8_unchecked, writeb, u8; + read16_unchecked, readw, write16_unchecked, writew, u16; + read32_unchecked, readl, write32_unchecked, writel, u32; ); +} =20 - define_read!(read8_relaxed, try_read8_relaxed, readb_relaxed -> u8); - define_read!(read16_relaxed, try_read16_relaxed, readw_relaxed -> u16); - define_read!(read32_relaxed, try_read32_relaxed, readl_relaxed -> u32); - define_read!( - #[cfg(CONFIG_64BIT)] - read64_relaxed, - try_read64_relaxed, - readq_relaxed -> u64 +#[cfg(CONFIG_64BIT)] +impl IoAccess64 for MMIo { + impl_accessor_fn!( + read64_unchecked, readq, write64_unchecked, writeq, u64; ); +} =20 - define_write!(write8, try_write8, writeb <- u8); - define_write!(write16, try_write16, writew <- u16); - define_write!(write32, try_write32, writel <- u32); - define_write!( - #[cfg(CONFIG_64BIT)] - write64, - try_write64, - writeq <- u64 +impl IoAccessRelaxed for MMIo { + impl_accessor_fn!( + read8_relaxed_unchecked, readb_relaxed, write8_relaxed_unchecked, = writeb_relaxed, u8; + read16_relaxed_unchecked, readw_relaxed, write16_relaxed_unchecked= , writew_relaxed, u16; + read32_relaxed_unchecked, readl_relaxed, write32_relaxed_unchecked= , writel_relaxed, u32; ); +} =20 - define_write!(write8_relaxed, try_write8_relaxed, writeb_relaxed <- u8= ); - define_write!(write16_relaxed, try_write16_relaxed, writew_relaxed <- = u16); - define_write!(write32_relaxed, try_write32_relaxed, writel_relaxed <- = u32); - define_write!( - #[cfg(CONFIG_64BIT)] - write64_relaxed, - try_write64_relaxed, - writeq_relaxed <- u64 +#[cfg(CONFIG_64BIT)] +impl IoAccess64Relaxed for MMIo { + impl_accessor_fn!( + read64_relaxed_unchecked, readq_relaxed, write64_relaxed_unchecked= , writeq_relaxed, u64; ); } --=20 2.49.0 From nobody Sun Feb 8 07:58:51 2026 Received: from mail-oi1-f179.google.com (mail-oi1-f179.google.com [209.85.167.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0111E23F41A; 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[73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 006d021491bc7-60842b096desm303745eaf.30.2025.05.08.20.16.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 20:16:25 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, akpm@linux-foundation.org, ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, tmgross@umich.edu, gregkh@linuxfoundation.org, rafael@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, raag.jadav@intel.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, me@kloenk.dev, andrewjballance@gmail.com, fujita.tomonori@gmail.com, daniel.almeida@collabora.com Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 03/11] rust: io: implement Debug for IoRaw and add some doctests Date: Thu, 8 May 2025 22:15:16 -0500 Message-ID: <20250509031524.2604087-4-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fiona Behrens Implement `Debug` for `kernel::io::IoRaw` which also outputs the const generic SIZE as a field. Add some doctests to `IoRaw::new` and `MMIo::from_raw(_ref)`. Signed-off-by: Fiona Behrens Signed-off-by: Andrew Ballance --- rust/kernel/io.rs | 62 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 19bbf802027c..09440dd3e73b 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -227,6 +227,33 @@ pub struct IoRaw { =20 impl IoRaw { /// Returns a new `IoRaw` instance on success, an error otherwise. + /// + /// # Examples + /// + /// Const generic size 0, only allowing runtime checks: + /// ``` + /// use kernel::io::IoRaw; + /// + /// let raw: IoRaw<0> =3D IoRaw::new(0xDEADBEEFC0DE, 8).unwrap(); + /// # assert_eq!(raw.addr(), 0xDEADBEEFC0DE); + /// # assert_eq!(raw.maxsize(), 8); + /// ``` + /// + /// Const generic size equals maxsize: + /// ``` + /// use kernel::io::IoRaw; + /// + /// let raw: IoRaw<8> =3D IoRaw::new(0xDEADBEEFC0DE, 8).unwrap(); + /// # assert_eq!(raw.addr(), 0xDEADBEEFC0DE); + /// # assert_eq!(raw.maxsize(), 8); + /// ``` + /// + /// Const generic size bigger then maxsize: + /// ``` + /// use kernel::io::IoRaw; + /// + /// IoRaw::<16>::new(0xDEADBEEFC0DE, 8).unwrap_err(); + /// ``` pub fn new(addr: usize, maxsize: usize) -> Result { if maxsize < SIZE { return Err(EINVAL); @@ -248,6 +275,16 @@ pub fn maxsize(&self) -> usize { } } =20 +impl core::fmt::Debug for IoRaw { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + f.debug_struct("IoRaw") + .field("SIZE", &SIZE) + .field("addr", &self.addr) + .field("maxsize", &self.maxsize) + .finish() + } +} + /// IO-mapped memory, starting at the base address [`addr`] and spanning [= `maxsize`] bytes. /// /// The creator (usually a subsystem / bus such as PCI) is responsible for= creating the @@ -264,6 +301,7 @@ pub fn maxsize(&self) -> usize { /// [`maxsize`]: IoAccess::maxsize /// [`read`]: https://docs.kernel.org/driver-api/device-io.html#difference= s-between-i-o-access-functions /// [`write`]: https://docs.kernel.org/driver-api/device-io.html#differenc= es-between-i-o-access-functions +#[derive(Debug)] #[repr(transparent)] pub struct MMIo(IoRaw); =20 @@ -274,6 +312,18 @@ impl MMIo { /// /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of /// size `maxsize`. + /// + /// # Examples + /// + /// ``` + /// use kernel::io::{IoRaw, MMIo, IoAccess}; + /// + /// let raw =3D IoRaw::<2>::new(0xDEADBEEFC0DE, 2).unwrap(); + /// // SAFETY: test, value is not actually written to. + /// let mmio: MMIo<2> =3D unsafe { MMIo::from_raw(raw) }; + /// # assert_eq!(0xDEADBEEFC0DE, mmio.addr()); + /// # assert_eq!(2, mmio.maxsize()); + /// ``` #[inline] pub unsafe fn from_raw(raw: IoRaw) -> Self { Self(raw) @@ -286,6 +336,18 @@ pub unsafe fn from_raw(raw: IoRaw) -> Self { /// /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of /// size `maxsize`. + /// + /// # Examples + /// + /// ``` + /// use kernel::io::{IoRaw, MMIo, IoAccess}; + /// + /// let raw =3D IoRaw::<2>::new(0xDEADBEEFC0DE, 2).unwrap(); + /// // SAFETY: test, value is not actually written to. + /// let mmio: &MMIo<2> =3D unsafe { MMIo::from_raw_ref(&raw) }; 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[73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 006d021491bc7-60842b096desm303745eaf.30.2025.05.08.20.16.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 20:16:31 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, akpm@linux-foundation.org, ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, tmgross@umich.edu, gregkh@linuxfoundation.org, rafael@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, raag.jadav@intel.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, me@kloenk.dev, andrewjballance@gmail.com, fujita.tomonori@gmail.com, daniel.almeida@collabora.com Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 04/11] rust: io: add PortIo Date: Thu, 8 May 2025 22:15:17 -0500 Message-ID: <20250509031524.2604087-5-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fiona Behrens Add `rust::io::PortIo` implementing the `IoAccess` trait. Signed-off-by: Fiona Behrens Signed-off-by: Andrew Ballance --- rust/helpers/io.c | 20 +++++++++++ rust/kernel/io.rs | 88 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+) diff --git a/rust/helpers/io.c b/rust/helpers/io.c index 525af02f209e..d439b61c672e 100644 --- a/rust/helpers/io.c +++ b/rust/helpers/io.c @@ -51,3 +51,23 @@ define_rust_mmio_write_helper(writel_relaxed, u32); #ifdef CONFIG_64BIT define_rust_mmio_write_helper(writeq_relaxed, u64); #endif + +#define define_rust_pio_read_helper(name, type) \ + type rust_helper_##name(unsigned long port) \ + { \ + return name(port); \ + } + +#define define_rust_pio_write_helper(name, type) \ + void rust_helper_##name(type value, unsigned long port) \ + { \ + name(value, port); \ + } + +define_rust_pio_read_helper(inb, u8); +define_rust_pio_read_helper(inw, u16); +define_rust_pio_read_helper(inl, u32); + +define_rust_pio_write_helper(outb, u8); +define_rust_pio_write_helper(outw, u16); +define_rust_pio_write_helper(outl, u32); diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 09440dd3e73b..70621a016a87 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -395,3 +395,91 @@ impl IoAccess64Relaxed for MM= Io { read64_relaxed_unchecked, readq_relaxed, write64_relaxed_unchecked= , writeq_relaxed, u64; ); } + +/// Port-IO, starting at the base address [`addr`] and spanning [`maxsize`= ] bytes. +/// +/// The creator is responsible for performing an additional region request= , etc. +/// +/// # Invariants +/// +/// [`addr`] is the start and [`maxsize`] the length of a valid port io re= gion of size [`maxsize`]. +/// +/// [`addr`] is valid to access with the C [`in`]/[`out`] family of functi= ons. +/// +/// [`addr`]: IoAccess::addr +/// [`maxsize`]: IoAccess::maxsize +/// [`in`]: https://docs.kernel.org/driver-api/device-io.html#differences-= between-i-o-access-functions +/// [`out`]: https://docs.kernel.org/driver-api/device-io.html#differences= -between-i-o-access-functions +#[derive(Debug)] +#[repr(transparent)] +pub struct PortIo(IoRaw); + +impl PortIo { + /// Convert a [`IoRaw`] into an [`PortIo`] instance, providing the acc= essors to the + /// PortIo mapping. + /// + /// # Safety + /// + /// Callers must ensure that `addr` is the start of a valid Port I/O r= egion of size `maxsize`. + /// + /// # Examples + /// + /// ``` + /// use kernel::io::{IoRaw, PortIo, IoAccess}; + /// + /// let raw =3D IoRaw::<2>::new(0xDEADBEEFC0DE, 2).unwrap(); + /// // SAFETY: test, value is not actually written to. + /// let pio: PortIo<2> =3D unsafe { PortIo::from_raw(raw) }; + /// # assert_eq!(0xDEADBEEFC0DE, pio.addr()); + /// # assert_eq!(2, pio.maxsize()); + /// ``` + #[inline] + pub unsafe fn from_raw(raw: IoRaw) -> Self { + Self(raw) + } + + /// Convert a ref to [`IoRaw`] into an [`PortIo`] instance, providing = the accessors to + /// the PortIo mapping. + /// + /// # Safety + /// + /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of + /// size `maxsize`. + /// + /// # Examples + /// + /// ``` + /// use kernel::io::{IoRaw, PortIo, IoAccess}; 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[73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 006d021491bc7-60842b096desm303745eaf.30.2025.05.08.20.16.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 20:16:38 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, akpm@linux-foundation.org, ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, tmgross@umich.edu, gregkh@linuxfoundation.org, rafael@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, raag.jadav@intel.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, me@kloenk.dev, andrewjballance@gmail.com, fujita.tomonori@gmail.com, daniel.almeida@collabora.com Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 05/11] rust: io: add new Io type Date: Thu, 8 May 2025 22:15:18 -0500 Message-ID: <20250509031524.2604087-6-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" adds a new Io type that uses the C ioread/iowrite family of functions and implements the IoAccess trait for it. Signed-off-by: Andrew Ballance --- rust/helpers/io.c | 8 +++++ rust/kernel/io.rs | 86 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+) diff --git a/rust/helpers/io.c b/rust/helpers/io.c index d439b61c672e..11c0c34f2eba 100644 --- a/rust/helpers/io.c +++ b/rust/helpers/io.c @@ -71,3 +71,11 @@ define_rust_pio_read_helper(inl, u32); define_rust_pio_write_helper(outb, u8); define_rust_pio_write_helper(outw, u16); define_rust_pio_write_helper(outl, u32); + +define_rust_mmio_read_helper(ioread8, u8); +define_rust_mmio_read_helper(ioread16, u16); +define_rust_mmio_read_helper(ioread32, u32); + +define_rust_mmio_write_helper(iowrite8, u8); +define_rust_mmio_write_helper(iowrite16, u16); +define_rust_mmio_write_helper(iowrite32, u32); diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 70621a016a87..3d8b6e731ce7 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -483,3 +483,89 @@ fn addr(&self) -> usize { read32_unchecked, inl, write32_unchecked, outl, u32; ); } + +/// Io that can be either PortIo or MMIo, +/// starting at the base address [`addr`] and spanning [`maxsize`] bytes. +/// +/// The creator (usually a subsystem / bus such as PCI) is responsible for= creating the +/// mapping, performing an additional region request, etc. +/// +/// # Invariants +/// +/// [`addr`] is the start and [`maxsize`] the length of a valid io region = of size [`maxsize`]. +/// +/// [`addr`] is valid to access with the C [`ioread`]/[`iowrite`] family o= f functions. +/// +/// [`addr`]: IoAccess::addr +/// [`maxsize`]: IoAccess::maxsize +/// [`ioread`]: https://docs.kernel.org/driver-api/device-io.html#differen= ces-between-i-o-access-functions +/// [`iowrite`]: https://docs.kernel.org/driver-api/device-io.html#differe= nces-between-i-o-access-functions +#[derive(Debug)] +#[repr(transparent)] +pub struct Io(IoRaw); + +impl Io { + /// Convert a [`IoRaw`] into an [`Io`] instance, providing the accesso= rs to the + /// Io mapping. + /// + /// # Safety + /// + /// Callers must ensure that `addr` is the start of a valid I/O region= of size `maxsize`. + /// + /// ``` + /// use kernel::io::{IoRaw, Io, IoAccess}; + /// + /// let raw =3D IoRaw::<2>::new(0xDEADBEEFC0DE, 2).unwrap(); + /// // SAFETY: test, value is not actually written to. + /// let io: Io<2> =3D unsafe { Io::from_raw(raw) }; + /// # assert_eq!(0xDEADBEEFC0DE, io.addr()); + /// # assert_eq!(2, io.maxsize()); + /// ``` + pub unsafe fn from_raw(raw: IoRaw) -> Self { + Self(raw) + } + + /// Convert a ref to [`IoRaw`] into an [`Io`] instance, providing the = accessors to + /// the Io mapping. + /// + /// # Safety + /// + /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of + /// size `maxsize`. + /// + /// # Examples + /// + /// ``` + /// use kernel::io::{IoRaw, Io, IoAccess}; + /// + /// let raw =3D IoRaw::<2>::new(0xDEADBEEFC0DE, 2).unwrap(); + /// // SAFETY: test, value is not actually written to. + /// let io: &Io<2> =3D unsafe { Io::from_raw_ref(&raw) }; + /// # assert_eq!(raw.addr(), io.addr()); + /// # assert_eq!(raw.maxsize(), io.maxsize()); + /// ``` + #[inline] + pub unsafe fn from_raw_ref(raw: &IoRaw) -> &Self { + // SAFETY: `Io` is a transparent wrapper around `IoRaw`. + unsafe { &*core::ptr::from_ref(raw).cast() } + } +} + +// SAFETY: as per invariant `raw` is valid +unsafe impl IoAccess for Io { + #[inline] + fn addr(&self) -> usize { + self.0.addr() + } + + #[inline] + fn maxsize(&self) -> usize { + self.0.maxsize() + } + + impl_accessor_fn!( + read8_unchecked, ioread8, write8_unchecked, iowrite8, u8; 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[73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 006d021491bc7-60842b096desm303745eaf.30.2025.05.08.20.16.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 20:16:43 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, akpm@linux-foundation.org, ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, tmgross@umich.edu, gregkh@linuxfoundation.org, rafael@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, raag.jadav@intel.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, me@kloenk.dev, andrewjballance@gmail.com, fujita.tomonori@gmail.com, daniel.almeida@collabora.com Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 06/11] io: move PIO_OFFSET to linux/io.h Date: Thu, 8 May 2025 22:15:19 -0500 Message-ID: <20250509031524.2604087-7-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fiona Behrens Move the non arch specific PIO size to linux/io.h. This allows rust to access `PIO_OFFSET`, `PIO_MASK` and `PIO_RESERVED`. This is required to implement `IO_COND` in rust. Signed-off-by: Fiona Behrens Signed-off-by: Andrew Ballance --- include/linux/io.h | 13 +++++++++++++ lib/iomap.c | 13 ------------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/include/linux/io.h b/include/linux/io.h index 6a6bc4d46d0a..df032061544a 100644 --- a/include/linux/io.h +++ b/include/linux/io.h @@ -12,6 +12,19 @@ #include #include =20 +#ifndef HAVE_ARCH_PIO_SIZE +/* + * We encode the physical PIO addresses (0-0xffff) into the + * pointer by offsetting them with a constant (0x10000) and + * assuming that all the low addresses are always PIO. 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[73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 006d021491bc7-60842b096desm303745eaf.30.2025.05.08.20.16.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 20:16:48 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, akpm@linux-foundation.org, ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, tmgross@umich.edu, gregkh@linuxfoundation.org, rafael@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, raag.jadav@intel.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, me@kloenk.dev, andrewjballance@gmail.com, fujita.tomonori@gmail.com, daniel.almeida@collabora.com Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 07/11] rust: io: add from_raw_cookie functions Date: Thu, 8 May 2025 22:15:20 -0500 Message-ID: <20250509031524.2604087-8-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" adds a `from_raw_cookie` function to the IoAccess trait. `from_raw_cookie` attempts to convert a iomem address that can be accessed by the ioread/iowrite family of C functions into either a `Io`, `PortIo` or `MMIo`. This is done so that devices that know what type of Io they are at compile time can give a hint about their type. Suggested-by: Danilo Krummrich Signed-off-by: Andrew Ballance --- rust/kernel/io.rs | 104 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 3d8b6e731ce7..30892f2909a6 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -6,6 +6,62 @@ =20 use crate::error::{code::EINVAL, Result}; use crate::{bindings, build_assert}; +use io_backend::*; + +/// `io_backend` is private and implements the config specific logic for +/// `IoAccess::from_raw_cookie`. +#[cfg(CONFIG_GENERIC_IOMAP)] +mod io_backend { + // if generic_iomap is enabled copy the logic from IO_COND in `lib/iom= ap.c` + + #[inline] + pub(super) fn is_mmio(addr: usize) -> bool { + addr >=3D bindings::PIO_RESERVED as usize + } + + #[inline] + pub(super) fn is_portio(addr: usize) -> bool { + !is_mmio(addr) && addr > bindings::PIO_OFFSET as usize + } + + #[inline] + pub(super) fn cookie_to_pio(addr: usize) -> usize { + addr & bindings::PIO_MASK as usize + } + + #[inline] + pub(super) fn cookie_to_mmio(cookie: usize) -> usize { + cookie + } +} +#[cfg(not(CONFIG_GENERIC_IOMAP))] +mod io_backend { + // for everyone who does not use generic iomap + // except for alpha and parisc, neither of which has a rust compiler, + // ioread/iowrite is defined in `include/asm-generic/io.h`. + // + // for these ioread/iowrite, maps to read/write. + // so allow any io to be converted because they use the same backend + #[inline] + pub(super) fn is_mmio(_addr: usize) -> bool { + true + } + + #[inline] + pub(super) fn is_portio(_addr: usize) -> bool { + false + } + + #[inline] + pub(super) fn cookie_to_pio(cookie: usize) -> usize { + cookie + } + + #[inline] + pub(super) fn cookie_to_mmio(cookie: usize) -> usize { + cookie + } +} =20 /// Private macro to define the [`IoAccess`] functions. macro_rules! define_io_access_function { @@ -160,8 +216,18 @@ pub unsafe trait IoAccess { fn maxsize(&self) -> usize; =20 /// Returns the base address of the accessed IO area. + /// if `self` was created by ['from_raw_cookie'], `addr` might not be = equal to the original + /// address. fn addr(&self) -> usize; =20 + /// Attempts to create a `Self` from a [`IoRaw`]. + /// + /// # Safety + /// `raw` should be a io cookie that can be accessed by the C `ioread`= /`iowrite` functions + unsafe fn from_raw_cookie(raw: IoRaw) -> Result + where + Self: Sized; + define_io_access_function!(@read read8_unchecked, read8, try_read8, u8; read16_unchecked, read16, try_read16, u16; @@ -367,6 +433,19 @@ fn addr(&self) -> usize { self.0.addr() } =20 + unsafe fn from_raw_cookie(mut raw: IoRaw) -> Result + where + Self: Sized, + { + if is_mmio(raw.addr()) { + // INVARIANT: `addr` is decoded so it should be ok to access w= ith read/write + raw.addr =3D cookie_to_mmio(raw.addr()); + Ok(Self(raw)) + } else { + Err(EINVAL) + } + } + impl_accessor_fn!( read8_unchecked, readb, write8_unchecked, writeb, u8; read16_unchecked, readw, write16_unchecked, writew, u16; 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[73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 006d021491bc7-60842b096desm303745eaf.30.2025.05.08.20.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 20:16:55 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, akpm@linux-foundation.org, ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, tmgross@umich.edu, gregkh@linuxfoundation.org, rafael@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, raag.jadav@intel.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, me@kloenk.dev, andrewjballance@gmail.com, fujita.tomonori@gmail.com, daniel.almeida@collabora.com Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 08/11] rust: pci: make Bar generic over Io Date: Thu, 8 May 2025 22:15:21 -0500 Message-ID: <20250509031524.2604087-9-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" renames `Bar` to `RawBar` and makes it generic over `IoAccess`. a user can give a compile time suggestion when mapping a bar so that the type of io can be known. Suggested-by: Danilo Krummrich Signed-off-by: Andrew Ballance --- rust/kernel/pci.rs | 88 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 69 insertions(+), 19 deletions(-) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index c97d6d470b28..7e592db99073 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -11,8 +11,7 @@ devres::Devres, driver, error::{to_result, Result}, - io::Io, - io::IoRaw, + io::{Io, IoAccess, IoRaw, MMIo, PortIo}, str::CStr, types::{ARef, ForeignOwnable, Opaque}, ThisModule, @@ -259,15 +258,25 @@ pub struct Device( /// /// # Invariants /// -/// `Bar` always holds an `IoRaw` inststance that holds a valid pointer to= the start of the I/O +/// `Bar` always holds an `I` inststance that holds a valid pointer to the= start of the I/O /// memory mapped PCI bar and its size. -pub struct Bar { +pub struct RawBar =3D Io>= { pdev: ARef, - io: IoRaw, + original_ioptr: usize, + io: I, num: i32, } =20 -impl Bar { +/// a pci bar that can be either PortIo or MMIo +pub type IoBar =3D RawBar>; + +/// a pci bar that maps a [`PortIo`]. +pub type MMIoBar =3D RawBar>; + +/// a pci bar that maps a [`MMIo`]. +pub type PIoBar =3D RawBar>; + +impl> RawBar { fn new(pdev: &Device, num: u32, name: &CStr) -> Result { let len =3D pdev.resource_len(num)?; if len =3D=3D 0 { @@ -299,7 +308,22 @@ fn new(pdev: &Device, num: u32, name: &CStr) -> Result= { return Err(ENOMEM); } =20 - let io =3D match IoRaw::new(ioptr, len as usize) { + let raw =3D match IoRaw::new(ioptr, len as usize) { + Ok(io) =3D> io, + Err(err) =3D> { + // SAFETY: + // `pdev` is valid by the invariants of `Device`. + // `ioptr` is guaranteed to be the start of a valid I/O ma= pped memory region. + // `num` is checked for validity by a previous call to `De= vice::resource_len`. + unsafe { Self::do_release(pdev, ioptr, num) }; + return Err(err); + } + }; + + // SAFETY: + // - `raw` is from `pci_iomap` + // - addresses from `pci_iomap` should be accesed through ioread/i= owrite + let io =3D match unsafe { I::from_raw_cookie(raw) } { Ok(io) =3D> io, Err(err) =3D> { // SAFETY: @@ -311,8 +335,9 @@ fn new(pdev: &Device, num: u32, name: &CStr) -> Result<= Self> { } }; =20 - Ok(Bar { + Ok(RawBar { pdev: pdev.into(), + original_ioptr: ioptr, io, num, }) @@ -334,29 +359,28 @@ unsafe fn do_release(pdev: &Device, ioptr: usize, num= : i32) { =20 fn release(&self) { // SAFETY: The safety requirements are guaranteed by the type inva= riant of `self.pdev`. - unsafe { Self::do_release(&self.pdev, self.io.addr(), self.num) }; + unsafe { Self::do_release(&self.pdev, self.original_ioptr, self.nu= m) }; } } =20 -impl Bar { +impl RawBar { fn index_is_valid(index: u32) -> bool { // A `struct pci_dev` owns an array of resources with at most `PCI= _NUM_RESOURCES` entries. index < bindings::PCI_NUM_RESOURCES } } =20 -impl Drop for Bar { +impl> Drop for RawBar { fn drop(&mut self) { self.release(); } } =20 -impl Deref for Bar { - type Target =3D Io; +impl> Deref for RawBar { + type Target =3D I; =20 fn deref(&self) -> &Self::Target { - // SAFETY: By the type invariant of `Self`, the MMIO range in `sel= f.io` is properly mapped. - unsafe { Io::from_raw(&self.io) } + &self.io } } =20 @@ -379,7 +403,7 @@ pub fn device_id(&self) -> u16 { =20 /// Returns the size of the given PCI bar resource. pub fn resource_len(&self, bar: u32) -> Result { - if !Bar::index_is_valid(bar) { + if !RawBar::index_is_valid(bar) { return Err(EINVAL); } =20 @@ -395,17 +419,43 @@ pub fn iomap_region_sized( &self, bar: u32, name: &CStr, - ) -> Result>> { - let bar =3D Bar::::new(self, bar, name)?; + ) -> Result>> { + let bar =3D RawBar::::new(self, bar, name)?; let devres =3D Devres::new(self.as_ref(), bar, GFP_KERNEL)?; =20 Ok(devres) } =20 /// Mapps an entire PCI-BAR after performing a region-request on it. - pub fn iomap_region(&self, bar: u32, name: &CStr) -> Result> { + pub fn iomap_region(&self, bar: u32, name: &CStr) -> Result> { self.iomap_region_sized::<0>(bar, name) } + + /// Maps an entire PCI-BAR after performing a region-request` where the + /// type of Io backend is known at compile time. + pub fn iomap_region_hint( + &self, + bar: u32, + name: &CStr, + ) -> Result>> { + let bar =3D RawBar::<0, I>::new(self, bar, name)?; + let devres =3D Devres::new(self.as_ref(), bar, GFP_KERNEL)?; + + Ok(devres) + } + /// Maps an entire PCI-BAR after performing a region-request` where the + /// type of Io backend is known at compile time. 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[73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 006d021491bc7-60842b096desm303745eaf.30.2025.05.08.20.16.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 20:17:00 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, akpm@linux-foundation.org, ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, tmgross@umich.edu, gregkh@linuxfoundation.org, rafael@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, raag.jadav@intel.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, me@kloenk.dev, andrewjballance@gmail.com, fujita.tomonori@gmail.com, daniel.almeida@collabora.com Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 09/11] samples: rust: rust_driver_pci: update to use new bar and io api Date: Thu, 8 May 2025 22:15:22 -0500 Message-ID: <20250509031524.2604087-10-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" update rust_driver_pci.rs to use the new bar and io api. Signed-off-by: Andrew Ballance --- samples/rust/rust_driver_pci.rs | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/samples/rust/rust_driver_pci.rs b/samples/rust/rust_driver_pci= .rs index 2bb260aebc9e..b645155142db 100644 --- a/samples/rust/rust_driver_pci.rs +++ b/samples/rust/rust_driver_pci.rs @@ -4,7 +4,9 @@ //! //! To make this driver probe, QEMU must be run with `-device pci-testdev`. =20 -use kernel::{bindings, c_str, device::Core, devres::Devres, pci, prelude::= *, types::ARef}; +use kernel::{ + bindings, c_str, device::Core, devres::Devres, io::IoAccess, pci, prel= ude::*, types::ARef, +}; =20 struct Regs; =20 @@ -16,7 +18,7 @@ impl Regs { const END: usize =3D 0x10; } =20 -type Bar0 =3D pci::Bar<{ Regs::END }>; +type Bar0 =3D pci::IoBar<{ Regs::END }>; =20 #[derive(Debug)] struct TestIndex(u8); --=20 2.49.0 From nobody Sun Feb 8 07:58:51 2026 Received: from mail-oi1-f176.google.com (mail-oi1-f176.google.com [209.85.167.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C04D624167A; Fri, 9 May 2025 03:17:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746760628; cv=none; b=O3i6551TGfgzxoJ6NHgZ0WutntJOlUG6iElM/GXxtMj8mUHKt/gsdmhXY/37fxIhJdarw5zeJoxC5MwtiRxHqzlU8H0nll3lBpwTteIhCqv7D12VjloW8GdxWpX3QUnkKCYIibvuXvQU9AleFvCopQncnyPM/q9HcQhoa/x/lP0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746760628; c=relaxed/simple; bh=trFt74+3gg1ftMy1tXtRkrm0JO0Uv1lk6B3Xa/KkMHg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dJQuBYQ3TWkJnzuUjBW+ebWsnYS/VrBXZxTTJXgFFCHDFV8+VWPrENveAk4xZhSlvD6nCcFNma6C6gBgoYTiN74a4bJJrggsINTIH7+0wOX9UmwJ9zNhBdHM3xZyZDoZ3HLF7lMw1kB4xjyYxieshnoaHAnueKtAOtUm+rJF3Pk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ajoUsxrP; arc=none smtp.client-ip=209.85.167.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ajoUsxrP" Received: by mail-oi1-f176.google.com with SMTP id 5614622812f47-401be80368fso600625b6e.1; Thu, 08 May 2025 20:17:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1746760626; x=1747365426; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XgqV+bJH9bwGqYSCW6zT8FRineTcAn4X+KFdTGVLZEw=; b=ajoUsxrPkbTVpPW6SvsFDAaauwxtPTvK0czWs0F5C9IRsZSgiFpJmkCQWsRHUKW4Qp PfRo/C7EQy80II2SL76om6sB1zanVsiXg7UP+zRdU/4EnMABu9mc162b4+I5e3y/zMQr ttQ/HBIFIOJzfqsNQT+Zn/NF/1FzP+tK9MJ2R7g0UQrM3k8tcQ2SBqJo/t4iRUq/W6zs UlOQDBeevigFtInDgnyKutvkLP9v6PxxC5lnlF0U/Jahkw+YBAd0Tmi0EAVCqWzm2PCe dWKQMDkOqDDB177EY46TympruALonMxWAszDye+24wlFU4I6jM6YioN4qXNtcGt80DE1 MeYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746760626; x=1747365426; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XgqV+bJH9bwGqYSCW6zT8FRineTcAn4X+KFdTGVLZEw=; b=hm19ImUapJWyqV/zCF7tcGAB3kKxxaXduzx2Fva1vTskALf4a+S6QCRZOTXIjx+jNo Y9uF2PyOt2ii+Tls2GObIwySBK3EmsdIpThAZYXTAdd4sXD+u5IaDT0fjfwkSOoR4ArN N+jgXZ0oY+f+2yf7aRw0yzPkOujppxqUwNNZk/uu/SUli6RBpanyXB15b0WbNOrDQnNZ BXR9OTOdoO01+6WQBD8ipeZh/8n7IpxpW8xtHLm5ZnWu1tlwhX9b/JRnFUi6jc+R+sxr J32/Up7PkxohfVF5NZM8UniWNX3G8L5vIfLfIWsIkGNpJUBxn18ARgteEraPvDHe7rnO yU5w== X-Forwarded-Encrypted: i=1; AJvYcCUB2Ux10eEHG6q829AH8gy+PqpkFJDNsCnPfj72Rbi9kuZaC3SxVJBrJBbmcVpDDdrgb8mRta99z9DQY14mBZ4=@vger.kernel.org, AJvYcCUPD4w3QDHYPl7iZ0oOoChDb5HIpBRLoTdzYysjn6BERXHMIuGUQ8I/AznwcJeLRQLB7pIXptUkSaZkz5M=@vger.kernel.org, AJvYcCUbHT6wn3vLZ7QvnAIqdEdBl3sjhoUbxytF/vRvhuW3PySB/i2aB4nxRbFXUTdUm/82NwUzvGHFxv9B@vger.kernel.org X-Gm-Message-State: AOJu0YzpifjSbB4cUv23ha8IXe5jYZZEY6oHCZ7CDUsj12mFr019/po2 vUKaCs/pclu/O91+D9tT35GhU2JUNZ1QOKdX9WZPs2Oy82bWUJNc X-Gm-Gg: ASbGncs6izQdCxo+hcnV2xZNaQ+1fEcJZVx5R3kjo9FwLIx9UjFqBkBrRH+SGJbXI90 F7W4LQ1xsQ00Y306qtLyM+Kq32TJZhKhZgl3TYxt10Dt94DWb+PTLB1woVLZLH8eLlXipH18pGI DrksnBxIhZPwmtXWq0NvOefXysWcky664Cj4VHrWRITSrHOwxgzoP1hYixXYxNubszEggbnFbXk t4OnSrQ3/ef1MMb3rWvq11dehgkvxDYRYeJGXfNbGTX5cjpjjNMnEKH35WskTYIODN4HGGI0myi U+A1/UtuF+j5dcZvRMNl82B0qdFFxjXdJc3D1umOUSAtYcUEmIPs6VD25fei/G1DTFBFZWeH+el V8v3gD+xwnyqP X-Google-Smtp-Source: AGHT+IFW81DiF+olMWJMKxd0X0Haiy6R6/35pkLPuRc9ZALbjLeamffaAjN2DDY5D6gMNu99B3Hc9A== X-Received: by 2002:a05:6820:3082:b0:607:e267:7297 with SMTP id 006d021491bc7-6084c10184amr1043846eaf.5.1746760625781; Thu, 08 May 2025 20:17:05 -0700 (PDT) Received: from my-computer.lan (c-73-76-29-249.hsd1.tx.comcast.net. [73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 006d021491bc7-60842b096desm303745eaf.30.2025.05.08.20.17.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 20:17:05 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, akpm@linux-foundation.org, ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, tmgross@umich.edu, gregkh@linuxfoundation.org, rafael@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, raag.jadav@intel.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, me@kloenk.dev, andrewjballance@gmail.com, fujita.tomonori@gmail.com, daniel.almeida@collabora.com Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 10/11] gpu: nova-core: update to use the new bar and io api Date: Thu, 8 May 2025 22:15:23 -0500 Message-ID: <20250509031524.2604087-11-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" updates nova-core to use the new Io and Bar api. Signed-off-by: Andrew Ballance --- drivers/gpu/nova-core/driver.rs | 4 ++-- drivers/gpu/nova-core/regs.rs | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index a08fb6599267..42596ee2e07f 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -11,7 +11,7 @@ pub(crate) struct NovaCore { } =20 const BAR0_SIZE: usize =3D 8; -pub(crate) type Bar0 =3D pci::Bar; +pub(crate) type Bar0 =3D pci::MMIoBar; =20 kernel::pci_device_table!( PCI_TABLE, @@ -33,7 +33,7 @@ fn probe(pdev: &pci::Device, _info: &Self::IdInfo) = -> Result(0, c_str!("nova-c= ore/bar0"))?; + let bar =3D pdev.iomap_region_sized_hint::(0, c_str!= ("nova-core/bar0"))?; =20 let this =3D KBox::pin_init( try_pin_init!(Self { diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index b1a25b86ef17..079c3d275a47 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 =20 use crate::driver::Bar0; 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[73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 006d021491bc7-60842b096desm303745eaf.30.2025.05.08.20.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 20:17:11 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, akpm@linux-foundation.org, ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, tmgross@umich.edu, gregkh@linuxfoundation.org, rafael@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, raag.jadav@intel.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, me@kloenk.dev, andrewjballance@gmail.com, fujita.tomonori@gmail.com, daniel.almeida@collabora.com Cc: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 11/11] rust: devres: fix doctest Date: Thu, 8 May 2025 22:15:24 -0500 Message-ID: <20250509031524.2604087-12-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" fix a doc test to use the new Io api. Signed-off-by: Andrew Ballance --- rust/kernel/devres.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rust/kernel/devres.rs b/rust/kernel/devres.rs index ddb1ce4a78d9..88d145821ca8 100644 --- a/rust/kernel/devres.rs +++ b/rust/kernel/devres.rs @@ -45,7 +45,7 @@ struct DevresInner { /// # Example /// /// ```no_run -/// # use kernel::{bindings, c_str, device::Device, devres::Devres, io::{I= o, IoRaw}}; +/// # use kernel::{bindings, c_str, device::Device, devres::Devres, io::{I= o, IoRaw, IoAccess}}; /// # use core::ops::Deref; /// /// // See also [`pci::Bar`] for a real example. @@ -80,7 +80,7 @@ struct DevresInner { /// /// fn deref(&self) -> &Self::Target { /// // SAFETY: The memory range stored in `self` has been properly= mapped in `Self::new`. -/// unsafe { Io::from_raw(&self.0) } +/// unsafe { Io::from_raw_ref(&self.0) } /// } /// } /// # fn no_run() -> Result<(), Error> { --=20 2.49.0