From nobody Sun Dec 14 06:19:50 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEF7928DF5C; Fri, 9 May 2025 10:14:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746785673; cv=none; b=M1JFHRe7p/9Ih2piv9HDgVKPLEojZM4FvpRu6xWMboImES2wALFZeAdz28rHisoF0UxcfCpajMYhYqFOEtXp8gj2SFjMDW1ekSJRP3PhqYUyVd78dPg6FEwDFCpS+ri2/GN3rfM+Eqd3xRThAxqFmJgecvB40MTHbOqCqd8bUhA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746785673; c=relaxed/simple; bh=tC3yerrzg8rWelNEn6xwDuErAgY2oEHyEk9X9qlwnaA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pENLFkrkJHiDgTAKUMugoAYBxiOq2+c4gGOdOjHjKtVW9NRbLCBWP0Qm5FuakMNc7cUlg6QUnnol+r/92c+Em9N5un+2pKKPlmIXOHDmvIxSsxmIaoblMY4TpEA/1fyHiPG0w5QmNLI/hfsNZ8RTXEuOMR+Pkls8vk6R9fFUdFQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=nMT5GQ0h; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="nMT5GQ0h" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1746785669; bh=tC3yerrzg8rWelNEn6xwDuErAgY2oEHyEk9X9qlwnaA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nMT5GQ0h5zoIckKo02quXQRW07wwO9O4bAqPovy04mWZsKKVBh18dIr03I0G16P8z xUSNTbWP/JOQk7G0z/qUgAgm+eXTRQvyGmNThHsCzppuqHhe+uFw0bUsTsOsP8tTY9 XtvPqqkBA7OvW/NHxJOLcYIbH5id58dOboiUYrMgpSk22Lp5dxV+1l/sh1EZVbDJMH 2+Hz8v8HchkjdVlKVJoVjOO5m1LAwazY2llYdnIVm5n0/f28ldlbvqm17w3BrTVOVn yPme61YfEEzNu71hPAGJZVBhgrL33pIqIoiz0SUdOEePgM7lHjQMFPkMfaW5acemn3 Hq7g9JiPshkjQ== Received: from yukiji.home (amontpellier-657-1-116-247.w83-113.abo.wanadoo.fr [83.113.51.247]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5E1A417E05A6; Fri, 9 May 2025 12:14:28 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 09 May 2025 12:12:47 +0200 Subject: [PATCH v6 1/5] dt-bindings: gpu: mali-bifrost: Add compatible for MT8370 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250509-mt8370-enable-gpu-v6-1-2833888cb1d3@collabora.com> References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com> In-Reply-To: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Boris Brezillon , Steven Price Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746785666; l=1599; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=tC3yerrzg8rWelNEn6xwDuErAgY2oEHyEk9X9qlwnaA=; b=SUudfoxKoIM1mIWdH3VYBxGXNrCkLcyx4HTJkoy72azrPYoyGg9GUVAiccsh/5z+E1hMTi3Dg CYZ/mD8RwEEBdTdsbet60itRzyJ4bdk+N8iEgxENE9LwjJoZ8OH+DwA X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add a compatible for the MediaTek MT8370 SoC, with an integrated ARM Mali G57 MC2 GPU (Valhall-JM, dual core). None of the already existing SoC specific compatibles is usable as fallback, as those either do not match the number of cores (and number of power domains), or are for a different GPU architecture. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley Signed-off-by: Louis-Alexis Eyraud --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/= Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 019bd28a29f19bb4f7a9c32434b208b6d04db221..5726b79fd0f9de8914f724929f4= 62409e088ec31 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -40,6 +40,7 @@ properties: - enum: - mediatek,mt8188-mali - mediatek,mt8192-mali + - mediatek,mt8370-mali - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision i= s fully discoverable =20 reg: @@ -221,7 +222,9 @@ allOf: properties: compatible: contains: - const: mediatek,mt8186-mali + enum: + - mediatek,mt8186-mali + - mediatek,mt8370-mali then: properties: power-domains: --=20 2.49.0 From nobody Sun Dec 14 06:19:50 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06CFF28ECD2; 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Fri, 9 May 2025 12:14:29 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 09 May 2025 12:12:48 +0200 Subject: [PATCH v6 2/5] drm/panfrost: Drop duplicated Mediatek supplies arrays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250509-mt8370-enable-gpu-v6-2-2833888cb1d3@collabora.com> References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com> In-Reply-To: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Boris Brezillon , Steven Price Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746785666; l=4157; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=R3vnkjN+ASY/SbYqCquRQHrPKm8EfxBUCQMcvUi7KtI=; b=jGPkOxwSIA9wn8AvKqHdSHECc1gmU6zCddwHvpmkh2tzo+xz2IbHmcUQaleAoMb3FicW9++sa jS2gQM6Yzc1CWuP2nSH2v0aCOzIEnlq/+eKwzmYDJVVTiG3zB5LodiK X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= In the panfrost driver, the platform data of several Mediatek SoC declares and uses custom supplies array definitions (mediatek_mt8192_supplies, mediatek_mt8183_b_supplies), that are the same as default_supplies (used by default platform data). So drop these duplicated definitions and use default_supplies instead. Also, rename mediatek_mt8183_supplies to a more generic name too (legacy_supplies). Signed-off-by: Louis-Alexis Eyraud Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_drv.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index f1ec3b02f15a0029d20c7d81046ded59854e885c..7b899a9b2120c608e61dab9ca83= 1ab8e907e8139 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -797,19 +797,18 @@ static const struct panfrost_compatible amlogic_data = =3D { * On new devicetrees please use the _b variant with a single and * coupled regulators instead. */ -static const char * const mediatek_mt8183_supplies[] =3D { "mali", "sram",= NULL }; +static const char * const legacy_supplies[] =3D { "mali", "sram", NULL }; static const char * const mediatek_mt8183_pm_domains[] =3D { "core0", "cor= e1", "core2" }; static const struct panfrost_compatible mediatek_mt8183_data =3D { - .num_supplies =3D ARRAY_SIZE(mediatek_mt8183_supplies) - 1, - .supply_names =3D mediatek_mt8183_supplies, + .num_supplies =3D ARRAY_SIZE(legacy_supplies) - 1, + .supply_names =3D legacy_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), .pm_domain_names =3D mediatek_mt8183_pm_domains, }; =20 -static const char * const mediatek_mt8183_b_supplies[] =3D { "mali", NULL = }; static const struct panfrost_compatible mediatek_mt8183_b_data =3D { - .num_supplies =3D ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1, - .supply_names =3D mediatek_mt8183_b_supplies, + .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, + .supply_names =3D default_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), .pm_domain_names =3D mediatek_mt8183_pm_domains, .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), @@ -817,8 +816,8 @@ static const struct panfrost_compatible mediatek_mt8183= _b_data =3D { =20 static const char * const mediatek_mt8186_pm_domains[] =3D { "core0", "cor= e1" }; static const struct panfrost_compatible mediatek_mt8186_data =3D { - .num_supplies =3D ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1, - .supply_names =3D mediatek_mt8183_b_supplies, + .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, + .supply_names =3D default_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8186_pm_domains), .pm_domain_names =3D mediatek_mt8186_pm_domains, .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), @@ -826,20 +825,19 @@ static const struct panfrost_compatible mediatek_mt81= 86_data =3D { =20 /* MT8188 uses the same power domains and power supplies as MT8183 */ static const struct panfrost_compatible mediatek_mt8188_data =3D { - .num_supplies =3D ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1, - .supply_names =3D mediatek_mt8183_b_supplies, + .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, + .supply_names =3D default_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), .pm_domain_names =3D mediatek_mt8183_pm_domains, .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), .gpu_quirks =3D BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE), }; 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Fri, 9 May 2025 12:14:31 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 09 May 2025 12:12:49 +0200 Subject: [PATCH v6 3/5] drm/panfrost: Commonize Mediatek power domain array definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250509-mt8370-enable-gpu-v6-3-2833888cb1d3@collabora.com> References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com> In-Reply-To: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Boris Brezillon , Steven Price Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746785666; l=4267; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=33sX9S2Jlt4X8Crp65Sy6YYfUXNzf0QbXMSWJBZZdlQ=; b=WJVUyuGGi1RtE1ncr6ro6HoNYyaB727WpQW7A55qXFAouhejxURf32FAa/s9bN4D8upsMCajf +XgR3Q+WWo1BA2ugaopEUfinm6UQ5WonU3zjegpRMGKdLHbIQuk0j04 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= In the panfrost driver, the platform data of several Mediatek SoC declares and uses several different power domains arrays according to GPU core number present in the SoC: - mediatek_mt8186_pm_domains (2 cores) - mediatek_mt8183_pm_domains (3 cores) - mediatek_mt8192_pm_domains (5 cores) As they all are fixed arrays, starting with the same entries and the platform data also has a power domains array length field (num_pm_domains), they can be replaced by a single array, containing all entries, if the num_pm_domains field of the platform data is also set to the matching core number. So, create a generic power domain array (mediatek_pm_domains) and use it in the mt8183(b), mt8186, mt8188 and mt8192 platform data instead. Signed-off-by: Louis-Alexis Eyraud Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_drv.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index 7b899a9b2120c608e61dab9ca831ab8e907e8139..21b28bef84015793d9dba6b1e58= 5891dc0dfcb6d 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -789,6 +789,8 @@ static const struct panfrost_compatible amlogic_data = =3D { .vendor_quirk =3D panfrost_gpu_amlogic_quirk, }; =20 +static const char * const mediatek_pm_domains[] =3D { "core0", "core1", "c= ore2", + "core3", "core4" }; /* * The old data with two power supplies for MT8183 is here only to * keep retro-compatibility with older devicetrees, as DVFS will @@ -798,48 +800,43 @@ static const struct panfrost_compatible amlogic_data = =3D { * coupled regulators instead. */ static const char * const legacy_supplies[] =3D { "mali", "sram", NULL }; -static const char * const mediatek_mt8183_pm_domains[] =3D { "core0", "cor= e1", "core2" }; static const struct panfrost_compatible mediatek_mt8183_data =3D { .num_supplies =3D ARRAY_SIZE(legacy_supplies) - 1, .supply_names =3D legacy_supplies, - .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), - .pm_domain_names =3D mediatek_mt8183_pm_domains, + .num_pm_domains =3D 3, + .pm_domain_names =3D mediatek_pm_domains, }; =20 static const struct panfrost_compatible mediatek_mt8183_b_data =3D { .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, .supply_names =3D default_supplies, - .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), - .pm_domain_names =3D mediatek_mt8183_pm_domains, + .num_pm_domains =3D 3, + .pm_domain_names =3D mediatek_pm_domains, .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), }; =20 -static const char * const mediatek_mt8186_pm_domains[] =3D { "core0", "cor= e1" }; static const struct panfrost_compatible mediatek_mt8186_data =3D { .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, .supply_names =3D default_supplies, - .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8186_pm_domains), - .pm_domain_names =3D mediatek_mt8186_pm_domains, + .num_pm_domains =3D 2, + .pm_domain_names =3D mediatek_pm_domains, .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), }; =20 -/* MT8188 uses the same power domains and power supplies as MT8183 */ static const struct panfrost_compatible mediatek_mt8188_data =3D { .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, .supply_names =3D default_supplies, - .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), - .pm_domain_names =3D mediatek_mt8183_pm_domains, + .num_pm_domains =3D 3, + .pm_domain_names =3D mediatek_pm_domains, .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), .gpu_quirks =3D BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE), }; =20 -static const char * const mediatek_mt8192_pm_domains[] =3D { "core0", "cor= e1", "core2", - "core3", "core4" }; static const struct panfrost_compatible mediatek_mt8192_data =3D { .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, .supply_names =3D default_supplies, - .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8192_pm_domains), - .pm_domain_names =3D mediatek_mt8192_pm_domains, + .num_pm_domains =3D 5, + .pm_domain_names =3D mediatek_pm_domains, .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), .gpu_quirks =3D BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE), }; 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Fri, 9 May 2025 12:14:32 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 09 May 2025 12:12:50 +0200 Subject: [PATCH v6 4/5] drm/panfrost: Add support for Mali on the MT8370 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250509-mt8370-enable-gpu-v6-4-2833888cb1d3@collabora.com> References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com> In-Reply-To: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Boris Brezillon , Steven Price Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746785666; l=2568; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=HGN+lSC329vd4LrTVucVEkhNoI9JDXkgOdKiKkeryhg=; b=LpMLtSXuVD5FDdUslB7iS5yt9l3TGnYZSbqRdL706Aoq8i5sjoLP9giqbFM5Q9FOJyhlNbYoK 9sR7PaooMy9C2RwtjPBqdbwi19X9e60L9wfTIZBC0DwzGRzGCfdppmG X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add a compatible for the MediaTek MT8370 SoC, with an integrated ARM Mali G57 MC2 GPU (Valhall-JM, dual core), with new platform data for its support in the panfrost driver. It uses the same data as MT8186 for the power management features to describe power supplies, pm_domains and enablement (one regulator, two power domains) but also sets the FORCE_AARCH64_PGTABLE flag in the GPU configuration quirks bitfield to enable AARCH64 4K page table format mode. As MT8186 and MT8370 SoC have different GPU architecture (Mali G52 2EE MC2 for MT8186), making them not compatible, and this mode is only enabled for Mediatek SoC that are Mali G57 based (compatible with mediatek,mali-mt8188 or mediatek,mali-8192), having specific platform data allows to set this flag for MT8370 without modifying MT8186 configuration and behaviour. Reviewed-by: Steven Price Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/panfrost/panfrost_drv.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index 21b28bef84015793d9dba6b1e585891dc0dfcb6d..07cd67baa81bfccabf3b1a29f7d= 78702038bb2cd 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -841,6 +841,15 @@ static const struct panfrost_compatible mediatek_mt819= 2_data =3D { .gpu_quirks =3D BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE), }; =20 +static const struct panfrost_compatible mediatek_mt8370_data =3D { + .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, + .supply_names =3D default_supplies, + .num_pm_domains =3D 2, + .pm_domain_names =3D mediatek_pm_domains, + .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), + .gpu_quirks =3D BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE), +}; + static const struct of_device_id dt_match[] =3D { /* Set first to probe before the generic compatibles */ { .compatible =3D "amlogic,meson-gxm-mali", @@ -863,6 +872,7 @@ static const struct of_device_id dt_match[] =3D { { .compatible =3D "mediatek,mt8186-mali", .data =3D &mediatek_mt8186_data= }, { .compatible =3D "mediatek,mt8188-mali", .data =3D &mediatek_mt8188_data= }, { .compatible =3D "mediatek,mt8192-mali", .data =3D &mediatek_mt8192_data= }, + { .compatible =3D "mediatek,mt8370-mali", .data =3D &mediatek_mt8370_data= }, { .compatible =3D "allwinner,sun50i-h616-mali", .data =3D &allwinner_h616= _data }, {} }; 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Fri, 9 May 2025 12:14:34 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 09 May 2025 12:12:51 +0200 Subject: [PATCH v6 5/5] arm64: dts: mediatek: mt8370: Enable gpu support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250509-mt8370-enable-gpu-v6-5-2833888cb1d3@collabora.com> References: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com> In-Reply-To: <20250509-mt8370-enable-gpu-v6-0-2833888cb1d3@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Boris Brezillon , Steven Price Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746785666; l=1948; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=Nh/3NP0bjRTX7YboruB3JZ2xLOeP0c8eAjI6a96C+Ns=; b=eS5XUwVylAb8iDUak8oAOPDL805+h1Snt1WhfhP5/wiMk6RaACqriIaEcPBEjxh/02dQm1DLC cEMADU1uaGeA0DdlZO8WNI/tOi61KEvy5ydd1mr83tlCL9GPmWF18Tg X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add a new gpu node in mt8370.dtsi to enable support for the ARM Mali G57 MC2 GPU (Valhall-JM) found on the MT8370 SoC, using the Panfrost driver. On a Mediatek Genio 510 EVK board, the panfrost driver probed with the following message: ``` panfrost 13000000.gpu: clock rate =3D 390000000 panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0 panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003, 80000400 panfrost 13000000.gpu: Features: L2:0x08130206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7 panfrost 13000000.gpu: shader_present=3D0x5 l2_present=3D0x1 [drm] Initialized panfrost 1.3.0 for 13000000.gpu on minor 0 ``` Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- arch/arm64/boot/dts/mediatek/mt8370.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8370.dtsi b/arch/arm64/boot/dts= /mediatek/mt8370.dtsi index cf1a3759451ff899ce9e63e5a00f192fb483f6e5..7ac8b8d0349455922a73f35db60= 7b2b27cad23d7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8370.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8370.dtsi @@ -59,6 +59,22 @@ &cpu_little3_cooling_map0 { <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; =20 +/* + * Please note that overriding compatibles is a discouraged practice and i= s a + * clear indication of nodes not being, well, compatible! + * + * This is a special case, where the GPU is the same as MT8188, but with o= ne + * of the cores fused out in this lower-binned SoC. + */ +&gpu { + compatible =3D "mediatek,mt8370-mali", "arm,mali-valhall-jm"; + + power-domains =3D <&spm MT8188_POWER_DOMAIN_MFG2>, + <&spm MT8188_POWER_DOMAIN_MFG3>; + + power-domain-names =3D "core0", "core1"; +}; + &ppi_cluster0 { affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3>; }; --=20 2.49.0