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Fri, 09 May 2025 04:07:06 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:56 +0100 Subject: [PATCH 09/14] spi: spi-fsl-dspi: Reinitialize DSPI regs after resuming for S32G Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250509-james-nxp-spi-v1-9-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Clark X-Mailer: b4 0.14.0 From: Larisa Grigore After resuming, DSPI registers (MCR and SR) need to be reinitialized for S32G platforms. Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 73 +++++++++++++++++++++++++-----------------= ---- 1 file changed, 40 insertions(+), 33 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 50cec3b94322..0613642d769d 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1258,6 +1258,39 @@ static const struct of_device_id fsl_dspi_dt_ids[] = =3D { }; MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); =20 +static int dspi_init(struct fsl_dspi *dspi) +{ + unsigned int mcr; + + /* Set idle states for all chip select signals to high */ + mcr =3D SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0)); + + if (dspi->devtype_data->trans_mode =3D=3D DSPI_XSPI_MODE) + mcr |=3D SPI_MCR_XSPI; + if (!spi_controller_is_target(dspi->ctlr)) + mcr |=3D SPI_MCR_HOST; + + regmap_write(dspi->regmap, SPI_MCR, mcr); + regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); + + switch (dspi->devtype_data->trans_mode) { + case DSPI_XSPI_MODE: + regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE); + break; + case DSPI_DMA_MODE: + regmap_write(dspi->regmap, SPI_RSER, + SPI_RSER_TFFFE | SPI_RSER_TFFFD | + SPI_RSER_RFDFE | SPI_RSER_RFDFD); + break; + default: + dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", + dspi->devtype_data->trans_mode); + return -EINVAL; + } + + return 0; +} + #ifdef CONFIG_PM_SLEEP static int dspi_suspend(struct device *dev) { @@ -1284,6 +1317,13 @@ static int dspi_resume(struct device *dev) if (ret) return ret; spi_controller_resume(dspi->ctlr); + + ret =3D dspi_init(dspi); + if (ret) { + dev_err(dev, "failed to initialize dspi during resume\n"); + return ret; + } + if (dspi->irq) enable_irq(dspi->irq); =20 @@ -1293,39 +1333,6 @@ static int dspi_resume(struct device *dev) =20 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); =20 -static int dspi_init(struct fsl_dspi *dspi) -{ - unsigned int mcr; - - /* Set idle states for all chip select signals to high */ - mcr =3D SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0)); - - if (dspi->devtype_data->trans_mode =3D=3D DSPI_XSPI_MODE) - mcr |=3D SPI_MCR_XSPI; - if (!spi_controller_is_target(dspi->ctlr)) - mcr |=3D SPI_MCR_HOST; - - regmap_write(dspi->regmap, SPI_MCR, mcr); - regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); - - switch (dspi->devtype_data->trans_mode) { - case DSPI_XSPI_MODE: - regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE); - break; - case DSPI_DMA_MODE: - regmap_write(dspi->regmap, SPI_RSER, - SPI_RSER_TFFFE | SPI_RSER_TFFFD | - SPI_RSER_RFDFE | SPI_RSER_RFDFD); - break; - default: - dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", - dspi->devtype_data->trans_mode); - return -EINVAL; - } - - return 0; -} - static int dspi_target_abort(struct spi_controller *host) { struct fsl_dspi *dspi =3D spi_controller_get_devdata(host); --=20 2.34.1