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Fri, 09 May 2025 04:06:59 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:51 +0100 Subject: [PATCH 04/14] spi: spi-fsl-dspi: Add config and regmaps for S32G platforms Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250509-james-nxp-spi-v1-4-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Clark X-Mailer: b4 0.14.0 From: Larisa Grigore S32G adds SPI_{T,R}XFR4 and extends SPI_CTAR registers to 5. Add the new regmaps, configs and bits. dspi_volatile_ranges gets SPI_{T,R}XFR4 added which affects all platforms, however they are further limited by dspi_yes_ranges. Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 39 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 701cf56d28e7..df6f85122bfe 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -35,7 +35,7 @@ #define SPI_TCR 0x08 #define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16) =20 -#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4)) +#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(2, 0)) * 4)) #define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27)) #define SPI_CTAR_CPOL BIT(26) #define SPI_CTAR_CPHA BIT(25) @@ -92,12 +92,14 @@ #define SPI_TXFR1 0x40 #define SPI_TXFR2 0x44 #define SPI_TXFR3 0x48 +#define SPI_TXFR4 0x4C #define SPI_RXFR0 0x7c #define SPI_RXFR1 0x80 #define SPI_RXFR2 0x84 #define SPI_RXFR3 0x88 +#define SPI_RXFR4 0x8C =20 -#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4)) +#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(2, 0)) * 4)) #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16) #define SPI_CTARE_DTCP(x) ((x) & 0x7ff) =20 @@ -135,6 +137,7 @@ enum { LX2160A, MCF5441X, VF610, + S32G }; =20 static const struct regmap_range dspi_yes_ranges[] =3D { @@ -146,15 +149,29 @@ static const struct regmap_range dspi_yes_ranges[] = =3D { regmap_reg_range(SPI_SREX, SPI_SREX), }; =20 +static const struct regmap_range s32g_dspi_yes_ranges[] =3D { + regmap_reg_range(SPI_MCR, SPI_MCR), + regmap_reg_range(SPI_TCR, SPI_CTAR(5)), + regmap_reg_range(SPI_SR, SPI_TXFR4), + regmap_reg_range(SPI_RXFR0, SPI_RXFR4), + regmap_reg_range(SPI_CTARE(0), SPI_CTARE(5)), + regmap_reg_range(SPI_SREX, SPI_SREX), +}; + static const struct regmap_access_table dspi_access_table =3D { .yes_ranges =3D dspi_yes_ranges, .n_yes_ranges =3D ARRAY_SIZE(dspi_yes_ranges), }; =20 +static const struct regmap_access_table s32g_dspi_access_table =3D { + .yes_ranges =3D s32g_dspi_yes_ranges, + .n_yes_ranges =3D ARRAY_SIZE(s32g_dspi_yes_ranges), +}; + static const struct regmap_range dspi_volatile_ranges[] =3D { regmap_reg_range(SPI_MCR, SPI_TCR), regmap_reg_range(SPI_SR, SPI_SR), - regmap_reg_range(SPI_PUSHR, SPI_RXFR3), + regmap_reg_range(SPI_PUSHR, SPI_RXFR4), regmap_reg_range(SPI_SREX, SPI_SREX) }; =20 @@ -166,6 +183,7 @@ static const struct regmap_access_table dspi_volatile_t= able =3D { enum { DSPI_REGMAP, DSPI_XSPI_REGMAP, + S32G_DSPI_XSPI_REGMAP, DSPI_PUSHR }; =20 @@ -188,6 +206,15 @@ static const struct regmap_config dspi_regmap_config[]= =3D { .wr_table =3D &dspi_access_table, .rd_table =3D &dspi_access_table }, + [S32G_DSPI_XSPI_REGMAP] =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D 0x13c, + .volatile_table =3D &dspi_volatile_table, + .wr_table =3D &s32g_dspi_access_table, + .rd_table =3D &s32g_dspi_access_table, + }, [DSPI_PUSHR] =3D { .name =3D "pushr", .reg_bits =3D 16, @@ -262,6 +289,12 @@ static const struct fsl_dspi_devtype_data devtype_data= [] =3D { .fifo_size =3D 16, .regmap =3D &dspi_regmap_config[DSPI_REGMAP] }, + [S32G] =3D { + .trans_mode =3D DSPI_XSPI_MODE, + .max_clock_factor =3D 1, + .fifo_size =3D 5, + .regmap =3D &dspi_regmap_config[S32G_DSPI_XSPI_REGMAP] + } }; =20 struct fsl_dspi_dma { --=20 2.34.1