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Fri, 09 May 2025 04:07:09 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:58 +0100 Subject: [PATCH 11/14] spi: spi-fsl-dspi: Halt the module after a new message transfer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250509-james-nxp-spi-v1-11-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bogdan-Gabriel Roman , James Clark X-Mailer: b4 0.14.0 From: Bogdan-Gabriel Roman The XSPI mode implementation in this driver still uses the EOQ flag to signal the last word in a transmission and deassert the PCS signal. However, at speeds lower than ~200kHZ, the PCS signal seems to remain asserted even when SR[EOQF] =3D 1 indicates the end of a transmission. This is a problem for target devices which require the deassertation of the PCS signal between transfers. Hence, this commit 'forces' the deassertation of the PCS by stopping the module through MCR[HALT] after completing a new transfer. According to the reference manual, the module stops or transitions from the Running state to the Stopped state after the current frame, when any one of the following conditions exist: - The value of SR[EOQF] =3D 1. - The chip is in Debug mode and the value of MCR[FRZ] =3D 1. - The value of MCR[HALT] =3D 1. This shouldn't be done if the last transfer in the message has cs_change set. Signed-off-by: Bogdan-Gabriel Roman Signed-off-by: Larisa Grigore Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 31521dac1580..db921ee6305f 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -64,6 +64,7 @@ #define SPI_SR_TFIWF BIT(18) #define SPI_SR_RFDF BIT(17) #define SPI_SR_CMDFFF BIT(16) +#define SPI_SR_TXRXS BIT(30) #define SPI_SR_CLEAR (SPI_SR_TCFQF | \ SPI_SR_TFUF | SPI_SR_TFFF | \ SPI_SR_CMDTCF | SPI_SR_SPEF | \ @@ -1056,9 +1057,20 @@ static int dspi_transfer_one_message(struct spi_cont= roller *ctlr, struct spi_transfer *transfer; bool cs =3D false; int status =3D 0; + u32 val =3D 0; + bool cs_change =3D false; =20 message->actual_length =3D 0; =20 + /* Put DSPI in running mode if halted. */ + regmap_read(dspi->regmap, SPI_MCR, &val); + if (val & SPI_MCR_HALT) { + regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, 0); + while (regmap_read(dspi->regmap, SPI_SR, &val) >=3D 0 && + !(val & SPI_SR_TXRXS)) + ; + } + list_for_each_entry(transfer, &message->transfers, transfer_list) { dspi->cur_transfer =3D transfer; dspi->cur_msg =3D message; @@ -1088,6 +1100,7 @@ static int dspi_transfer_one_message(struct spi_contr= oller *ctlr, dspi->tx_cmd |=3D SPI_PUSHR_CMD_CONT; } =20 + cs_change =3D transfer->cs_change; dspi->tx =3D transfer->tx_buf; dspi->rx =3D transfer->rx_buf; dspi->len =3D transfer->len; @@ -1125,6 +1138,15 @@ static int dspi_transfer_one_message(struct spi_cont= roller *ctlr, dspi_deassert_cs(spi, &cs); } =20 + if (status || !cs_change) { + /* Put DSPI in stop mode */ + regmap_update_bits(dspi->regmap, SPI_MCR, + SPI_MCR_HALT, SPI_MCR_HALT); + while (regmap_read(dspi->regmap, SPI_SR, &val) >=3D 0 && + val & SPI_SR_TXRXS) + ; + } + message->status =3D status; spi_finalize_current_message(ctlr); =20 @@ -1306,6 +1328,8 @@ static int dspi_init(struct fsl_dspi *dspi) if (!spi_controller_is_target(dspi->ctlr)) mcr |=3D SPI_MCR_HOST; =20 + mcr |=3D SPI_MCR_HALT; + regmap_write(dspi->regmap, SPI_MCR, mcr); regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); =20 --=20 2.34.1