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Fri, 09 May 2025 04:06:55 -0700 (PDT) From: James Clark Date: Fri, 09 May 2025 12:05:48 +0100 Subject: [PATCH 01/14] spi: spi-fsl-dspi: Define regmaps per device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250509-james-nxp-spi-v1-1-32bfcd2fea11@linaro.org> References: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> In-Reply-To: <20250509-james-nxp-spi-v1-0-32bfcd2fea11@linaro.org> To: Vladimir Oltean , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , larisa.grigore@nxp.com, arnd@linaro.org, andrei.stefanescu@nxp.com, dan.carpenter@linaro.org Cc: linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Clark X-Mailer: b4 0.14.0 Refactor the regmaps so they can be defined per device rather than programmatically. This will allow us to add two new regmaps for S32G in a later commit. No functional changes. Signed-off-by: James Clark Reviewed-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 121 ++++++++++++++++++++++++-----------------= ---- 1 file changed, 66 insertions(+), 55 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 067c954cb6ea..31ea8ce81e98 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -121,6 +121,7 @@ struct fsl_dspi_devtype_data { enum dspi_trans_mode trans_mode; u8 max_clock_factor; int fifo_size; + const struct regmap_config *regmap; }; =20 enum { @@ -136,60 +137,123 @@ enum { VF610, }; =20 +static const struct regmap_range dspi_volatile_ranges[] =3D { + regmap_reg_range(SPI_MCR, SPI_TCR), + regmap_reg_range(SPI_SR, SPI_SR), + regmap_reg_range(SPI_PUSHR, SPI_RXFR3), +}; + +static const struct regmap_access_table dspi_volatile_table =3D { + .yes_ranges =3D dspi_volatile_ranges, + .n_yes_ranges =3D ARRAY_SIZE(dspi_volatile_ranges), +}; + +static const struct regmap_range dspi_xspi_volatile_ranges[] =3D { + regmap_reg_range(SPI_MCR, SPI_TCR), + regmap_reg_range(SPI_SR, SPI_SR), + regmap_reg_range(SPI_PUSHR, SPI_RXFR3), + regmap_reg_range(SPI_SREX, SPI_SREX), +}; + +static const struct regmap_access_table dspi_xspi_volatile_table =3D { + .yes_ranges =3D dspi_xspi_volatile_ranges, + .n_yes_ranges =3D ARRAY_SIZE(dspi_xspi_volatile_ranges), +}; + +enum { + DSPI_REGMAP, + DSPI_XSPI_REGMAP, + DSPI_PUSHR +}; + +static const struct regmap_config dspi_regmap_config[] =3D { + [DSPI_REGMAP] =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D 0x88, + .volatile_table =3D &dspi_volatile_table + }, + [DSPI_XSPI_REGMAP] =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D 0x13c, + .volatile_table =3D &dspi_xspi_volatile_table + }, + [DSPI_PUSHR] =3D { + .name =3D "pushr", + .reg_bits =3D 16, + .val_bits =3D 16, + .reg_stride =3D 2, + .max_register =3D 0x2 + } +}; + static const struct fsl_dspi_devtype_data devtype_data[] =3D { [VF610] =3D { .trans_mode =3D DSPI_DMA_MODE, .max_clock_factor =3D 2, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_REGMAP] }, [LS1021A] =3D { /* Has A-011218 DMA erratum */ .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS1012A] =3D { /* Has A-011218 DMA erratum */ .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 16, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS1028A] =3D { .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS1043A] =3D { /* Has A-011218 DMA erratum */ .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 16, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS1046A] =3D { /* Has A-011218 DMA erratum */ .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 16, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS2080A] =3D { .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LS2085A] =3D { .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [LX2160A] =3D { .trans_mode =3D DSPI_XSPI_MODE, .max_clock_factor =3D 8, .fifo_size =3D 4, + .regmap =3D &dspi_regmap_config[DSPI_XSPI_REGMAP] }, [MCF5441X] =3D { .trans_mode =3D DSPI_DMA_MODE, .max_clock_factor =3D 8, .fifo_size =3D 16, + .regmap =3D &dspi_regmap_config[DSPI_REGMAP] }, }; =20 @@ -1167,54 +1231,6 @@ static int dspi_resume(struct device *dev) =20 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); =20 -static const struct regmap_range dspi_volatile_ranges[] =3D { - regmap_reg_range(SPI_MCR, SPI_TCR), - regmap_reg_range(SPI_SR, SPI_SR), - regmap_reg_range(SPI_PUSHR, SPI_RXFR3), -}; - -static const struct regmap_access_table dspi_volatile_table =3D { - .yes_ranges =3D dspi_volatile_ranges, - .n_yes_ranges =3D ARRAY_SIZE(dspi_volatile_ranges), -}; - -static const struct regmap_config dspi_regmap_config =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D 0x88, - .volatile_table =3D &dspi_volatile_table, -}; - -static const struct regmap_range dspi_xspi_volatile_ranges[] =3D { - regmap_reg_range(SPI_MCR, SPI_TCR), - regmap_reg_range(SPI_SR, SPI_SR), - regmap_reg_range(SPI_PUSHR, SPI_RXFR3), - regmap_reg_range(SPI_SREX, SPI_SREX), -}; - -static const struct regmap_access_table dspi_xspi_volatile_table =3D { - .yes_ranges =3D dspi_xspi_volatile_ranges, - .n_yes_ranges =3D ARRAY_SIZE(dspi_xspi_volatile_ranges), -}; - -static const struct regmap_config dspi_xspi_regmap_config[] =3D { - { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D 0x13c, - .volatile_table =3D &dspi_xspi_volatile_table, - }, - { - .name =3D "pushr", - .reg_bits =3D 16, - .val_bits =3D 16, - .reg_stride =3D 2, - .max_register =3D 0x2, - }, -}; - static int dspi_init(struct fsl_dspi *dspi) { unsigned int mcr; @@ -1272,7 +1288,6 @@ static int dspi_target_abort(struct spi_controller *h= ost) static int dspi_probe(struct platform_device *pdev) { struct device_node *np =3D pdev->dev.of_node; - const struct regmap_config *regmap_config; struct fsl_dspi_platform_data *pdata; struct spi_controller *ctlr; int ret, cs_num, bus_num =3D -1; @@ -1355,11 +1370,7 @@ static int dspi_probe(struct platform_device *pdev) goto out_ctlr_put; } =20 - if (dspi->devtype_data->trans_mode =3D=3D DSPI_XSPI_MODE) - regmap_config =3D &dspi_xspi_regmap_config[0]; - else - regmap_config =3D &dspi_regmap_config; - dspi->regmap =3D devm_regmap_init_mmio(&pdev->dev, base, regmap_config); + dspi->regmap =3D devm_regmap_init_mmio(&pdev->dev, base, dspi->devtype_da= ta->regmap); if (IS_ERR(dspi->regmap)) { dev_err(&pdev->dev, "failed to init regmap: %ld\n", PTR_ERR(dspi->regmap)); @@ -1370,7 +1381,7 @@ static int dspi_probe(struct platform_device *pdev) if (dspi->devtype_data->trans_mode =3D=3D DSPI_XSPI_MODE) { dspi->regmap_pushr =3D devm_regmap_init_mmio( &pdev->dev, base + SPI_PUSHR, - &dspi_xspi_regmap_config[1]); + &dspi_regmap_config[DSPI_PUSHR]); if (IS_ERR(dspi->regmap_pushr)) { dev_err(&pdev->dev, "failed to init pushr regmap: %ld\n", --=20 2.34.1