From nobody Sun Sep 28 19:18:25 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 372D3231A21; Thu, 8 May 2025 23:49:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746748188; cv=none; b=WuE+atfkuCeWwsk+iH08IfBt3DEWwN8Iy8QN0G4xErWoFN4cmuGqt6Vuse6QsYovchivqq/1ksiZFMPDxVItkSrA0IvjVBhKreuV3aUixCk9U8DkTPOyHghXDUh63qPO/NJ1xmj/jnUQA3uhE5Ci/LFk5FEqxk791aC68OAJV+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746748188; c=relaxed/simple; bh=Wrr79+CJ85JON8vzwGdPUpl+grkKCAE70pkA3RyyukE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=a5foHocRBlCMbbRn3gyOldFesZ5Y7wFCKu0t+r1y3ADHaUk1FI+0ZdnsFFw+WRvuLTeuefPEedSNbS6weRGktM0goIc4ZCR1xob7VuOIAmQvs5fVKwqJ+Bl7rE2LHtel0R1/W5wy2iE4wx7GrZy+VAiSzL9ay3jg/kKRttk3cL8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=S/9aZ/2H; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="S/9aZ/2H" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id B59862616D; Fri, 9 May 2025 01:49:45 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 4QjRQtUPG1cv; Fri, 9 May 2025 01:49:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1746748185; bh=Wrr79+CJ85JON8vzwGdPUpl+grkKCAE70pkA3RyyukE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=S/9aZ/2HezfZdjTgdwbeEnVbIrxyPOwgKMFCvoUWj6ejuTBUiQ5NtT5KYsbf9eo5K ArnQarhvElmRIwp/fxPCFrMsgVrn9zfi4PJ5u8qEUZC7TGU8GoBUnBlpO9/ddnEdoU 8/NiG9eXhpipnU8FzdCTXO597PA1Zr6qHh4dlrtM3mvXNUB8sFm7vDHbI4ZsRjUwXC gZ8ChBeVl2pANsaQK5Nk13hTWqhvE7nmfd4imobispiopwEaukYOJMkaSWMvdb3JuW mPBs8YUuPqylGwOkbQB9mz1Ued0nggZd5SEQlNxz1lbDhoY7rd+Grl/xAk+SH334Wm 2WcMJrNRrwHoA== From: Yao Zi To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman , Yao Zi , Chukun Pan Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/2] arm64: dts: rockchip: Add SDMMC/SDIO controllers for RK3528 Date: Thu, 8 May 2025 23:48:29 +0000 Message-ID: <20250508234829.27111-3-ziyao@disroot.org> In-Reply-To: <20250508234829.27111-2-ziyao@disroot.org> References: <20250508234829.27111-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RK3528 features two SDIO controllers and one SD/MMC controller, describe them in devicetree. Since their sample and drive clocks are located in the VO and VPU GRFs, corresponding syscons are added to make these clocks available. Signed-off-by: Yao Zi Reviewed-by: Jonas Karlman --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 69 ++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts= /rockchip/rk3528.dtsi index 923cff6bb103..193b84b5e912 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -329,6 +329,16 @@ qos_vpu: qos@ff280400 { reg =3D <0x0 0xff280400 0x0 0x20>; }; =20 + vpu_grf: syscon@ff340000 { + compatible =3D "rockchip,rk3528-vpu-grf", "syscon"; + reg =3D <0x0 0xff340000 0x0 0x8000>; + }; + + vo_grf: syscon@ff360000 { + compatible =3D "rockchip,rk3528-vo-grf", "syscon"; + reg =3D <0x0 0xff360000 0x0 0x10000>; + }; + cru: clock-controller@ff4a0000 { compatible =3D "rockchip,rk3528-cru"; reg =3D <0x0 0xff4a0000 0x0 0x30000>; @@ -691,6 +701,65 @@ sdhci: mmc@ffbf0000 { status =3D "disabled"; }; =20 + sdio0: mmc@ffc10000 { + compatible =3D "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg =3D <0x0 0xffc10000 0x0 0x4000>; + clocks =3D <&cru HCLK_SDIO0>, + <&cru CCLK_SRC_SDIO0>, + <&cru SCLK_SDIO0_DRV>, + <&cru SCLK_SDIO0_SAMPLE>; + clock-names =3D "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth =3D <0x100>; + interrupts =3D ; + max-frequency =3D <200000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>; + resets =3D <&cru SRST_H_SDIO0>; + reset-names =3D "reset"; + status =3D "disabled"; + }; + + sdio1: mmc@ffc20000 { + compatible =3D "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg =3D <0x0 0xffc20000 0x0 0x4000>; + clocks =3D <&cru HCLK_SDIO1>, + <&cru CCLK_SRC_SDIO1>, + <&cru SCLK_SDIO1_DRV>, + <&cru SCLK_SDIO1_SAMPLE>; + clock-names =3D "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth =3D <0x100>; + interrupts =3D ; + max-frequency =3D <200000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>; + resets =3D <&cru SRST_H_SDIO1>; + reset-names =3D "reset"; + status =3D "disabled"; + }; + + sdmmc: mmc@ffc30000 { + compatible =3D "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg =3D <0x0 0xffc30000 0x0 0x4000>; + clocks =3D <&cru HCLK_SDMMC0>, + <&cru CCLK_SRC_SDMMC0>, + <&cru SCLK_SDMMC_DRV>, + <&cru SCLK_SDMMC_SAMPLE>; + clock-names =3D "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth =3D <0x100>; + interrupts =3D ; + max-frequency =3D <150000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, + <&sdmmc_det>; + resets =3D <&cru SRST_H_SDMMC0>; + reset-names =3D "reset"; + rockchip,default-sample-phase =3D <90>; + status =3D "disabled"; + }; + dmac: dma-controller@ffd60000 { compatible =3D "arm,pl330", "arm,primecell"; reg =3D <0x0 0xffd60000 0x0 0x4000>; --=20 2.49.0 From nobody Sun Sep 28 19:18:25 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99FC9235364; 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arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="f1c0b3M7" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 33436260B4; Fri, 9 May 2025 01:49:50 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id VPESXp933hLo; Fri, 9 May 2025 01:49:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1746748189; bh=kijDMJqlKD9yOwTzumhm7hP9dmi1d/mq0EYroDcjheQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=f1c0b3M7TFg29F5QhsevI49hCuPo4IrRvwmi8ks6DNd5Z/g60gSAXZ4rugDMUihhF PzsKj+ojPPyp5hq/zLgn5WKV8GgJSItjZVs2oe+ghP54ne6GU0Xqaaq81bMqHGVi+o PjA1vSGT6uvbfCIqDC8m4KkoAhRUAHHzAMZQMrUyES+bn7QomuB5ac16dAmBIMgxXV YJw8se8qNqodYfORFxtgSB8rBxN5+Nn0ck04iuAWtykgHlgLFMZ3HaBubBb9jVPiQF MEr3xEU9+9Q44CWW7MvAEfxSvQoQnwygerzELOC01ldEwSNOCal9i2ua7SNSfn7DD9 Qph50B6duksmQ== From: Yao Zi To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman , Yao Zi , Chukun Pan Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 2/2] arm64: dts: rockchip: Enable SD-card interface on Radxa E20C Date: Thu, 8 May 2025 23:48:30 +0000 Message-ID: <20250508234829.27111-4-ziyao@disroot.org> In-Reply-To: <20250508234829.27111-2-ziyao@disroot.org> References: <20250508234829.27111-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SD-card is available on Radxa E20C board. Signed-off-by: Yao Zi Reviewed-by: Jonas Karlman --- .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm6= 4/boot/dts/rockchip/rk3528-radxa-e20c.dts index 0942baba6b8f..d45b6594b2de 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts @@ -18,6 +18,7 @@ / { =20 aliases { mmc0 =3D &sdhci; + mmc1 =3D &sdmmc; }; =20 chosen { @@ -130,6 +131,18 @@ vcc5v0_sys: regulator-5v0-vcc-sys { regulator-max-microvolt =3D <5000000>; }; =20 + vccio_sd: regulator-vccio-sd { + compatible =3D "regulator-gpio"; + gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc_vol_ctrl_h>; + regulator-name =3D "vccio_sd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + states =3D <1800000 0x0>, <3300000 0x1>; + vin-supply =3D <&vcc5v0_sys>; + }; + vdd_arm: regulator-vdd-arm { compatible =3D "pwm-regulator"; pwms =3D <&pwm1 0 5000 PWM_POLARITY_INVERTED>; @@ -205,6 +218,12 @@ wan_led_g: wan-led-g { rockchip,pins =3D <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + sdmmc { + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins =3D <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; =20 &pwm1 { @@ -235,6 +254,17 @@ &sdhci { status =3D "okay"; }; =20 +&sdmmc { + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0m0_xfer>; --=20 2.49.0