From nobody Tue Dec 16 07:31:11 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57DDD4B1E6E; Thu, 8 May 2025 15:52:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746719551; cv=none; b=n/q0bRptBJv0XShMs5foG53FJ6g5abeS1ygIJNg4ArM6p6AqKOM8r8uDZoXsy2pifTT2htAbayciyBd6zMHHs3dxIwKh3ZMiniP1t6bvJlmaeu8nSU58zSI5paUJ2c8jjBfJ76lr/JkNj/I1s+6WZy50QCgM5WbZe6jiBl2ibKA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746719551; c=relaxed/simple; bh=MfwWOk6Tx/TEqv605hM8mog1v0i46hFLimGEGpLYuUE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uJrbcWRFI1sums8Aym+kRDsyU22ayn3jNDhKjNtwX+JHYjvosFmW8lU468eS/UwAKY8MZOmB4F7m4KsjvrRwG4Lz2o+CNog4ESAsdgFyEPf71Bwb7RPjQxXT1cSBlVf5zc7Qcf8ZD4UNzJs/zCIOzuho+PT6SBZb9Gbfu0i72cQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=YHwFXXnr; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="YHwFXXnr" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 548FqDse1703887 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 8 May 2025 10:52:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746719533; bh=zkRgnerI36b6HY4HkOyt64j/523Zu+/FuRNnOX/SiVU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YHwFXXnr4fOELaKYHk/U08lGuFNTXHVKouN4qlQWfFLD3HTEGnQA+SxmgR4YArG0a NkgYTuc+qxstuKAAN+Xhu1PCKmvgu9z2Kd8LFwZtrdPlBYa/aQFmGi2RGkt02lqJMG kInUO9MijHRiyPJq6fnPAZLl6qnGFMei5Zgwa6Jc= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 548FqD6x027835 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 May 2025 10:52:13 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 May 2025 10:52:12 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 May 2025 10:52:12 -0500 Received: from abhilash-HP.dhcp.ti.com (abhilash-hp.dhcp.ti.com [172.24.227.115]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 548Fq2oL050794; Thu, 8 May 2025 10:52:09 -0500 From: Yemike Abhilash Chandra To: , , , , , CC: , , , , , , , Subject: [PATCH v2 1/4] arm64: dts: ti: j722s-evm: Add DT nodes for power regulators Date: Thu, 8 May 2025 21:21:31 +0530 Message-ID: <20250508155134.2026300-2-y-abhilashchandra@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250508155134.2026300-1-y-abhilashchandra@ti.com> References: <20250508155134.2026300-1-y-abhilashchandra@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add device tree nodes for two regulators on the J722S-EVM. VSYS_3V3 is the output of LM5141-Q1, and it serves as an input to TPS22990 which produces VSYS_3V3_EXP [1]. VSYS_3V3_EXP serves as vin-supply to CSI RPI Connectors. Signed-off-by: Yemike Abhilash Chandra [1]: https://www.ti.com/lit/zip/sprr495 Reviewed-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index 34b9d190800e..0f18fe710929 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -141,6 +141,17 @@ vsys_5v0: regulator-vsys5v0 { regulator-boot-on; }; =20 + vsys_3v3: regulator-vsys3v3 { + /* output of LM5141-Q1 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + vdd_mmc1: regulator-mmc1 { /* TPS22918DBVR */ compatible =3D "regulator-fixed"; @@ -153,6 +164,17 @@ vdd_mmc1: regulator-mmc1 { bootph-all; }; =20 + vcc_3v3_exp: regulator-TPS22990 { + /* output of TPS22990 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_exp"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vsys_3v3>; + regulator-always-on; + regulator-boot-on; + }; + vdd_sd_dv: regulator-TLV71033 { compatible =3D "regulator-gpio"; regulator-name =3D "tlv71033"; --=20 2.34.1 From nobody Tue Dec 16 07:31:11 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05D4E279791; Thu, 8 May 2025 15:53:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746719592; cv=none; b=IO/DqZx5DTS6ZIULyQMTuGYrCK1O0zWurtK9JTHnpiwzbHGzLZ/Yqncti1R8cFPIibDO5gufWIutNADga6D5/FQEz2WSflAnSntDfwF7l0qtzROolirnODFch3cy27DpBe9wXOSYwwTve5wbtHA9Lwy5cGZoVYcTt4fbpr+RzL4= ARC-Message-Signature: i=1; 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Thu, 8 May 2025 10:52:43 -0500 Received: from abhilash-HP.dhcp.ti.com (abhilash-hp.dhcp.ti.com [172.24.227.115]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 548Fq2oM050794; Thu, 8 May 2025 10:52:39 -0500 From: Yemike Abhilash Chandra To: , , , , , CC: , , , , , , , Subject: [PATCH v2 2/4] arm64: dts: ti: j722s-evm: Add MUX to control CSI2RX Date: Thu, 8 May 2025 21:21:32 +0530 Message-ID: <20250508155134.2026300-3-y-abhilashchandra@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250508155134.2026300-1-y-abhilashchandra@ti.com> References: <20250508155134.2026300-1-y-abhilashchandra@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" J722S EVM has the CSI2RX routed to a MIPI CSI connector and to 22-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index 0f18fe710929..43256c71a19c 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -266,6 +266,20 @@ transceiver2: can-phy2 { max-bitrate =3D <5000000>; standby-gpios =3D <&exp1 17 GPIO_ACTIVE_HIGH>; }; + + csi01_mux: mux-controller-0 { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp1 6 GPIO_ACTIVE_HIGH>; + idle-state =3D <0>; + }; + + csi23_mux: mux-controller-1 { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp1 7 GPIO_ACTIVE_HIGH>; + idle-state =3D <0>; + }; }; =20 &main_pmx0 { --=20 2.34.1 From nobody Tue Dec 16 07:31:11 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDC1B279791; Thu, 8 May 2025 15:53:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746719585; cv=none; b=lHqqqiOVpD06dSOkKTYBrjCbHb3aeEOYzL9QF65i+kt6yMsLEFdFOPKI5HsIABRAugTAvjBtAtgHMCZwzj7kstuFpPiy4hnloohmgcdJ8PqWKq8xeQfJbREYkefs0WzRFHbdZLsOPHhpfQxiu02HGMAL5GtooPwTalbC3dAl6+k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746719585; c=relaxed/simple; bh=F/q9V2sM+hxPkDRhThRcshxDMo5H7oWL7zvs20GHR2g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SVkNv8pEOIeaCR4eU6YSHsrgDl8d0aFEobZisNX68ToELoRb3vntb/5cRABEbMahrd/62MgcW3mzxsykP672cJDuoN5DOOufgQ+R1MVMIEVXWXmt7EIRiw4lvDhB9PLsMYjqEGvfRJaLH5MD2u10nfn/NND2MioLu6rcQy9+vBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=iZ3PVDJ1; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="iZ3PVDJ1" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 548FqnFn1704159 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 8 May 2025 10:52:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746719569; bh=33sKYYkXDp1y4LV52B5pg7ZkBuRmivNNRuVE+7WRY68=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iZ3PVDJ1oVypnLzeqMYYkW0jiQ2xr+MY+fQVNNu0PkP4nApb5RIfs5+P6iM8g58/R qSOG0OdDetdg5E9gm76lsyd7B6+8FCmVyA3/UPSsbLupDh9Pmq0WfJlWtFNAeVsEEB R4U9oFiUiP3O4/EzrLbsApODHqit6e2puNDKWJ/c= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 548Fqn9b028061 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 May 2025 10:52:49 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 May 2025 10:52:48 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 May 2025 10:52:48 -0500 Received: from abhilash-HP.dhcp.ti.com (abhilash-hp.dhcp.ti.com [172.24.227.115]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 548Fq2oN050794; Thu, 8 May 2025 10:52:44 -0500 From: Yemike Abhilash Chandra To: , , , , , CC: , , , , , , , Subject: [PATCH v2 3/4] arm64: dts: ti: k3-j722s-evm: Add overlay for quad IMX219 Date: Thu, 8 May 2025 21:21:33 +0530 Message-ID: <20250508155134.2026300-4-y-abhilashchandra@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250508155134.2026300-1-y-abhilashchandra@ti.com> References: <20250508155134.2026300-1-y-abhilashchandra@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Vaishnav Achath RPi v2 Camera (IMX219) is an 8MP camera that can be used with J722S EVM through the 22-pin CSI-RX connector. Add a reference overlay for quad IMX219 RPI camera v2 modules on J722S EVM Signed-off-by: Vaishnav Achath Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar --- arch/arm64/boot/dts/ti/Makefile | 5 + ...k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso | 329 ++++++++++++++++++ 2 files changed, 334 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-i= mx219.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 3c3aa09a94b6..b317eaff64cc 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo # Boards with J722s SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-beagley-ai.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo =20 # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb @@ -227,6 +228,8 @@ k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-= board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo k3-j742s2-evm-usb0-type-a-dtbs :=3D k3-j742s2-evm.dtb \ k3-j784s4-j742s2-evm-usb0-type-a.dtbo +k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs :=3D k3-j722s-evm.dtb \ + k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-evm.dtb \ @@ -264,6 +267,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ k3-j742s2-evm-usb0-type-a.dtb \ + k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ k3-j784s4-evm-usb0-type-a.dtb \ @@ -288,5 +292,6 @@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721e-evm-pcie0-ep +=3D -@ DTC_FLAGS_k3-j721e-sk +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ +DTC_FLAGS_k3-j722s-evm +=3D -@ DTC_FLAGS_k3-j784s4-evm +=3D -@ DTC_FLAGS_k3-j742s2-evm +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.d= tso b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso new file mode 100644 index 000000000000..5e5f08dd2ba9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DT Overlay for RPi Camera V2.1 on J722S-EVM board. + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://datasheets.raspberrypi.com/camera/camera-v2-schemat= ics.pdf + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + cam0_reset_pins_default: cam0-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x03c, PIN_OUTPUT, 7) /* (R22) GPIO0_15 */ + >; + }; + + cam1_reset_pins_default: cam1-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x044, PIN_OUTPUT, 7) /* (R26) GPIO0_17 */ + >; + }; + + cam2_reset_pins_default: cam2-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x04c, PIN_OUTPUT, 7) /* (T25) GPIO0_19 */ + >; + }; + + cam3_reset_pins_default: cam3-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x054, PIN_OUTPUT, 7) /* (T21) GPIO0_21 */ + >; + }; +}; + +&{/} { + clk_imx219_fixed: clock-24000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + reg_2p8v: regulator-2p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "2P8V"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <&vcc_3v3_exp>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "1P8V"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_3v3_exp>; + regulator-always-on; + }; + + reg_1p2v: regulator-1p2v { + compatible =3D "regulator-fixed"; + regulator-name =3D "1P2V"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <&vcc_3v3_exp>; + regulator-always-on; + }; +}; + +&csi01_mux { + idle-state =3D <1>; +}; + +&csi23_mux { + idle-state =3D <1>; +}; + +&pca9543_0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + imx219_0: sensor@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + + VANA-supply =3D <®_2p8v>; + VDIG-supply =3D <®_1p8v>; + VDDL-supply =3D <®_1p2v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam0_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 15 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint =3D <&csi2rx0_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + imx219_1: sensor@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + + VANA-supply =3D <®_2p8v>; + VDIG-supply =3D <®_1p8v>; + VDDL-supply =3D <®_1p2v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam1_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 17 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint =3D <&csi2rx1_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; +}; + +&pca9543_1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + imx219_2: sensor@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + + VANA-supply =3D <®_2p8v>; + VDIG-supply =3D <®_1p8v>; + VDDL-supply =3D <®_1p2v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam2_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 19 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam2: endpoint { + remote-endpoint =3D <&csi2rx2_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + imx219_3: sensor@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + + VANA-supply =3D <®_2p8v>; + VDIG-supply =3D <®_1p8v>; + VDDL-supply =3D <®_1p2v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam3_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam3: endpoint { + remote-endpoint =3D <&csi2rx3_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam0>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam1>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam2>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx3 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi3_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx3_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam3>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status =3D "okay"; +}; + +&dphy0 { + status =3D "okay"; +}; + +&ti_csi2rx1 { + status =3D "okay"; +}; + +&dphy1 { + status =3D "okay"; +}; + +&ti_csi2rx2 { + status =3D "okay"; +}; + +&dphy2 { + status =3D "okay"; +}; + +&ti_csi2rx3 { + status =3D "okay"; +}; + +&dphy3 { + status =3D "okay"; +}; --=20 2.34.1 From nobody Tue Dec 16 07:31:11 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFF2B279916; Thu, 8 May 2025 15:53:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" From: Vaishnav Achath TechNexion TEVI OV5640 camera is a 5MP camera that can be used with J722S EVM through the 22-pin CSI-RX connector. Add a reference overlay for quad TEVI OV5640 modules on J722S EVM. Signed-off-by: Vaishnav Achath Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar --- arch/arm64/boot/dts/ti/Makefile | 4 + .../k3-j722s-evm-csi2-quad-tevi-ov5640.dtso | 322 ++++++++++++++++++ 2 files changed, 326 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov56= 40.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index b317eaff64cc..b0ac5c05274f 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -133,6 +133,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-beagley-ai.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo =20 # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb @@ -230,6 +231,8 @@ k3-j742s2-evm-usb0-type-a-dtbs :=3D k3-j742s2-evm.dtb \ k3-j784s4-j742s2-evm-usb0-type-a.dtbo k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs :=3D k3-j722s-evm.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo +k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs :=3D k3-j722s-evm.dtb \ + k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-evm.dtb \ @@ -268,6 +271,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ k3-j742s2-evm-usb0-type-a.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \ + k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ k3-j784s4-evm-usb0-type-a.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso= b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso new file mode 100644 index 000000000000..55e767a020d9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * 4 x TEVI OV5640 MIPI Camera module on RPI camera connector. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_ov5640_fixed: clock-24000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + reg_2p8v: regulator-2p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "2P8V"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <&vcc_3v3_exp>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "1P8V"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_3v3_exp>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "3P3V"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3v3_exp>; + regulator-always-on; + }; +}; + + +&main_pmx0 { + cam0_reset_pins_default: cam0-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x03c, PIN_OUTPUT, 7) /* (R22) GPIO0_15 */ + >; + }; + + cam1_reset_pins_default: cam1-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x044, PIN_OUTPUT, 7) /* (R26) GPIO0_17 */ + >; + }; + + cam2_reset_pins_default: cam2-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x04c, PIN_OUTPUT, 7) /* (T25) GPIO0_19 */ + >; + }; + + cam3_reset_pins_default: cam3-default-reset-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x054, PIN_OUTPUT, 7) /* (T21) GPIO0_21 */ + >; + }; +}; + +&csi01_mux { + idle-state =3D <1>; +}; + +&csi23_mux { + idle-state =3D <1>; +}; + +&pca9543_0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + ov5640_0: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + AVDD-supply =3D <®_2p8v>; + DOVDD-supply =3D <®_1p8v>; + DVDD-supply =3D <®_3p3v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam0_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 15 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint =3D <&csi2rx0_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; + + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + ov5640_1: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + AVDD-supply =3D <®_2p8v>; + DOVDD-supply =3D <®_1p8v>; + DVDD-supply =3D <®_3p3v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam1_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 17 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint =3D <&csi2rx1_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; +}; + +&pca9543_1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + ov5640_2: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + AVDD-supply =3D <®_2p8v>; + DOVDD-supply =3D <®_1p8v>; + DVDD-supply =3D <®_3p3v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam2_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 19 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam2: endpoint { + remote-endpoint =3D <&csi2rx2_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; + + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + ov5640_3: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + + AVDD-supply =3D <®_2p8v>; + DOVDD-supply =3D <®_1p8v>; + DVDD-supply =3D <®_3p3v>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam3_reset_pins_default>; + + reset-gpios =3D <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam3: endpoint { + remote-endpoint =3D <&csi2rx3_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam0>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam1>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam2>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx3 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi3_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx3_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam3>; + bus-type =3D <4>; /* CSI2 DPHY */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status =3D "okay"; +}; + +&dphy0 { + status =3D "okay"; +}; + +&ti_csi2rx1 { + status =3D "okay"; +}; + +&dphy1 { + status =3D "okay"; +}; + + +&ti_csi2rx2 { + status =3D "okay"; +}; + +&dphy2 { + status =3D "okay"; +}; + + +&ti_csi2rx3 { + status =3D "okay"; +}; + +&dphy3 { + status =3D "okay"; +}; --=20 2.34.1