From nobody Tue Dec 16 05:57:59 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 565F827A11C; Thu, 8 May 2025 15:10:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746717042; cv=none; b=TD+NYtA4dtWe6zn8l9vIecGcI0Px7F2kYKZmEN4uPg3aKTD79bh8U/3NnKN2vARV2JdDt+8LR71r8XOJW4axMjfN3p2CRdrejIXHfj8+YyE/RgmEXkSueMwKLDDBs7jn+yGDHONBNU4+68gu0jerAhFZqzISQSKE5X7nVZbh7nQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746717042; c=relaxed/simple; bh=VsZJM4fdgTC4TBsJStz1wEpdUgPObcJD8shMbI2R9Lc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CpJ/1Mlp/LSym3Zq/TkRTC9sqJq+zffgyFJ1mUN0vNazOWWNUsgfKx9wDttmLe9/Ckc6k2GyMZdGAjU/i2LJZ7OACy+sCyRsyIOobzPygPd2LCpsaoUO/I2ikMEmA5cKY5lYUS5/61oHlBWiOQE7xhkUq8rfEdkPnLeIRxO4p+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=DPBnjYC9; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="DPBnjYC9" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=QxndbpgSNr0cYULeSq6GWDTM3BOUwJ9UwSQ4i+jhzdA=; b=DPBnjYC9VvLA1k1DxrxMKjwsqd 9XFI13phL5Pigm43MuKdoXV94t46mU7vZ6YvRGdFA9lnczL5Qx448YsXOwd4T4sYQotsLhI9vAA7/ ew7DqZ9DMMxzU487udci9mPt7YmCR1YBpacaJQqKSXxJkFXk3p5qTjCWSe8v57uUzQuy46u0zOUZu dI1HKBQ8TGRaix2ozfBcb88ZEl1SzTVydmLSsw6xatnhns8Dax1n2RDYU01yltbmApM+KK6mV8d+7 oel5qf7Fzh7p3DUd0Z6VCGGzaQ8V3uYzBoCP/PgPNGj+w85pd0YhZDCWZ7exoBP6zHr5h/m5VdV7x 1wZZfUaw==; Received: from i53875a1d.versanet.de ([83.135.90.29] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uD2tE-0005fP-AW; Thu, 08 May 2025 17:10:24 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH 1/6] arm64: dts: rockchip: add basic mdio node to px30 Date: Thu, 8 May 2025 17:09:50 +0200 Message-ID: <20250508150955.1897702-2-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250508150955.1897702-1-heiko@sntech.de> References: <20250508150955.1897702-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Using snps,reset-* properties for handling the phy-reset is deprecated and instead a real phy node should be defined that then contains the reset-gpios handling. To facilitate this, add the core mdio node under the px30's gmac, similar to how the other Rockchip socs already do this. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/px30.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/r= ockchip/px30.dtsi index 9137dd76e72c..feabdadfa440 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -985,6 +985,12 @@ gmac: ethernet@ff360000 { resets =3D <&cru SRST_GMAC_A>; reset-names =3D "stmmaceth"; status =3D "disabled"; + + mdio: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; }; =20 sdmmc: mmc@ff370000 { --=20 2.47.2 From nobody Tue Dec 16 05:57:59 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ED7528468D; Thu, 8 May 2025 15:10:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746717039; cv=none; b=adK2cDUsPoPYzbuBnpKo1lM8rpExvNwMS/Griicc+cU2RrUtItiWgsLH5U5O2GzaQ89WojI91JqcMRiuwIL69EytwAJt2Io5qzQFerM1fD5yYS3BUaYoYWfvQYV650wNcxHXzNf+7rEd8ZWcCi67WFluW40R637Pq58XgdxQOV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746717039; c=relaxed/simple; bh=4clY6zjdX72t09bsA0j5RCRCA/dSROqNIJ8RImooIgg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OP9YvCUkRwdp/p43fRnzhZC+k18j+SXehJJOq2ETpvkPuxzsiSHhE4oO0YoYtC2i7ic53M6SC+Ksz79bih4TEdwv/77RupflmLjvJMsFewEZGSRbyrJwOdgKfSo/p+Nbz16jYqtP4BuWhncQtOgEdexK+bYuDfVQnjfTIzbQ8LA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=znn8OgGb; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="znn8OgGb" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=v6Lj3OAwwGDjaJkTxr/XS365aD/k3hFs5qcq4+YYQ/k=; b=znn8OgGbdaC154+C8vhI9MKwYX olq81jiDghVLyEbBYFNKGPVT6ChEzuizdstYVMOwQoo6VcS/smYBzzW8v6OBpGahzvAUbLcrFLz0P Em2IuekeFfLNTBwR4sws22Sr2ZxWdtynRh6MbFCPCL25APaOs6qrwOaj8QQXTqDMvUAg3Cb3Rq4ig gbz5QrImXjcvP3zwmX6tSzM6JguFAgS3ifHnhT8aSqv2Z0Xh04ZgN/jFQ5ZD2vJ3Zf6aRZ1h5gLx5 fSql2Tpb2lNRcxrIudBP6mw//VKwk1+b266qQNgcEQYfq/BH1icAy3r0DKBzJsy71uKUi5Sjn/4Qj 7Rywv23A==; Received: from i53875a1d.versanet.de ([83.135.90.29] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uD2tE-0005fP-OE; Thu, 08 May 2025 17:10:24 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH 2/6] arm64: dts: rockchip: move reset to dedicated eth-phy node on ringneck Date: Thu, 8 May 2025 17:09:51 +0200 Message-ID: <20250508150955.1897702-3-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250508150955.1897702-1-heiko@sntech.de> References: <20250508150955.1897702-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Using snps,reset-* properties to handle the ethernet-phy resets is deprecated and instead a real phy node should be used. Move the Ringneck phy-reset properties to such a node Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Tested-by: Quentin Schulz --- .../boot/dts/rockchip/px30-ringneck.dtsi | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/b= oot/dts/rockchip/px30-ringneck.dtsi index 142244d52706..ab232e5c7ad6 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -83,9 +83,7 @@ &emmc { =20 /* On-module TI DP83825I PHY but no connector, enable in carrierboard */ &gmac { - snps,reset-gpio =3D <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us =3D <0 50000 50000>; + phy-handle =3D <&dp83825>; phy-supply =3D <&vcc_3v3>; clock_in_out =3D "output"; }; @@ -344,6 +342,18 @@ &io_domains { status =3D "okay"; }; =20 +&mdio { + dp83825: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&phy_rst>; + reset-assert-us =3D <50000>; + reset-deassert-us =3D <50000>; + reset-gpios =3D <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -351,6 +361,12 @@ emmc_reset: emmc-reset { }; }; =20 + ethernet { + phy_rst: phy-rst { + rockchip,pins =3D <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { module_led_pin: module-led-pin { rockchip,pins =3D <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; --=20 2.47.2 From nobody Tue Dec 16 05:57:59 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 708D31581E0; Thu, 8 May 2025 15:10:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746717039; cv=none; b=QrmtJAAzTWEpdzUfa1f2YTCIyqBhmuLDONG0D86+5tCTu9WeRqLLIbBXfcULR33f4EBhv1b/RBpwwFrjVkQM4PkmKZwB1T7ziQnxRE9boo67PP1U3njCIwAJYljH8puiIMYz06hk4jUbXojrqAEeJCilugFD0Sk1MR0lDTwDILE= ARC-Message-Signature: i=1; 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charset="utf-8" From: Heiko Stuebner Cobra are Touchscreen devices built around the PX30 SoC using a variety of display options. The devices feature an EMMC, network port, usb host + OTG ports and a 720x1280 display with a touchscreen. Signed-off-by: Heiko Stuebner Acked-by: Conor Dooley Reviewed-by: Quentin Schulz --- Documentation/devicetree/bindings/arm/rockchip.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 650fb833d96e..6435c724e682 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1109,6 +1109,16 @@ properties: - rockchip,rv1126 - rockchip,rv1109 =20 + - description: Theobroma Systems PX30-Cobra + items: + - enum: + - tsd,px30-cobra-ltk050h3146w + - tsd,px30-cobra-ltk050h3146w-a2 + - tsd,px30-cobra-ltk050h3148w + - tsd,px30-cobra-ltk500hd1829 + - const: tsd,px30-cobra + - const: rockchip,px30 + - description: Theobroma Systems PX30-uQ7 with Haikou baseboard items: - const: tsd,px30-ringneck-haikou --=20 2.47.2 From nobody Tue Dec 16 05:57:59 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B8E22798E4; Thu, 8 May 2025 15:10:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746717041; cv=none; b=u3NKIZs1tHJXTa98B7PKLVbmQFg3sX9SdqhxEDNcIig8oo24tFlJghPrTxfGaIsGbxcn36zsLjOTLyogL6BwHB8vqzgWf5tDPBuJ0QWFB/Qu7avj4FAGB5lscUu0sBVj7K3j+8wYEY3mIUM54dgEM4Dj3rR2JHHaM4spApV4gm0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746717041; c=relaxed/simple; bh=9Xep61xbZ2MAeuFTXrRagisPqdNz+8L5RunI5/tfdvQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mO9Tkfy3lVPmkzDcYjSwHwPBN5ehnWHfKIeJvlUpUu/pdQlqNRd9J1bzWdcz7+/0jOLDDparnw/L7jVlUP88lLKTyjUpPSZTmmoSSuKebHDX6OJMQjtSM1uMCbZfiKm/oWPp3cN6rbJLlAUb0hXV0nWSjFGUFZ2xLsKmq212ZTY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=LYPyuQp9; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="LYPyuQp9" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=1Ws3cYh42CTI3N0AP5Ab2LRltszdLuziGFjHuUVHnHE=; b=LYPyuQp9ObUaT1SSREE2DLiqaR +DegIbA338jyqqF3WNrxrB6a/2xJsVL13nY+BupQtSdc735TUmR59Rp1P3C5+n8s5fFSeUvSeOoX4 ahbBBp6BR5zNSCeBYG1DIzCOQ8fQbRn2O9kjhN2FNrK4KkK6VqzPqM7Rp9M43UDbatnQELEU/Dybg aFJjMMpS+s93JV2tcBurrAk/6+k0f6FAZXNzyJ1glFCwizWPL1xTS+Zn7jPdaz8H95OIWc5Ofb5ny 37Rh1EBEjDKrHJapoIHGYHKPfyD80W8WCAJF1b95YKsjLsoSo2bQp/f3Qi7fks5ckMdKiReXR9JXx fNRDT18g==; Received: from i53875a1d.versanet.de ([83.135.90.29] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uD2tF-0005fP-Iv; Thu, 08 May 2025 17:10:25 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH 4/6] arm64: dts: rockchip: add px30-cobra base dtsi and board variants Date: Thu, 8 May 2025 17:09:53 +0200 Message-ID: <20250508150955.1897702-5-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250508150955.1897702-1-heiko@sntech.de> References: <20250508150955.1897702-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Cobra are Touchscreen devices built around the PX30 SoC using a variety of display options. The devices feature an EMMC, network port, usb host + OTG ports and a 720x1280 display with a touchscreen. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 4 + .../rockchip/px30-cobra-ltk050h3146w-a2.dts | 39 ++ .../dts/rockchip/px30-cobra-ltk050h3146w.dts | 39 ++ .../dts/rockchip/px30-cobra-ltk050h3148w.dts | 39 ++ .../dts/rockchip/px30-cobra-ltk500hd1829.dts | 58 ++ arch/arm64/boot/dts/rockchip/px30-cobra.dtsi | 570 ++++++++++++++++++ 6 files changed, 749 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2= .dts create mode 100644 arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts create mode 100644 arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts create mode 100644 arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts create mode 100644 arch/arm64/boot/dts/rockchip/px30-cobra.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 3e8771ef69ba..8151e8bb1cd3 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,4 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-cobra-ltk050h3146w-a2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-cobra-ltk050h3146w.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-cobra-ltk050h3148w.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-cobra-ltk500hd1829.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-ctouch2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-ctouch2-of10.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts b/= arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts new file mode 100644 index 000000000000..1d26164be7b8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-cobra.dtsi" + +/ { + model =3D "Theobroma Systems Cobra with LTK050H3146W-A2 Display"; + compatible =3D "tsd,px30-cobra-ltk050h3146w-a2", "tsd,px30-cobra", "rockc= hip,px30"; +}; + +&dsi { + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk050h3146w-a2"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc_1v8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dsp_rst>; + reset-gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply =3D <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts b/arc= h/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts new file mode 100644 index 000000000000..82c6acdb4fae --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-cobra.dtsi" + +/ { + model =3D "Theobroma Systems Cobra with LTK050H3146W Display"; + compatible =3D "tsd,px30-cobra-ltk050h3146w", "tsd,px30-cobra", "rockchip= ,px30"; +}; + +&dsi { + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk050h3146w"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc_1v8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dsp_rst>; + reset-gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply =3D <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts b/arc= h/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts new file mode 100644 index 000000000000..94449132df38 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-cobra.dtsi" + +/ { + model =3D "Theobroma Systems Cobra with ltk050h3148w Display"; + compatible =3D "tsd,px30-cobra-ltk050h3148w", "tsd,px30-cobra", "rockchip= ,px30"; +}; + +&dsi { + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk050h3148w"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc_1v8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dsp_rst>; + reset-gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply =3D <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts b/arc= h/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts new file mode 100644 index 000000000000..418b4b4daaa3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-cobra.dtsi" + +/ { + model =3D "Theobroma Systems Cobra prototype with LTK500HD1829 Display"; + compatible =3D "tsd,px30-cobra-ltk500hd1829", "tsd,px30-cobra", "rockchip= ,px30"; + + aliases { + mmc1 =3D &sdmmc; + }; +}; + +&dsi { + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk500hd1829"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc_1v8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dsp_rst>; + reset-gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; +}; + +&sdmmc { + bus-width =3D <4>; + broken-cd; + cap-sd-highspeed; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply =3D <&vccio_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi b/arch/arm64/boot= /dts/rockchip/px30-cobra.dtsi new file mode 100644 index 000000000000..92066cbc1a70 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi @@ -0,0 +1,570 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include +#include +#include +#include +#include "px30.dtsi" + +/ { + aliases { + mmc0 =3D &emmc; + }; + + chosen { + stdout-path =3D "serial5:115200n8"; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + power-supply =3D <&vcc5v0_sys>; + pwms =3D <&pwm0 0 25000 0>; + }; + + beeper { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm1 0 1000 0>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible =3D "mmc-pwrseq-emmc"; + pinctrl-0 =3D <&emmc_reset>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + + led-0 { + color =3D ; + gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + label =3D "heartbeat"; + linux,default-trigger =3D "heartbeat"; + }; + }; + + pwm-leds { + compatible =3D "pwm-leds"; + + ring_red: led-0 { + color =3D ; + default-state =3D "off"; + label =3D "ring_red"; + pwms =3D <&pwm5 0 1000000 0>; + max-brightness =3D <255>; + }; + + ring_green: led-1 { + color =3D ; + default-state =3D "off"; + label =3D "ring_green"; + pwms =3D <&pwm6 0 1000000 0>; + max-brightness =3D <255>; + }; + + ring_blue: led-2 { + color =3D ; + default-state =3D "off"; + label =3D "ring_blue"; + pwms =3D <&pwm7 0 1000000 0>; + max-brightness =3D <255>; + }; + }; + + /* also named 5V_Q7 in schematics */ + vcc5v0_sys: regulator-vccsys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; +}; + +&cpu0 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_arm>; +}; + +&display_subsystem { + status =3D "okay"; +}; + +&dsi_dphy { + status =3D "okay"; +}; + +&emmc { + bus-width =3D <8>; + cap-mmc-highspeed; + /* + * For hs200 support, U-Boot would have to set the RK809 DCDC4 + * rail to 1.8V from the default of 3.0V. It doesn't do that on + * devices out in the field, so disable hs200. + * mmc-hs200-1_8v; + */ + mmc-pwrseq =3D <&emmc_pwrseq>; + non-removable; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_emmc>; + status =3D "okay"; +}; + +&gmac { + clock_in_out =3D "output"; + phy-handle =3D <&dp83825>; + phy-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_log>; + status =3D "okay"; +}; + +/* I2C0 =3D PMIC, STUSB4500, RTC */ +&i2c0 { + status =3D "okay"; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + #clock-cells =3D <0>; + clock-output-names =3D "xin32k"; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + wakeup-source; + rockchip,system-power-controller; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc_3v3>; + vcc6-supply =3D <&vcc_3v3>; + vcc7-supply =3D <&vcc_3v3>; + vcc9-supply =3D <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name =3D "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name =3D "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG5 { + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc_3v0_1v8: vcc_emmc: DCDC_REG4 { + regulator-name =3D "vcc_3v0_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3000000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc_1v0: LDO_REG3 { + regulator-name =3D "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + + vcc_2v8: LDO_REG4 { + regulator-name =3D "vcc_2v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <2800000>; + }; + }; + + /* + * vccio_sd also supplies the vmmc supply, so needs + * to stay single voltage. + */ + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3000000>; + }; + }; + + /* vcc_sdio also supplies the pull-up resistors for i2c1 */ + vcc_sdio: LDO_REG6 { + regulator-name =3D "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc_lcd: LDO_REG7 { + regulator-name =3D "vcc_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + + vcc_1v8_lcd: LDO_REG8 { + regulator-name =3D "vcc_1v8_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca_1v8: LDO_REG9 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&i2c2 { + clock-frequency =3D <100000>; + i2c-scl-falling-time-ns =3D <50>; + i2c-scl-rising-time-ns =3D <300>; + status =3D "okay"; + + touchscreen@14 { + compatible =3D "goodix,gt911"; + reg =3D <0x14>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + irq-gpios =3D <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tch_int &tch_rst>; + reset-gpios =3D <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-x; + AVDD28-supply =3D <&vcc_2v8>; + VDDIO-supply =3D <&vcc_3v3>; + }; +}; + +/* + * Enable pull-ups to prevent floating pins when the touch + * panel is not connected. + */ +&i2c2_xfer { + rockchip,pins =3D + <2 RK_PB7 2 &pcfg_pull_up>, + <2 RK_PC0 2 &pcfg_pull_up>; +}; + +&io_domains { + vccio1-supply =3D <&vcc_sdio>; + vccio2-supply =3D <&vccio_sd>; + vccio3-supply =3D <&vcc_3v3>; + vccio4-supply =3D <&vcc_3v3>; + vccio5-supply =3D <&vcc_1v8>; + vccio6-supply =3D <&vcc_emmc>; + status =3D "okay"; +}; + +&mdio { + dp83825: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&phy_rst>; + reset-assert-us =3D <50000>; + reset-deassert-us =3D <50000>; + reset-gpios =3D <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cobra_pin_hog>; + + hog { + cobra_pin_hog: cobra_pin_hog { + rockchip,pins =3D + /* STUSB4500 open drain outout POWER_OK2, needs pull-up */ + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + /* STUSB4500 open drain outout POWER_OK3, needs pull-up */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + /* The default pull-down can keep the IC in reset. */ + <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, + /* USB-A 5V enable */ + <3 RK_PC0 RK_FUNC_GPIO &pcfg_output_high>, + /* USB-A data enable */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_high>, + /* USB_HUB1_RESET */ + <0 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>, + /* USB_HUB2_RESET */ + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins =3D + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + phy_rst: phy-rst { + rockchip,pins =3D + <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + panel { + tch_int: tch-int { + rockchip,pins =3D + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + tch_rst: tch-rst { + rockchip,pins =3D + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + dsp_rst: dsp-rst { + rockchip,pins =3D + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins =3D + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_pin: soc-slppin { + rockchip,pins =3D + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc-slppin-slp { + rockchip,pins =3D + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc-slppin-rst { + rockchip,pins =3D + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc_3v3>; + pmuio2-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { + status =3D "okay"; +}; + +&pwm5 { + status =3D "okay"; +}; + +&pwm6 { + status =3D "okay"; +}; + +&pwm7 { + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&tsadc { + status =3D "okay"; +}; + +&u2phy { + status =3D "okay"; +}; + +&u2phy_host { + status =3D "okay"; +}; + +&u2phy_otg { + status =3D "okay"; +}; + +&uart1 { + /delete-property/ dmas; + /delete-property/ dma-names; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_xfer>; + status =3D "okay"; +}; + +&uart5 { + pinctrl-0 =3D <&uart5_xfer>; + status =3D "okay"; +}; + +&usb20_otg { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&vopb { + status =3D "okay"; +}; + +&vopb_mmu { + status =3D "okay"; +}; + +&vopl { + status =3D "disabled"; +}; + +&vopl_mmu { + status =3D "disabled"; +}; + +&wdt { + status =3D "okay"; +}; --=20 2.47.2 From nobody Tue Dec 16 05:57:59 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ECA327A90E; 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Received: from i53875a1d.versanet.de ([83.135.90.29] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uD2tG-0005fP-0y; Thu, 08 May 2025 17:10:26 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH 5/6] dt-bindings: arm: rockchip: add PX30-PP1516 boards from Theobroma Systems Date: Thu, 8 May 2025 17:09:54 +0200 Message-ID: <20250508150955.1897702-6-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250508150955.1897702-1-heiko@sntech.de> References: <20250508150955.1897702-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner PP1516 are Touchscreen devices built around the PX30 SoC and companion devices to PX30-Cobra, again with multiple display options. The devices feature an EMMC, OTG port and a 720x1280 display with a touchscreen and camera Signed-off-by: Heiko Stuebner Acked-by: Conor Dooley Reviewed-by: Quentin Schulz --- Documentation/devicetree/bindings/arm/rockchip.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 6435c724e682..58af37b4d6b8 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1119,6 +1119,14 @@ properties: - const: tsd,px30-cobra - const: rockchip,px30 =20 + - description: Theobroma Systems PX30-PP1516 + items: + - enum: + - tsd,px30-pp1516-ltk050h3146w-a2 + - tsd,px30-pp1516-ltk050h3148w + - const: tsd,px30-pp1516 + - const: rockchip,px30 + - description: Theobroma Systems PX30-uQ7 with Haikou baseboard items: - const: tsd,px30-ringneck-haikou --=20 2.47.2 From nobody Tue Dec 16 05:57:59 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ED10283FFA; Thu, 8 May 2025 15:10:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746717038; cv=none; b=RH+Ykd+j3RdJUSmXghME/++CeRKVJknICROI8A1flq6slCtngrbBrosom1M17F5vC3Vqo6Tz40U2AUNHso1YwmqhIYWl+pLsb/nQQWQX46i/emfP6FmPTqvMJiByfpFoSj2p4qxNfpNy7p9nm28SHJUac9uXEZFOOCsjEhrJEnU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746717038; c=relaxed/simple; bh=n+9Tx2Li+q+OLJjVPL7vPosmWKeo974C9d3XtoK2L50=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kbgvZsmrYKJ+RBF5lyzcpL8mE2ZUh/4C0/byXdF7cEYzwlMXFWbSPhC4YBvE2U+zNlxEL7kRji5OVnlR6NrZ0joP+dUE6EDPL0Ga6/D1vmSPeyJWNGoj5TI9Njvk7WwRUVpozhR1bm1HJZX6pZeycweOfAT4CO4JZ/VBAH2KFvM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=qoka9tfQ; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="qoka9tfQ" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=LPqyxanN+42RIG3m9ACZR0qPdqhLbitXArcHw0z/Obc=; b=qoka9tfQSeuLhOn/287J7LX4dt MTRztaOYNoskYojNyRQoXxJoWGqXabyhlAwSS9E+RnLgQ89LB05wP0dB/afMQYaqPwYHA5rzQAFo1 ePXuIZmd3hWTuv/0OPZVi/UAx95IYfpKlE0BhuG1j95el1KhVZqSfkLif4P/Tqa30R6Fbh5QEqI4e bPoUzYIvbE9mCMbnU9t1Ti/Dj4axzNb9BQaubFJ0GaYav/dTpMJzvtpoD2UwelTW8ABMQUsstWPAU EqB4eLV2O/W4mcZgU9Os0EvvmlABK5au0cSIsGSmUYVEGG9mRIglryaptPXE0WhrG6y9T8ds0dLGn ta3gYajA==; Received: from i53875a1d.versanet.de ([83.135.90.29] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uD2tG-0005fP-E9; Thu, 08 May 2025 17:10:26 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH 6/6] arm64: dts: rockchip: add px30-pp1516 base dtsi and board variants Date: Thu, 8 May 2025 17:09:55 +0200 Message-ID: <20250508150955.1897702-7-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250508150955.1897702-1-heiko@sntech.de> References: <20250508150955.1897702-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner PP1516 are Touchscreen devices built around the PX30 SoC and companion devices to PX30-Cobra, again with multiple display options. The devices feature an EMMC, OTG port and a 720x1280 display with a touchscreen and camera Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../rockchip/px30-pp1516-ltk050h3146w-a2.dts | 39 ++ .../dts/rockchip/px30-pp1516-ltk050h3148w.dts | 39 ++ arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi | 601 ++++++++++++++++++ 4 files changed, 681 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a= 2.dts create mode 100644 arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.d= ts create mode 100644 arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 8151e8bb1cd3..899113f88a29 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-cto= uch2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-ctouch2-of10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-firefly-jd4-core-mb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-pp1516-ltk050h3146w-a2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-pp1516-ltk050h3148w.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-lvds-9904379.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-video-demo.dtbo diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts b= /arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts new file mode 100644 index 000000000000..b71929bcb33e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-pp1516.dtsi" + +/ { + model =3D "Theobroma Systems PP-1516 with LTK050H3146W-A2 Display"; + compatible =3D "tsd,px30-pp1516-ltk050h3146w-a2", "tsd,px30-pp1516", "roc= kchip,px30"; +}; + +&dsi { + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk050h3146w-a2"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc_1v8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dsp_rst>; + reset-gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply =3D <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts b/ar= ch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts new file mode 100644 index 000000000000..a9bd5936c701 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-pp1516.dtsi" + +/ { + model =3D "Theobroma Systems PP-1516 with LTK050H3148W Display"; + compatible =3D "tsd,px30-pp1516-ltk050h3148w", "tsd,px30-pp1516", "rockch= ip,px30"; +}; + +&dsi { + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk050h3148w"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc_1v8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dsp_rst>; + reset-gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply =3D <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi b/arch/arm64/boo= t/dts/rockchip/px30-pp1516.dtsi new file mode 100644 index 000000000000..121654b17764 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi @@ -0,0 +1,601 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include +#include +#include +#include "px30.dtsi" + +/ { + aliases { + mmc0 =3D &emmc; + }; + + chosen { + stdout-path =3D "serial5:115200n8"; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + power-supply =3D <&vcc5v0_sys>; + pwms =3D <&pwm0 0 25000 0>; + }; + + beeper { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm1 0 1000 0>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible =3D "mmc-pwrseq-emmc"; + pinctrl-0 =3D <&emmc_reset>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + + /* + * LED2 on the PCB, left of the USB-C connector. + * Typically NOT populated. + */ + debug: led-0 { + label =3D "debug"; + gpios =3D <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "none"; + }; + + /* + * LED14 on the PCB, left of the PX30 SoC. + * Typically NOT populated. + */ + heartbeat: led-1 { + label =3D "heartbeat"; + gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + vcc1v2_sys: regulator-vcc1v2-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc1v2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + vcc5v0_sys: regulator-vccsys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc_cam_avdd: regulator-vcc-cam-avdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_cam_avdd"; + gpio =3D <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam_avdd_en>; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <&vcc_2v8>; + }; + + vcc_cam_dovdd: regulator-vcc-cam-dovdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_cam_dovdd"; + gpio =3D <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam_dovdd_en>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_1v8>; + }; + + vcc_cam_dvdd: regulator-vcc-cam-dvdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_cam_dvdd"; + gpio =3D <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam_dvdd_en>; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <&vcc1v2_sys>; + }; + + vcc_lens_afvdd: regulator-vcc-lens-afvdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_lens_afvdd"; + gpio =3D <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam_afdd_en>; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <&vcc_2v8>; + }; +}; + +&cpu0 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_arm>; +}; + +&csi_dphy { + status =3D "okay"; +}; + +&display_subsystem { + status =3D "okay"; +}; + +&dsi_dphy { + status =3D "okay"; +}; + +&emmc { + bus-width =3D <8>; + cap-mmc-highspeed; + /* + * For hs200 support, U-Boot would have to set the RK809 DCDC4 + * rail to 1.8V from the default of 3.0V. It doesn't do that on + * devices out in the field, so disable hs200. + * mmc-hs200-1_8v; + */ + mmc-pwrseq =3D <&emmc_pwrseq>; + non-removable; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_emmc>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_log>; + status =3D "okay"; +}; + +/* I2C0 =3D PMIC, Touchscreen */ +&i2c0 { + status =3D "okay"; + + touchscreen@14 { + compatible =3D "goodix,gt911"; + reg =3D <0x14>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + irq-gpios =3D <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tch_int &tch_rst>; + reset-gpios =3D <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + AVDD28-supply =3D <&vcc_2v8>; + VDDIO-supply =3D <&vcc_3v3>; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + #clock-cells =3D <0>; + clock-output-names =3D "xin32k"; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + wakeup-source; + rockchip,system-power-controller; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc_3v3>; + vcc6-supply =3D <&vcc_3v3>; + vcc7-supply =3D <&vcc_3v3>; + vcc9-supply =3D <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name =3D "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name =3D "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0_1v8: vcc_emmc: DCDC_REG4 { + regulator-name =3D "vcc_3v0_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3000000>; + }; + }; + + vcc_3v3: DCDC_REG5 { + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc_1v0: LDO_REG3 { + regulator-name =3D "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + + vcc_2v8: LDO_REG4 { + regulator-name =3D "vcc_2v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <2800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3000000>; + }; + }; + + vcc_sdio: LDO_REG6 { + regulator-name =3D "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc_lcd: LDO_REG7 { + regulator-name =3D "vcc_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + + vcc_1v8_lcd: LDO_REG8 { + regulator-name =3D "vcc_1v8_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca_1v8: LDO_REG9 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +/* I2C2 =3D Accelerometer + Camera */ +&i2c2 { + /* MEMSIC MXC4005 accelerometer is rated for I2C Fast Mode (<=3D400KHz) */ + /* OmniVision OV5675 camera is rated for I2C Fast Mode (<=3D400KHz) */ + clock-frequency =3D <400000>; + status =3D "okay"; + + focus: focus@c { + compatible =3D "dongwoon,dw9714"; + reg =3D <0xc>; + vcc-supply =3D <&vcc_lens_afvdd>; + }; + + accel@15 { + compatible =3D "memsic,mxc4005"; + reg =3D <0x15>; + }; + + camera@36 { + compatible =3D "ovti,ov5675"; + reg =3D <0x36>; + clocks =3D <&cru SCLK_CIF_OUT>; + assigned-clocks =3D <&cru SCLK_CIF_OUT>; + assigned-clock-rates =3D <19200000>; + avdd-supply =3D <&vcc_cam_avdd>; + dvdd-supply =3D <&vcc_cam_dvdd>; + dovdd-supply =3D <&vcc_cam_dovdd>; + lens-focus =3D <&focus>; + orientation =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cif_clkout_m0 &cam_pwdn>; + reset-gpios =3D <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + rotation =3D <0>; + + port { + ucam_out: endpoint { + remote-endpoint =3D <&mipi_in_ucam>; + data-lanes =3D <1 2>; + link-frequencies =3D /bits/ 64 <450000000>; + }; + }; + }; +}; + +&io_domains { + vccio1-supply =3D <&vcc_sdio>; + vccio2-supply =3D <&vccio_sd>; + vccio3-supply =3D <&vcc_1v8>; + vccio4-supply =3D <&vcc_3v3>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_emmc>; + status =3D "okay"; +}; + +&isp { + status =3D "okay"; + + ports { + port@0 { + mipi_in_ucam: endpoint@0 { + reg =3D <0>; + data-lanes =3D <1 2>; + remote-endpoint =3D <&ucam_out>; + }; + }; + }; +}; + +&isp_mmu { + status =3D "okay"; +}; + +&pinctrl { + camera { + cam_afdd_en: cam-afdd-en { + rockchip,pins =3D + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_avdd_en: cam-avdd-en { + rockchip,pins =3D + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_dovdd_en: cam-dovdd-en { + rockchip,pins =3D + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_dvdd_en: cam-dvdd-en { + rockchip,pins =3D + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_pwdn: cam-pwdn { + rockchip,pins =3D + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins =3D + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + panel { + tch_int: tch-int { + rockchip,pins =3D + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + tch_rst: tch-rst { + rockchip,pins =3D + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + dsp_rst: dsp-rst { + rockchip,pins =3D + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins =3D + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc-slppin { + rockchip,pins =3D + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc-slppin-slp { + rockchip,pins =3D + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc-slppin-rst { + rockchip,pins =3D + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc_3v3>; + pmuio2-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&tsadc { + status =3D "okay"; +}; + +&u2phy { + status =3D "okay"; +}; + +&u2phy_host { + status =3D "okay"; +}; + +&u2phy_otg { + status =3D "okay"; +}; + +&uart5 { + pinctrl-0 =3D <&uart5_xfer>; + status =3D "okay"; +}; + +&usb20_otg { + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&vopb { + status =3D "okay"; +}; + +&vopb_mmu { + status =3D "okay"; +}; + +&wdt { + status =3D "okay"; +}; --=20 2.47.2