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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 8/9] x86/cpuid: Rename native_cpuid() to cpuid_native() Date: Thu, 8 May 2025 17:02:37 +0200 Message-ID: <20250508150240.172915-9-darwi@linutronix.de> In-Reply-To: <20250508150240.172915-1-darwi@linutronix.de> References: <20250508150240.172915-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to let all the APIs under have a shared "cpuid_" namespace, rename native_cpuid() to cpuid_native(). Adjust all call-sites accordingly. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish --- arch/x86/boot/compressed/sev.c | 6 +++--- arch/x86/include/asm/cpuid/api.h | 6 +++--- arch/x86/kernel/cpu/microcode/intel.c | 2 +- arch/x86/kernel/cpu/microcode/internal.h | 4 ++-- arch/x86/kernel/paravirt.c | 2 +- arch/x86/mm/mem_encrypt_identity.c | 6 +++--- arch/x86/xen/enlighten_pv.c | 4 ++-- 7 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index f054bf52c10a..4b617f8f9b7f 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -494,7 +494,7 @@ static int sev_check_cpu_support(void) /* Check for the SME/SEV support leaf */ eax =3D 0x80000000; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); if (eax < 0x8000001f) return -ENODEV; =20 @@ -508,7 +508,7 @@ static int sev_check_cpu_support(void) */ eax =3D 0x8000001f; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); /* Check whether SEV is supported */ if (!(eax & BIT(1))) return -ENODEV; @@ -666,7 +666,7 @@ bool early_is_sevsnp_guest(void) */ eax =3D 0x8000001f; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); if (eax & BIT(28)) { struct msr m; =20 diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index e957f09d8a8f..7f4644747649 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -22,7 +22,7 @@ static inline bool cpuid_feature(void) } #endif =20 -static inline void native_cpuid(u32 *eax, u32 *ebx, +static inline void cpuid_native(u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) { /* ecx is often an input as well as an output. */ @@ -40,7 +40,7 @@ static inline u32 native_cpuid_##reg(u32 op) \ { \ u32 eax =3D op, ebx, ecx =3D 0, edx; \ \ - native_cpuid(&eax, &ebx, &ecx, &edx); \ + cpuid_native(&eax, &ebx, &ecx, &edx); \ \ return reg; \ } @@ -56,7 +56,7 @@ NATIVE_CPUID_REG(edx) #ifdef CONFIG_PARAVIRT_XXL # include #else -# define __cpuid native_cpuid +# define __cpuid cpuid_native #endif =20 /* diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 819199bc0119..66693831f665 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -347,7 +347,7 @@ static __init bool load_builtin_intel_microcode(struct = cpio_data *cp) if (IS_ENABLED(CONFIG_X86_32)) return false; =20 - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); =20 sprintf(name, "intel-ucode/%02x-%02x-%02x", x86_family(eax), x86_model(eax), x86_stepping(eax)); diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu= /microcode/internal.h index 5df621752fef..6049fd7ac16a 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -73,7 +73,7 @@ static inline int x86_cpuid_vendor(void) u32 eax =3D 0x00000000; u32 ebx, ecx =3D 0, edx; =20 - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); =20 if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) return X86_VENDOR_INTEL; @@ -89,7 +89,7 @@ static inline unsigned int x86_cpuid_family(void) u32 eax =3D 0x00000001; u32 ebx, ecx =3D 0, edx; =20 - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); =20 return x86_family(eax); } diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 1ccd05d8999f..e2c812beb06c 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -122,7 +122,7 @@ struct paravirt_patch_template pv_ops =3D { .cpu.io_delay =3D native_io_delay, =20 #ifdef CONFIG_PARAVIRT_XXL - .cpu.cpuid =3D native_cpuid, + .cpu.cpuid =3D cpuid_native, .cpu.get_debugreg =3D pv_native_get_debugreg, .cpu.set_debugreg =3D pv_native_set_debugreg, .cpu.read_cr0 =3D native_read_cr0, diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_i= dentity.c index 5eecdd92da10..6bad28dd8b07 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -501,7 +501,7 @@ void __head sme_enable(struct boot_params *bp) /* Check for the SME/SEV support leaf */ eax =3D 0x80000000; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); if (eax < 0x8000001f) return; =20 @@ -518,7 +518,7 @@ void __head sme_enable(struct boot_params *bp) */ eax =3D 0x8000001f; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); /* Check whether SEV or SME is supported */ if (!(eax & (AMD_SEV_BIT | AMD_SME_BIT))) return; @@ -552,7 +552,7 @@ void __head sme_enable(struct boot_params *bp) */ eax =3D 1; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); if (ecx & BIT(31)) return; =20 diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 21c7f524766e..d1a1a3546bd5 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -327,7 +327,7 @@ static bool __init xen_check_mwait(void) ax =3D 1; cx =3D 0; =20 - native_cpuid(&ax, &bx, &cx, &dx); + cpuid_native(&ax, &bx, &cx, &dx); =20 mwait_mask =3D (1 << (X86_FEATURE_EST % 32)) | (1 << (X86_FEATURE_MWAIT % 32)); @@ -344,7 +344,7 @@ static bool __init xen_check_mwait(void) cx =3D 0; dx =3D 0; =20 - native_cpuid(&ax, &bx, &cx, &dx); + cpuid_native(&ax, &bx, &cx, &dx); =20 /* Ask the Hypervisor whether to clear ACPI_PROC_CAP_C_C2C3_FFH. If so, * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3. --=20 2.49.0