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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 6/9] x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter Date: Thu, 8 May 2025 17:02:35 +0200 Message-ID: <20250508150240.172915-7-darwi@linutronix.de> In-Reply-To: <20250508150240.172915-1-darwi@linutronix.de> References: <20250508150240.172915-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CPUID(0x2) descriptors iterator has been renamed from: for_each_leaf_0x2_entry() to: for_each_cpuid_0x2_desc() since it iterates over CPUID(0x2) cache and TLB "descriptors", not "entries". In the macro's x86/cacheinfo call-site, rename the parameter denoting the parsed descriptor at each iteration from 'entry' to 'desc'. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index b6349c1792dd..adfa7e8bb865 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -381,7 +381,7 @@ static void intel_cacheinfo_done(struct cpuinfo_x86 *c,= unsigned int l3, static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) { unsigned int l1i =3D 0, l1d =3D 0, l2 =3D 0, l3 =3D 0; - const struct leaf_0x2_table *entry; + const struct leaf_0x2_table *desc; union leaf_0x2_regs regs; u8 *ptr; =20 @@ -389,12 +389,12 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) return; =20 cpuid_leaf_0x2(®s); - for_each_cpuid_0x2_desc(regs, ptr, entry) { - switch (entry->c_type) { - case CACHE_L1_INST: l1i +=3D entry->c_size; break; - case CACHE_L1_DATA: l1d +=3D entry->c_size; break; - case CACHE_L2: l2 +=3D entry->c_size; break; - case CACHE_L3: l3 +=3D entry->c_size; break; + for_each_cpuid_0x2_desc(regs, ptr, desc) { + switch (desc->c_type) { + case CACHE_L1_INST: l1i +=3D desc->c_size; break; + case CACHE_L1_DATA: l1d +=3D desc->c_size; break; + case CACHE_L2: l2 +=3D desc->c_size; break; + case CACHE_L3: l3 +=3D desc->c_size; break; } } =20 --=20 2.49.0