From nobody Tue Dec 16 07:27:38 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 576DA2797AE for ; Thu, 8 May 2025 15:02:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716570; cv=none; b=fVNgbLEjWCkzsBsSDdXhWelZm5PG70oArlqqn8rGurthxhC0imyBRgqIB0JROgpIz/YpzynbeMhJKFVSBxd5dwcAXlhDZ/2j6hbrcgRFYT/qX3+Bsnutxpa02ytst/sZzs0TpjDH+rQVuc8WSsi7epriO4Yyo/Q3EBwyEcZoWgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716570; c=relaxed/simple; bh=Av8ETro96thT4uWT57XyQ4plbzhxSuQwb4JgRF1q7Ao=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mPZV6EOZ+YVgES/2Yhh28EEoKnZVoebhcfq98ePswEFRARejZohOuBmx1CmrMmBeCT6F5Io6eN77JN2qxvL5NqS8HIbRKPaqHn4e/wmMjrzNLdEZ8E8+xO8Wctu1rcvP9JdVcVJhuQozj8Dtb96Gx6GYQWwxK9PY4fz4TQ4D6S8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Q8+aFH6n; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=zyWsFM1f; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Q8+aFH6n"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="zyWsFM1f" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1746716565; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ouXdEehDoqV1+SFbkKragQQWfw01WTv03V9ySvkqWns=; b=Q8+aFH6nT/Lb2b6lOV5TJsvAK8G4DhygUmqpSOKEHVDc3yy60nUS0ebt4ZS+ZR0TCBXIF7 PZNR+jbtna+NxolBmiS+jGQgLSafH988938lXi1x0E2RcVY03DwkvLr6zS8PEYWMenjpcC 3OnkqEgZfPGF7yHjrT2Qi8DZjG+c5IfHfd1ELLjexpJhFXlkyF9TLJfrIPauiPl1TS78Eu 9Xkar+AVdnUWww9PjKiS9O8KRgttzV6dapflxgRdRx8UimfAX+OPJUieGi8IxYJPeTodsv 6IeiaD3wfeEJu8eJ7sd4KqXUHt4uAmC7R94eLqV+UxMYwZnSpVjNV1uU77psbA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1746716565; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ouXdEehDoqV1+SFbkKragQQWfw01WTv03V9ySvkqWns=; b=zyWsFM1fgBbYLJ3YoOzXbosF0thD0QjSxmxVwDaRxBSnydxjL+pEbbRf1Gjbq7NC5g+Ak8 C4WaSRFSbE1LyfCg== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 1/9] x86/cpuid: Move CPUID(0x2) APIs into Date: Thu, 8 May 2025 17:02:30 +0200 Message-ID: <20250508150240.172915-2-darwi@linutronix.de> In-Reply-To: <20250508150240.172915-1-darwi@linutronix.de> References: <20250508150240.172915-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move all of the CPUID(0x2) APIs at into , in order centralize all CPUID APIs into the latter. While at it, separate the different CPUID leaf parsing APIs using header comments like "CPUID(0xN) parsing: ". Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid.h | 1 - arch/x86/include/asm/cpuid/api.h | 75 ++++++++++++++++++++++- arch/x86/include/asm/cpuid/leaf_0x2_api.h | 73 ---------------------- arch/x86/include/asm/cpuid/types.h | 3 +- 4 files changed, 75 insertions(+), 77 deletions(-) delete mode 100644 arch/x86/include/asm/cpuid/leaf_0x2_api.h diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h index 585819331dc6..d5749b25fa10 100644 --- a/arch/x86/include/asm/cpuid.h +++ b/arch/x86/include/asm/cpuid.h @@ -4,6 +4,5 @@ #define _ASM_X86_CPUID_H =20 #include -#include =20 #endif /* _ASM_X86_CPUID_H */ diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index bf76a1706d02..ff8891a0b6c8 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -160,6 +160,10 @@ static inline void __cpuid_read_reg(u32 leaf, u32 subl= eaf, __cpuid_read_reg(leaf, 0, regidx, (u32 *)(reg)); \ } =20 +/* + * Hypervisor-related APIs: + */ + static __always_inline bool cpuid_function_is_indexed(u32 function) { switch (function) { @@ -208,7 +212,76 @@ static inline u32 hypervisor_cpuid_base(const char *si= g, u32 leaves) } =20 /* - * CPUID(0x80000006) parsing helpers + * CPUID(0x2) parsing: + */ + +/** + * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output + * @regs: Output parameter + * + * Query CPUID leaf 0x2 and store its output in @regs. Force set any + * invalid 1-byte descriptor returned by the hardware to zero (the NULL + * cache/TLB descriptor) before returning it to the caller. + * + * Use for_each_leaf_0x2_entry() to iterate over the register output in + * parsed form. + */ +static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs) +{ + cpuid_leaf(0x2, regs); + + /* + * All Intel CPUs must report an iteration count of 1. In case + * of bogus hardware, treat all returned descriptors as NULL. + */ + if (regs->desc[0] !=3D 0x01) { + for (int i =3D 0; i < 4; i++) + regs->regv[i] =3D 0; + return; + } + + /* + * The most significant bit (MSB) of each register must be clear. + * If a register is invalid, replace its descriptors with NULL. + */ + for (int i =3D 0; i < 4; i++) { + if (regs->reg[i].invalid) + regs->regv[i] =3D 0; + } +} + +/** + * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors + * @regs: Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs() + * @__ptr: u8 pointer, for macro internal use only + * @entry: Pointer to parsed descriptor information at each iteration + * + * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers + * @regs. Provide the parsed information for each descriptor through @ent= ry. + * + * To handle cache-specific descriptors, switch on @entry->c_type. For TLB + * descriptors, switch on @entry->t_type. + * + * Example usage for cache descriptors:: + * + * const struct leaf_0x2_table *entry; + * union leaf_0x2_regs regs; + * u8 *ptr; + * + * cpuid_get_leaf_0x2_regs(®s); + * for_each_leaf_0x2_entry(regs, ptr, entry) { + * switch (entry->c_type) { + * ... + * } + * } + */ +#define for_each_leaf_0x2_entry(regs, __ptr, entry) \ + for (__ptr =3D &(regs).desc[1]; \ + __ptr < &(regs).desc[16] && (entry =3D &cpuid_0x2_table[*__ptr]); \ + __ptr++) + +/* + * CPUID(0x80000006) parsing: */ =20 static inline bool cpuid_amd_hygon_has_l3_cache(void) diff --git a/arch/x86/include/asm/cpuid/leaf_0x2_api.h b/arch/x86/include/a= sm/cpuid/leaf_0x2_api.h deleted file mode 100644 index 09fa3070b271..000000000000 --- a/arch/x86/include/asm/cpuid/leaf_0x2_api.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_X86_CPUID_LEAF_0x2_API_H -#define _ASM_X86_CPUID_LEAF_0x2_API_H - -#include -#include - -/** - * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output - * @regs: Output parameter - * - * Query CPUID leaf 0x2 and store its output in @regs. Force set any - * invalid 1-byte descriptor returned by the hardware to zero (the NULL - * cache/TLB descriptor) before returning it to the caller. - * - * Use for_each_leaf_0x2_entry() to iterate over the register output in - * parsed form. - */ -static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs) -{ - cpuid_leaf(0x2, regs); - - /* - * All Intel CPUs must report an iteration count of 1. In case - * of bogus hardware, treat all returned descriptors as NULL. - */ - if (regs->desc[0] !=3D 0x01) { - for (int i =3D 0; i < 4; i++) - regs->regv[i] =3D 0; - return; - } - - /* - * The most significant bit (MSB) of each register must be clear. - * If a register is invalid, replace its descriptors with NULL. - */ - for (int i =3D 0; i < 4; i++) { - if (regs->reg[i].invalid) - regs->regv[i] =3D 0; - } -} - -/** - * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors - * @regs: Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs() - * @__ptr: u8 pointer, for macro internal use only - * @entry: Pointer to parsed descriptor information at each iteration - * - * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers - * @regs. Provide the parsed information for each descriptor through @ent= ry. - * - * To handle cache-specific descriptors, switch on @entry->c_type. For TLB - * descriptors, switch on @entry->t_type. - * - * Example usage for cache descriptors:: - * - * const struct leaf_0x2_table *entry; - * union leaf_0x2_regs regs; - * u8 *ptr; - * - * cpuid_get_leaf_0x2_regs(®s); - * for_each_leaf_0x2_entry(regs, ptr, entry) { - * switch (entry->c_type) { - * ... - * } - * } - */ -#define for_each_leaf_0x2_entry(regs, __ptr, entry) \ - for (__ptr =3D &(regs).desc[1]; \ - __ptr < &(regs).desc[16] && (entry =3D &cpuid_0x2_table[*__ptr]); \ - __ptr++) - -#endif /* _ASM_X86_CPUID_LEAF_0x2_API_H */ diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index c95fee66e148..8a00364b79de 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -31,8 +31,7 @@ enum cpuid_regs_idx { #define CPUID_LEAF_TILE 0x1d =20 /* - * Types for CPUID(0x2) parsing - * Check + * Types for CPUID(0x2) parsing: */ =20 struct leaf_0x2_reg { --=20 2.49.0 From nobody Tue Dec 16 07:27:38 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 876142798F5 for ; Thu, 8 May 2025 15:02:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716571; cv=none; b=ZYFbP3FNXgy4ydSjzSq8kHy5cyl/tuWfHrPlmAEJYo2/qPTcMTIEhfGnGEjVXECETQXBu+ixoxBnSQYGm2MOSTNA/nTR07xdVzCRVkIR+Ib8vLXuXTo/Jw3FXqt+6BArmjaisCh4+FvLVNcI8dqc0PeOqB4LR1Q1H6E+pfpnzaw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716571; c=relaxed/simple; bh=KwRSLfvjHxj87pOjqUvVy5lfQX5BcaHXeYfDA5C4/Eg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mhW15ezXyHvl4q8H8x5J4kbRxBaIzzYaRdm2gqnsIuiCoU1cMsMWq7ZQRdfG1xoKJfK41zHgFpKbJM4Kdu3/74+Q92ZLwy6mgSJLqbdJJkmcRqakIbnbRo4MySQxttttSIf5JdMyNvrW/QU0wKsYyFDjfVTE2rjq08y5tlFvdb0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0xVzj8EJ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=e7Ha5cwy; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0xVzj8EJ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="e7Ha5cwy" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 2/9] x86/cpuid: Set as the main CPUID header Date: Thu, 8 May 2025 17:02:31 +0200 Message-ID: <20250508150240.172915-3-darwi@linutronix.de> In-Reply-To: <20250508150240.172915-1-darwi@linutronix.de> References: <20250508150240.172915-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The main CPUID header was originally a storefront for the headers: Now that the latter CPUID(0x2) header has been merged into the former, there is no practical difference between and Remove and let all call-sites directly include . Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish --- arch/x86/boot/compressed/sev.c | 2 +- arch/x86/coco/sev/core.c | 2 +- arch/x86/events/intel/pt.c | 2 +- arch/x86/include/asm/cpuid.h | 8 -------- arch/x86/include/asm/processor.h | 2 +- arch/x86/kernel/acpi/cstate.c | 2 +- arch/x86/kernel/amd_nb.c | 2 +- arch/x86/kernel/cpu/cacheinfo.c | 2 +- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/cpu/intel.c | 2 +- arch/x86/kernel/fpu/xstate.c | 2 +- arch/x86/kernel/hpet.c | 2 +- arch/x86/kernel/process.c | 2 +- arch/x86/kernel/smpboot.c | 2 +- arch/x86/kernel/tsc.c | 2 +- arch/x86/kvm/cpuid.c | 2 +- arch/x86/virt/svm/sev.c | 2 +- arch/x86/xen/enlighten_pv.c | 2 +- drivers/acpi/acpi_pad.c | 2 +- drivers/dma/ioat/dca.c | 2 +- drivers/idle/intel_idle.c | 2 +- drivers/platform/x86/intel/pmc/core.c | 2 +- sound/soc/intel/avs/tgl.c | 2 +- 23 files changed, 22 insertions(+), 30 deletions(-) delete mode 100644 arch/x86/include/asm/cpuid.h diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 0003e4416efd..f054bf52c10a 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include =20 #include "error.h" #include "../msr.h" diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index b0c1a7a57497..836fc4ce37d0 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -41,7 +41,7 @@ #include #include #include -#include +#include #include =20 #define DR7_RESET_VALUE 0x400 diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index fa37565f6418..5ec16f31b904 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -18,7 +18,7 @@ #include #include =20 -#include +#include #include #include #include diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h deleted file mode 100644 index d5749b25fa10..000000000000 --- a/arch/x86/include/asm/cpuid.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _ASM_X86_CPUID_H -#define _ASM_X86_CPUID_H - -#include - -#endif /* _ASM_X86_CPUID_H */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 5d2f7e5aff26..f639df061f09 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -16,7 +16,7 @@ struct vm86; #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index d5ac34186555..8698d66563ed 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -14,7 +14,7 @@ =20 #include #include -#include +#include #include #include #include diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index ffaad175cee2..cb4de00c36e7 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -15,7 +15,7 @@ #include =20 #include -#include +#include =20 static u32 *flush_words; =20 diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index f866d94352fb..6d61f7dff9e7 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index e5734df3b4a1..9f0f6dcb2f7d 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -29,7 +29,7 @@ =20 #include #include -#include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index a6493f60b3f2..ade5557dd3f8 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 6a41d1610d8b..d67636806c8d 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -20,7 +20,7 @@ #include #include =20 -#include +#include #include #include #include diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 7f4b2966e15c..e786664b735f 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -7,7 +7,7 @@ #include #include =20 -#include +#include #include #include #include diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 962c3ce39323..6e2f494472ae 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index d6cf1e23c2a3..d7d61b3de2bf 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -64,7 +64,7 @@ =20 #include #include -#include +#include #include #include #include diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 88e5a4ed9db3..56a1b7c5cf4e 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -16,7 +16,7 @@ #include #include =20 -#include +#include #include #include #include diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 571c906ffcbf..7f43d8d24fbe 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include "cpuid.h" #include "lapic.h" #include "mmu.h" diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c index fc473ca12c44..10a78a98e2dd 100644 --- a/arch/x86/virt/svm/sev.c +++ b/arch/x86/virt/svm/sev.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include =20 diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 846b5737d320..21c7f524766e 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -49,7 +49,7 @@ #include #include =20 -#include +#include #include #include #include diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c index 3fde4496f8a2..6f8bbe1247a5 100644 --- a/drivers/acpi/acpi_pad.c +++ b/drivers/acpi/acpi_pad.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include =20 diff --git a/drivers/dma/ioat/dca.c b/drivers/dma/ioat/dca.c index c9aba2304de7..5d3c0ae6b342 100644 --- a/drivers/dma/ioat/dca.c +++ b/drivers/dma/ioat/dca.c @@ -10,7 +10,7 @@ #include #include =20 -#include +#include =20 /* either a kernel change is needed, or we need something like this in ker= nel */ #ifndef CONFIG_SMP diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index 976f5be54e36..d0b94dbc0835 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -51,7 +51,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index 7a1d11f2914f..492c7b672bd7 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -22,7 +22,7 @@ #include #include =20 -#include +#include #include #include #include diff --git a/sound/soc/intel/avs/tgl.c b/sound/soc/intel/avs/tgl.c index 56905f2b9eb2..9dbb3ad0954a 100644 --- a/sound/soc/intel/avs/tgl.c +++ b/sound/soc/intel/avs/tgl.c @@ -47,7 +47,7 @@ static int avs_tgl_config_basefw(struct avs_dev *adev) #ifdef CONFIG_X86 unsigned int ecx; =20 -#include +#include ecx =3D cpuid_ecx(CPUID_TSC_LEAF); if (ecx) { ret =3D avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(e= cx), &ecx); --=20 2.49.0 From nobody Tue Dec 16 07:27:38 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F8EF27A11C for ; Thu, 8 May 2025 15:02:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716574; cv=none; b=HDYrguXcmMvc2U6KUurPY8JayLvGEk88pEVkcqG7Nj6KWKQL/9hmnAzllxzxZSy+Rdft4NmpoUb7u7yjz9YMMoXUicpQ/TlVvhIpAdWb64+raf5QiAkIWzv9xzIXPp992H1xWwo+84YRwruKMNZiqRLv6l5kh9z9zGfirQek01w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716574; c=relaxed/simple; bh=aZgW/tnKgyRU98N/yvDYngoeVYGERyea23wmk8q1bS0=; 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 3/9] x86/cpuid: Rename have_cpuid_p() to cpuid_feature() Date: Thu, 8 May 2025 17:02:32 +0200 Message-ID: <20250508150240.172915-4-darwi@linutronix.de> In-Reply-To: <20250508150240.172915-1-darwi@linutronix.de> References: <20250508150240.172915-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to let all the APIs under have a shared "cpuid_" namespace, rename have_cpuid_p() to cpuid_feature(). Adjust all call-sites accordingly. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 4 ++-- arch/x86/kernel/cpu/common.c | 10 +++++----- arch/x86/kernel/cpu/microcode/core.c | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index ff8891a0b6c8..c0211fcdc706 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -14,9 +14,9 @@ */ =20 #ifdef CONFIG_X86_32 -bool have_cpuid_p(void); +bool cpuid_feature(void); #else -static inline bool have_cpuid_p(void) +static inline bool cpuid_feature(void) { return true; } diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9f0f6dcb2f7d..def7af1dbd55 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -321,7 +321,7 @@ static int __init cachesize_setup(char *str) __setup("cachesize=3D", cachesize_setup); =20 /* Probe for the CPUID instruction */ -bool have_cpuid_p(void) +bool cpuid_feature(void) { return flag_is_changeable_p(X86_EFLAGS_ID); } @@ -1626,11 +1626,11 @@ static void __init early_identify_cpu(struct cpuinf= o_x86 *c) memset(&c->x86_capability, 0, sizeof(c->x86_capability)); c->extended_cpuid_level =3D 0; =20 - if (!have_cpuid_p()) + if (!cpuid_feature()) identify_cpu_without_cpuid(c); =20 /* cyrix could have cpuid enabled via c_identify()*/ - if (have_cpuid_p()) { + if (cpuid_feature()) { cpu_detect(c); get_cpu_vendor(c); intel_unlock_cpuid_leafs(c); @@ -1790,11 +1790,11 @@ static void generic_identify(struct cpuinfo_x86 *c) { c->extended_cpuid_level =3D 0; =20 - if (!have_cpuid_p()) + if (!cpuid_feature()) identify_cpu_without_cpuid(c); =20 /* cyrix could have cpuid enabled via c_identify()*/ - if (!have_cpuid_p()) + if (!cpuid_feature()) return; =20 cpu_detect(c); diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index b3658d11e7b6..1395fa72960f 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -125,7 +125,7 @@ void __init load_ucode_bsp(void) unsigned int cpuid_1_eax; bool intel =3D true; =20 - if (!have_cpuid_p()) + if (!cpuid_feature()) return; =20 cpuid_1_eax =3D native_cpuid_eax(1); --=20 2.49.0 From nobody Tue Dec 16 07:27:38 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B3BA27A13C for ; Thu, 8 May 2025 15:02:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716576; cv=none; b=eDB7nxCDTGyM8q8+ZBiicyJkPdj7Tm1gxz4JN5Fm2YSk/F4MT7M0VGl3ZXRHR46lOEb1x65Qpxg6kNB32rqZJGv8PtSriuVBw6Ft1zOvbrbPPyHOpGCZuO4cKqnZuh1bkO2OcufNqu/5M0yKuNV2LmLRfIw13wAyU9HCBp8sC5w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716576; c=relaxed/simple; bh=pLyBLISA1jVCwKlxy/h9Ji+QDPDETT7+/UIMCqqCApU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r+AQa/50CimN2S2TdKju3HcdssAyaSJzkTOYgz7aglf8ln/JIhEQqYs2AXWVVFX0nVYn1LzVIn75IRP18eIJKw7E7usdnHS17nL1KqKmGtzqY1xtgmDOz4nG531j75HPkoLtfgw8OKjGV/4J0s41fwC2zpRBl0BwdKb10thgeZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=eNcd90Rb; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=MaqB2Xkz; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="eNcd90Rb"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="MaqB2Xkz" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 4/9] x86/cpuid: Rename hypervisor_cpuid_base() to cpuid_hypervisor_base() Date: Thu, 8 May 2025 17:02:33 +0200 Message-ID: <20250508150240.172915-5-darwi@linutronix.de> In-Reply-To: <20250508150240.172915-1-darwi@linutronix.de> References: <20250508150240.172915-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to let all the APIs under have a shared "cpuid_" namespace, rename hypervisor_cpuid_base() to cpuid_hypervisor_base(). To align with the new style, also rename: for_each_possible_hypervisor_cpuid_base(function) to: for_each_possible_cpuid_hypervisor_base(function) Adjust all call-sites accordingly. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/acrn.h | 2 +- arch/x86/include/asm/cpuid/api.h | 6 +++--- arch/x86/include/asm/xen/hypervisor.h | 2 +- arch/x86/kernel/jailhouse.c | 2 +- arch/x86/kernel/kvm.c | 2 +- arch/x86/kvm/cpuid.c | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/acrn.h b/arch/x86/include/asm/acrn.h index 1dd14381bcb6..b509c622e6f4 100644 --- a/arch/x86/include/asm/acrn.h +++ b/arch/x86/include/asm/acrn.h @@ -25,7 +25,7 @@ void acrn_remove_intr_handler(void); static inline u32 acrn_cpuid_base(void) { if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) - return hypervisor_cpuid_base("ACRNACRNACRN", 0); + return cpuid_hypervisor_base("ACRNACRNACRN", 0); =20 return 0; } diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index c0211fcdc706..0e4b53306e99 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -188,14 +188,14 @@ static __always_inline bool cpuid_function_is_indexed= (u32 function) return false; } =20 -#define for_each_possible_hypervisor_cpuid_base(function) \ +#define for_each_possible_cpuid_hypervisor_base(function) \ for (function =3D 0x40000000; function < 0x40010000; function +=3D 0x100) =20 -static inline u32 hypervisor_cpuid_base(const char *sig, u32 leaves) +static inline u32 cpuid_hypervisor_base(const char *sig, u32 leaves) { u32 base, eax, signature[3]; =20 - for_each_possible_hypervisor_cpuid_base(base) { + for_each_possible_cpuid_hypervisor_base(base) { cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); =20 /* diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/x= en/hypervisor.h index bd0fc69a10a7..09b15a0e2d2e 100644 --- a/arch/x86/include/asm/xen/hypervisor.h +++ b/arch/x86/include/asm/xen/hypervisor.h @@ -43,7 +43,7 @@ extern struct start_info *xen_start_info; =20 static inline uint32_t xen_cpuid_base(void) { - return hypervisor_cpuid_base(XEN_SIGNATURE, 2); + return cpuid_hypervisor_base(XEN_SIGNATURE, 2); } =20 struct pci_dev; diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c index cd8ed1edbf9e..07da72de80ba 100644 --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -49,7 +49,7 @@ static uint32_t jailhouse_cpuid_base(void) !boot_cpu_has(X86_FEATURE_HYPERVISOR)) return 0; =20 - return hypervisor_cpuid_base("Jailhouse\0\0\0", 0); + return cpuid_hypervisor_base("Jailhouse\0\0\0", 0); } =20 static uint32_t __init jailhouse_detect(void) diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 3be9b3342c67..35d3d2803c57 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -874,7 +874,7 @@ static noinline uint32_t __kvm_cpuid_base(void) return 0; /* So we don't blow up on old processors */ =20 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) - return hypervisor_cpuid_base(KVM_SIGNATURE, 0); + return cpuid_hypervisor_base(KVM_SIGNATURE, 0); =20 return 0; } diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 7f43d8d24fbe..d153719302a2 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -236,7 +236,7 @@ static struct kvm_hypervisor_cpuid kvm_get_hypervisor_c= puid(struct kvm_vcpu *vcp struct kvm_cpuid_entry2 *entry; u32 base; =20 - for_each_possible_hypervisor_cpuid_base(base) { + for_each_possible_cpuid_hypervisor_base(base) { entry =3D kvm_find_cpuid_entry(vcpu, base); =20 if (entry) { --=20 2.49.0 From nobody Tue Dec 16 07:27:38 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 471EE27A90F for ; Thu, 8 May 2025 15:02:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716579; cv=none; b=GA6/KfnTQXRD0C4YwEh13o6PWxyEQPyk6CLodWki674l0eJquTvVX3kNimHUV9nmrxvY18d08SoH8Rs/WG7CLS+4YbVGk4p+RUeP+/1TQaI+zoZNsGQ3gWTFeVoC4ijAwgy8p+SJZY6FybD7Nn9+BCsexD/uSceooTth8FEx9tI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716579; c=relaxed/simple; bh=3PYcpfwLxTEKFv/bxLMLmifenYAM9sHe53k0E2HOZiM=; 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 5/9] x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2() Date: Thu, 8 May 2025 17:02:34 +0200 Message-ID: <20250508150240.172915-6-darwi@linutronix.de> In-Reply-To: <20250508150240.172915-1-darwi@linutronix.de> References: <20250508150240.172915-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename the CPUID(0x2) register accessor function: cpuid_get_leaf_0x2_regs(regs) to: cpuid_leaf_0x2(regs) for consistency with other accessors that return full CPUID registers outputs like: cpuid_leaf(regs) cpuid_subleaf(regs) In the same vein, rename the CPUID(0x2) iteration macro: for_each_leaf_0x2_entry() to: for_each_cpuid_0x2_desc() to include "cpuid" in the macro name, and since what is iterated upon is CPUID(0x2) cache and TLB "descriptos", not "entries". Prefix an underscore to that iterator macro parameters, so that the newly renamed 'desc' parameter do not get mixed with "union leaf_0x2_regs :: desc[]" in the macro's implementation. Adjust all the affected call-sites accordingly. While at it, use "CPUID(0x2)" instead of "CPUID leaf 0x2" as this is the recommended style. References: 62e565273993 ("x86/cacheinfo: Standardize header files and CPUI= D references") References: 718f9038acc5 ("x86/cpuid: Remove obsolete CPUID(0x2) iteration = macro") Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 34 ++++++++++++++++---------------- arch/x86/kernel/cpu/cacheinfo.c | 4 ++-- arch/x86/kernel/cpu/intel.c | 4 ++-- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 0e4b53306e99..e957f09d8a8f 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -216,17 +216,17 @@ static inline u32 cpuid_hypervisor_base(const char *s= ig, u32 leaves) */ =20 /** - * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output + * cpuid_leaf_0x2() - Return sanitized CPUID(0x2) register output * @regs: Output parameter * - * Query CPUID leaf 0x2 and store its output in @regs. Force set any + * Query CPUID(0x2) and store its output in @regs. Force set any * invalid 1-byte descriptor returned by the hardware to zero (the NULL * cache/TLB descriptor) before returning it to the caller. * - * Use for_each_leaf_0x2_entry() to iterate over the register output in + * Use for_each_cpuid_0x2_desc() to iterate over the register output in * parsed form. */ -static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs) +static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs) { cpuid_leaf(0x2, regs); =20 @@ -251,34 +251,34 @@ static inline void cpuid_get_leaf_0x2_regs(union leaf= _0x2_regs *regs) } =20 /** - * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors - * @regs: Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs() + * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors + * @regs: CPUID(0x2) register output, as returned by cpuid_leaf_0x2() * @__ptr: u8 pointer, for macro internal use only - * @entry: Pointer to parsed descriptor information at each iteration + * @desc: Pointer to parsed CPUID(0x2) descriptor at each iteration * - * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers - * @regs. Provide the parsed information for each descriptor through @ent= ry. + * Loop over the 1-byte descriptors in the passed CPUID(0x2) output regist= ers + * @regs. Provide the parsed information for each descriptor through @des= c. * * To handle cache-specific descriptors, switch on @entry->c_type. For TLB * descriptors, switch on @entry->t_type. * * Example usage for cache descriptors:: * - * const struct leaf_0x2_table *entry; + * const struct leaf_0x2_table *desc; * union leaf_0x2_regs regs; * u8 *ptr; * - * cpuid_get_leaf_0x2_regs(®s); - * for_each_leaf_0x2_entry(regs, ptr, entry) { - * switch (entry->c_type) { + * cpuid_leaf_0x2(®s); + * for_each_cpuid_0x2_desc(regs, ptr, desc) { + * switch (desc->c_type) { * ... * } * } */ -#define for_each_leaf_0x2_entry(regs, __ptr, entry) \ - for (__ptr =3D &(regs).desc[1]; \ - __ptr < &(regs).desc[16] && (entry =3D &cpuid_0x2_table[*__ptr]); \ - __ptr++) +#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \ + for (_ptr =3D &(_regs).desc[1]; \ + _ptr < &(_regs).desc[16] && (_desc =3D &cpuid_0x2_table[*_ptr]); \ + _ptr++) =20 /* * CPUID(0x80000006) parsing: diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 6d61f7dff9e7..b6349c1792dd 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -388,8 +388,8 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) if (c->cpuid_level < 2) return; =20 - cpuid_get_leaf_0x2_regs(®s); - for_each_leaf_0x2_entry(regs, ptr, entry) { + cpuid_leaf_0x2(®s); + for_each_cpuid_0x2_desc(regs, ptr, entry) { switch (entry->c_type) { case CACHE_L1_INST: l1i +=3D entry->c_size; break; case CACHE_L1_DATA: l1d +=3D entry->c_size; break; diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index ade5557dd3f8..d4efca7e4bd6 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -716,8 +716,8 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c) if (c->cpuid_level < 2) return; =20 - cpuid_get_leaf_0x2_regs(®s); - for_each_leaf_0x2_entry(regs, ptr, entry) + cpuid_leaf_0x2(®s); + for_each_cpuid_0x2_desc(regs, ptr, entry) intel_tlb_lookup(entry); } =20 --=20 2.49.0 From nobody Tue Dec 16 07:27:38 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3264227A93D for ; Thu, 8 May 2025 15:02:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716581; cv=none; b=r1yj+GT58Cxtze2SjXlPe8/PxnEsWUoyQz0UM2ZV/rotUNGri19qVMbz2+RPINddk0bzmT7wL09RJypxVPw/g5jHYScYOVO0MD9TV9e7nQbZeQSL1INosWNRzRJ8RozVN49Iz3mA/duWsJlHxuGcGIDcXSZbc1T4zaCvur+qd8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716581; c=relaxed/simple; bh=GzgoW8PqrF03rDB8xf2iF8PrYFL/CLMquTZ3aRxEwmk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=T7n/11NLuOWot+FWYZrNNIvZf+07EcGKeJthfThmmWPFN35B6ErTAW3WoN//dSt1iRfOMdiTAnLHKtvsSTQTzZdKQV1gtFhkQeoVP2yq8FOvLms4eRfH3CwpVPf39KQZkkCT1Kc3xdXH9Z/8bEbjRWMKVwObQ/0UlWgRJpLvZtA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=VYa2QzvQ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=HYw4GLgd; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="VYa2QzvQ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="HYw4GLgd" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 6/9] x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter Date: Thu, 8 May 2025 17:02:35 +0200 Message-ID: <20250508150240.172915-7-darwi@linutronix.de> In-Reply-To: <20250508150240.172915-1-darwi@linutronix.de> References: <20250508150240.172915-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CPUID(0x2) descriptors iterator has been renamed from: for_each_leaf_0x2_entry() to: for_each_cpuid_0x2_desc() since it iterates over CPUID(0x2) cache and TLB "descriptors", not "entries". In the macro's x86/cacheinfo call-site, rename the parameter denoting the parsed descriptor at each iteration from 'entry' to 'desc'. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index b6349c1792dd..adfa7e8bb865 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -381,7 +381,7 @@ static void intel_cacheinfo_done(struct cpuinfo_x86 *c,= unsigned int l3, static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) { unsigned int l1i =3D 0, l1d =3D 0, l2 =3D 0, l3 =3D 0; - const struct leaf_0x2_table *entry; + const struct leaf_0x2_table *desc; union leaf_0x2_regs regs; u8 *ptr; =20 @@ -389,12 +389,12 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) return; =20 cpuid_leaf_0x2(®s); - for_each_cpuid_0x2_desc(regs, ptr, entry) { - switch (entry->c_type) { - case CACHE_L1_INST: l1i +=3D entry->c_size; break; - case CACHE_L1_DATA: l1d +=3D entry->c_size; break; - case CACHE_L2: l2 +=3D entry->c_size; break; - case CACHE_L3: l3 +=3D entry->c_size; break; + for_each_cpuid_0x2_desc(regs, ptr, desc) { + switch (desc->c_type) { + case CACHE_L1_INST: l1i +=3D desc->c_size; break; + case CACHE_L1_DATA: l1d +=3D desc->c_size; break; + case CACHE_L2: l2 +=3D desc->c_size; break; + case CACHE_L3: l3 +=3D desc->c_size; break; } } =20 --=20 2.49.0 From nobody Tue Dec 16 07:27:38 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68E7C27AC5A for ; Thu, 8 May 2025 15:03:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716584; cv=none; b=tf1CZhR5Nsga4q+ddjregn+avJsgBgr+21eL4R18YWwS8XLTTAxOL0+l+9Ik2l4zT6XmVon/nrA6WCVkEoLeChwgjKxgQqe4h15UlQ5R6b++40Z/II3W+bdBNsaDUJOuKBA6D9YB6chlbG9+BP9Y0mrvisKWKgntaCH1a/7IW2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716584; c=relaxed/simple; bh=9AHgtL8RG7TPRu1Y6JSuPxMQpmSKTLNx3uaNOw+XK10=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QRCeZdpGvsueyjmbbyhLnpX4O8mrsIav2n6Pmm6x8pFyzel6ZV0J6Vh9wDfKH9aTctxSHBKdbi3S7lJA9uc7O3HAlJhuTrI1qlxoXm3zLMghGQ5rs5E202LxgRFPP88EpP3LhRatiOhc3ICvYkwjWpyEKf09RQqduJ/2JaOQOeo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=WgC8lVG6; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cg8vMZze; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="WgC8lVG6"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cg8vMZze" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 7/9] x86/cpu: Rename CPUID(0x2) descriptors iterator parameter Date: Thu, 8 May 2025 17:02:36 +0200 Message-ID: <20250508150240.172915-8-darwi@linutronix.de> In-Reply-To: <20250508150240.172915-1-darwi@linutronix.de> References: <20250508150240.172915-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CPUID(0x2) descriptors iterator has been renamed from: for_each_leaf_0x2_entry() to: for_each_cpuid_0x2_desc() since it iterates over CPUID(0x2) cache and TLB "descriptors", not "entries". In the macro's x86/cpu call-site, rename the parameter denoting the parsed descriptor at each iteration from 'entry' to 'desc'. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/intel.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index d4efca7e4bd6..cfcf9b3d270f 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -648,11 +648,11 @@ static unsigned int intel_size_cache(struct cpuinfo_x= 86 *c, unsigned int size) } #endif =20 -static void intel_tlb_lookup(const struct leaf_0x2_table *entry) +static void intel_tlb_lookup(const struct leaf_0x2_table *desc) { - short entries =3D entry->entries; + short entries =3D desc->entries; =20 - switch (entry->t_type) { + switch (desc->t_type) { case STLB_4K: tlb_lli_4k =3D max(tlb_lli_4k, entries); tlb_lld_4k =3D max(tlb_lld_4k, entries); @@ -709,7 +709,7 @@ static void intel_tlb_lookup(const struct leaf_0x2_tabl= e *entry) =20 static void intel_detect_tlb(struct cpuinfo_x86 *c) { - const struct leaf_0x2_table *entry; + const struct leaf_0x2_table *desc; union leaf_0x2_regs regs; u8 *ptr; =20 @@ -717,8 +717,8 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c) return; =20 cpuid_leaf_0x2(®s); - for_each_cpuid_0x2_desc(regs, ptr, entry) - intel_tlb_lookup(entry); + for_each_cpuid_0x2_desc(regs, ptr, desc) + intel_tlb_lookup(desc); } =20 static const struct cpu_dev intel_cpu_dev =3D { --=20 2.49.0 From nobody Tue Dec 16 07:27:38 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11DFB27B516 for ; Thu, 8 May 2025 15:03:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716586; cv=none; b=cKNZzlxX54pbuFts5Y/8WIA3J+Iw40u2jsIQjbrDyh/5NA4w8n5P3foU5MhS53ZoPxkzoXmifQAK86GSH+xp5GN61XQIyNfa6XJQAThhygAGwvsQ0+KEW8R+xPOQNFPXgoHiLKSOwa9bIMTXvDa2O33O/usrYzFeAa8U3i+89FI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746716586; c=relaxed/simple; bh=GVTfeGKHrkRu8eLI3uK43e70/CgAu2MN5heww0lN6nk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ksSjnMOjWiQub/9eZEXM37B9QPFbdOOyUVumUghAyrGI2JAsdUWOS5xIEczbEAwLbxYvRS+njWZvh63jECSeGPUxhA7WfR0SiIWbPrOoCmddApUmpC3bVzLPPTj/OjVIsdnD60Zy1L9R7vRiYQoYZkbU/O8czv3FLmLIqnIFjSs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Y+T3sffs; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=w4/IGnJi; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Y+T3sffs"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="w4/IGnJi" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1746716583; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WMuqN7CQJKVFh5Qod0h7zRKR2zJsoYZx0+h+Dl9/l9Y=; b=Y+T3sffsK6pGcrECFfFJ5hOYO0HzYneMkDtsq6QfpFSTwmWVnc1ADqmwHhKzd8FBHY0jRi 05DA5YsawAH86prndhESAuTYUZ3WLvY18nODU8fPFaXSfMpqmEDbSEF034M7TK6Uomz9XT I6y7vVPs2acVzyoOfNvD9Vd+xp/H0j7whFQdaA24jK3X5ISRA6iXkvg1amzwsJjQimtRrj km/Y4bLVLTcXHbbYCz61CSze6ANeVKBTFjxGXYnmBqAccZWjnpSydcGr3Bq+UX2LLs3GwA ye28GDB9sDtvMJBSRRTDX7h0TjdkTxEk1blAgtFwWvP53ywfSIr7+PgMWKQvbQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1746716583; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WMuqN7CQJKVFh5Qod0h7zRKR2zJsoYZx0+h+Dl9/l9Y=; b=w4/IGnJi+IT1L44wocBxfE6OCnwR1/1pMeNMwwRRfAc5pz84hhpcRD7GrlrkHGISlPIl8h KQmzLzkp4WEhfNBw== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 8/9] x86/cpuid: Rename native_cpuid() to cpuid_native() Date: Thu, 8 May 2025 17:02:37 +0200 Message-ID: <20250508150240.172915-9-darwi@linutronix.de> In-Reply-To: <20250508150240.172915-1-darwi@linutronix.de> References: <20250508150240.172915-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to let all the APIs under have a shared "cpuid_" namespace, rename native_cpuid() to cpuid_native(). Adjust all call-sites accordingly. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish --- arch/x86/boot/compressed/sev.c | 6 +++--- arch/x86/include/asm/cpuid/api.h | 6 +++--- arch/x86/kernel/cpu/microcode/intel.c | 2 +- arch/x86/kernel/cpu/microcode/internal.h | 4 ++-- arch/x86/kernel/paravirt.c | 2 +- arch/x86/mm/mem_encrypt_identity.c | 6 +++--- arch/x86/xen/enlighten_pv.c | 4 ++-- 7 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index f054bf52c10a..4b617f8f9b7f 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -494,7 +494,7 @@ static int sev_check_cpu_support(void) /* Check for the SME/SEV support leaf */ eax =3D 0x80000000; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); if (eax < 0x8000001f) return -ENODEV; =20 @@ -508,7 +508,7 @@ static int sev_check_cpu_support(void) */ eax =3D 0x8000001f; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); /* Check whether SEV is supported */ if (!(eax & BIT(1))) return -ENODEV; @@ -666,7 +666,7 @@ bool early_is_sevsnp_guest(void) */ eax =3D 0x8000001f; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); if (eax & BIT(28)) { struct msr m; =20 diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index e957f09d8a8f..7f4644747649 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -22,7 +22,7 @@ static inline bool cpuid_feature(void) } #endif =20 -static inline void native_cpuid(u32 *eax, u32 *ebx, +static inline void cpuid_native(u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) { /* ecx is often an input as well as an output. */ @@ -40,7 +40,7 @@ static inline u32 native_cpuid_##reg(u32 op) \ { \ u32 eax =3D op, ebx, ecx =3D 0, edx; \ \ - native_cpuid(&eax, &ebx, &ecx, &edx); \ + cpuid_native(&eax, &ebx, &ecx, &edx); \ \ return reg; \ } @@ -56,7 +56,7 @@ NATIVE_CPUID_REG(edx) #ifdef CONFIG_PARAVIRT_XXL # include #else -# define __cpuid native_cpuid +# define __cpuid cpuid_native #endif =20 /* diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 819199bc0119..66693831f665 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -347,7 +347,7 @@ static __init bool load_builtin_intel_microcode(struct = cpio_data *cp) if (IS_ENABLED(CONFIG_X86_32)) return false; =20 - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); =20 sprintf(name, "intel-ucode/%02x-%02x-%02x", x86_family(eax), x86_model(eax), x86_stepping(eax)); diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu= /microcode/internal.h index 5df621752fef..6049fd7ac16a 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -73,7 +73,7 @@ static inline int x86_cpuid_vendor(void) u32 eax =3D 0x00000000; u32 ebx, ecx =3D 0, edx; =20 - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); =20 if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) return X86_VENDOR_INTEL; @@ -89,7 +89,7 @@ static inline unsigned int x86_cpuid_family(void) u32 eax =3D 0x00000001; u32 ebx, ecx =3D 0, edx; =20 - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); =20 return x86_family(eax); } diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 1ccd05d8999f..e2c812beb06c 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -122,7 +122,7 @@ struct paravirt_patch_template pv_ops =3D { .cpu.io_delay =3D native_io_delay, =20 #ifdef CONFIG_PARAVIRT_XXL - .cpu.cpuid =3D native_cpuid, + .cpu.cpuid =3D cpuid_native, .cpu.get_debugreg =3D pv_native_get_debugreg, .cpu.set_debugreg =3D pv_native_set_debugreg, .cpu.read_cr0 =3D native_read_cr0, diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_i= dentity.c index 5eecdd92da10..6bad28dd8b07 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -501,7 +501,7 @@ void __head sme_enable(struct boot_params *bp) /* Check for the SME/SEV support leaf */ eax =3D 0x80000000; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); if (eax < 0x8000001f) return; =20 @@ -518,7 +518,7 @@ void __head sme_enable(struct boot_params *bp) */ eax =3D 0x8000001f; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); /* Check whether SEV or SME is supported */ if (!(eax & (AMD_SEV_BIT | AMD_SME_BIT))) return; @@ -552,7 +552,7 @@ void __head sme_enable(struct boot_params *bp) */ eax =3D 1; ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); + cpuid_native(&eax, &ebx, &ecx, &edx); if (ecx & BIT(31)) return; =20 diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 21c7f524766e..d1a1a3546bd5 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -327,7 +327,7 @@ static bool __init xen_check_mwait(void) ax =3D 1; cx =3D 0; =20 - native_cpuid(&ax, &bx, &cx, &dx); + cpuid_native(&ax, &bx, &cx, &dx); =20 mwait_mask =3D (1 << (X86_FEATURE_EST % 32)) | (1 << (X86_FEATURE_MWAIT % 32)); @@ -344,7 +344,7 @@ static bool __init xen_check_mwait(void) cx =3D 0; dx =3D 0; =20 - native_cpuid(&ax, &bx, &cx, &dx); + cpuid_native(&ax, &bx, &cx, &dx); =20 /* Ask the Hypervisor whether to clear ACPI_PROC_CAP_C_C2C3_FFH. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 9/9] x86/cpuid: Rename native_cpuid_REG() to cpuid_native_REG() Date: Thu, 8 May 2025 17:02:38 +0200 Message-ID: <20250508150240.172915-10-darwi@linutronix.de> In-Reply-To: <20250508150240.172915-1-darwi@linutronix.de> References: <20250508150240.172915-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to let all the APIs under have a shared "cpuid_" namespace, rename native_cpuid_REG() to cpuid_native_REG(). To beetter align with the new namespace, also rename the internal NATIVE_CPUID_REG() macro to __CPUID_NATIVE_REG(). Adjust all call-sites accordingly. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish --- arch/x86/boot/compressed/pgtable_64.c | 4 ++-- arch/x86/include/asm/cpuid/api.h | 12 ++++++------ arch/x86/include/asm/microcode.h | 2 +- arch/x86/kernel/cpu/microcode/amd.c | 2 +- arch/x86/kernel/cpu/microcode/core.c | 6 +++--- arch/x86/kernel/head32.c | 2 +- drivers/firmware/efi/libstub/x86-5lvl.c | 4 ++-- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compress= ed/pgtable_64.c index d8c5de40669d..8cfe50988aa2 100644 --- a/arch/x86/boot/compressed/pgtable_64.c +++ b/arch/x86/boot/compressed/pgtable_64.c @@ -125,8 +125,8 @@ asmlinkage void configure_5level_paging(struct boot_par= ams *bp, void *pgtable) */ if (IS_ENABLED(CONFIG_X86_5LEVEL) && !cmdline_find_option_bool("no5lvl") && - native_cpuid_eax(0) >=3D 7 && - (native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) { + cpuid_native_eax(0) >=3D 7 && + (cpuid_native_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) { l5_required =3D true; =20 /* Initialize variables for 5-level paging */ diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 7f4644747649..9f8a1176ad86 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -35,8 +35,8 @@ static inline void cpuid_native(u32 *eax, u32 *ebx, : "memory"); } =20 -#define NATIVE_CPUID_REG(reg) \ -static inline u32 native_cpuid_##reg(u32 op) \ +#define __CPUID_NATIVE_REG(reg) \ +static inline u32 cpuid_native_##reg(u32 op) \ { \ u32 eax =3D op, ebx, ecx =3D 0, edx; \ \ @@ -48,10 +48,10 @@ static inline u32 native_cpuid_##reg(u32 op) \ /* * Native CPUID functions returning a single datum: */ -NATIVE_CPUID_REG(eax) -NATIVE_CPUID_REG(ebx) -NATIVE_CPUID_REG(ecx) -NATIVE_CPUID_REG(edx) +__CPUID_NATIVE_REG(eax) +__CPUID_NATIVE_REG(ebx) +__CPUID_NATIVE_REG(ecx) +__CPUID_NATIVE_REG(edx) =20 #ifdef CONFIG_PARAVIRT_XXL # include diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microc= ode.h index 695e569159c1..755c9f693118 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -64,7 +64,7 @@ static inline u32 intel_get_microcode_revision(void) native_wrmsrl(MSR_IA32_UCODE_REV, 0); =20 /* As documented in the SDM: Do a CPUID 1 here */ - native_cpuid_eax(1); + cpuid_native_eax(1); =20 /* get the current revision from MSR 0x8B */ native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/micr= ocode/amd.c index 4a10d35e70aa..d757383b653c 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -1098,7 +1098,7 @@ static enum ucode_state load_microcode_amd(u8 family,= const u8 *data, size_t siz =20 static int __init save_microcode_in_initrd(void) { - unsigned int cpuid_1_eax =3D native_cpuid_eax(1); + unsigned int cpuid_1_eax =3D cpuid_native_eax(1); struct cpuinfo_x86 *c =3D &boot_cpu_data; struct cont_desc desc =3D { 0 }; enum ucode_state ret; diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 1395fa72960f..9924b8238492 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -106,7 +106,7 @@ static bool __init check_loader_disabled_bsp(void) * completely accurate as xen pv guests don't see that CPUID bit set but * that's good enough as they don't land on the BSP path anyway. */ - if (native_cpuid_ecx(1) & BIT(31)) + if (cpuid_native_ecx(1) & BIT(31)) return true; =20 if (x86_cpuid_vendor() =3D=3D X86_VENDOR_AMD) { @@ -128,7 +128,7 @@ void __init load_ucode_bsp(void) if (!cpuid_feature()) return; =20 - cpuid_1_eax =3D native_cpuid_eax(1); + cpuid_1_eax =3D cpuid_native_eax(1); =20 switch (x86_cpuid_vendor()) { case X86_VENDOR_INTEL: @@ -162,7 +162,7 @@ void load_ucode_ap(void) if (dis_ucode_ldr) return; =20 - cpuid_1_eax =3D native_cpuid_eax(1); + cpuid_1_eax =3D cpuid_native_eax(1); =20 switch (x86_cpuid_vendor()) { case X86_VENDOR_INTEL: diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c index de001b2146ab..43aa1cfc1b65 100644 --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -146,7 +146,7 @@ void __init __no_stack_protector mk_early_pgtbl_32(void) =20 #ifdef CONFIG_MICROCODE_INITRD32 /* Running on a hypervisor? */ - if (native_cpuid_ecx(1) & BIT(31)) + if (cpuid_native_ecx(1) & BIT(31)) return; =20 params =3D (struct boot_params *)__pa_nodebug(&boot_params); diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi= /libstub/x86-5lvl.c index 77359e802181..db347c91edb3 100644 --- a/drivers/firmware/efi/libstub/x86-5lvl.c +++ b/drivers/firmware/efi/libstub/x86-5lvl.c @@ -34,8 +34,8 @@ efi_status_t efi_setup_5level_paging(void) return EFI_SUCCESS; =20 /* check for 5 level paging support */ - if (native_cpuid_eax(0) < 7 || - !(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) + if (cpuid_native_eax(0) < 7 || + !(cpuid_native_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) return EFI_SUCCESS; =20 /* allocate some 32-bit addressable memory for code and a page table */ --=20 2.49.0