From nobody Tue Dec 16 07:31:46 2025 Received: from bayard.4d2.org (bayard.4d2.org [155.254.16.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24C531F37D3; Thu, 8 May 2025 11:17:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=155.254.16.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746703044; cv=none; b=jHs9m4fiPDbXriAJXQCt8lndnWheIDQMzaQlcMymjDoJrXOLOiGg+DekytaFbZT62a40oy3j6a32ch2vCvAJi1NUPNMFlH8wD0URE4pB21y5evshvb+q8Hmts0+qV43FC29DNGkJoDVlKEyuXmhiYBDOloCcur5XlPk2ZDqHqjk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746703044; c=relaxed/simple; bh=mm+CgjLs+rS3CPxZ9/r7vxj50BUPBgnFChiiDX6Gy/s=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=P/wbnnU16sgPskbmCgtku5rPtBuSMKWKZIm3b7RbqtnpB0G+wW/lL3B9W8fQ+lKDF9PZEXN6rWmZZ9QZRLHUL1KJMlYsF8zPH1cGtvd65j7SGSZv+JFcLUmAglZiHFlFd1yOezingAG3XxYIejiW3gJUpfBFhXoXGOy90kNphVs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=4d2.org; spf=pass smtp.mailfrom=4d2.org; dkim=pass (2048-bit key) header.d=4d2.org header.i=@4d2.org header.b=Ry3d5bWe; dkim=pass (2048-bit key) header.d=4d2.org header.i=@4d2.org header.b=Vm8iKbXq; arc=none smtp.client-ip=155.254.16.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=4d2.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=4d2.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=4d2.org header.i=@4d2.org header.b="Ry3d5bWe"; dkim=pass (2048-bit key) header.d=4d2.org header.i=@4d2.org header.b="Vm8iKbXq" Received: from bayard.4d2.org (bayard.4d2.org [127.0.0.1]) by bayard.4d2.org (Postfix) with ESMTP id 2983712FB439; Thu, 08 May 2025 04:17:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=4d2.org; s=mail; t=1746703039; bh=mm+CgjLs+rS3CPxZ9/r7vxj50BUPBgnFChiiDX6Gy/s=; h=From:To:Cc:Subject:Date:From; b=Ry3d5bWea+7xauZVZ7ybL5zSOz7/4fJvWBShpHx5mgLg9qDH7mXQSZmvG7gU8RUvv 3fP15KZxSGIdmRxajfgWhr19kZTmaCj4lbeGqNruqg5fzBheMkJBjygI2gFEwoPHZx bzsPhYLvwgrzBj0yKwUAOC+lMXeaLUX7IropKU9sFoxuo4ZheJrmO7UTA+GYYAWWUJ b2Wy0N49WVxuQNi3iRaLeDMbY4Q9orCCWUX3U5XhXcRwIYVltOv+aQVyePhu8xbibd BryUGRZAmf0VB7XdENQdYX8TnA0oBywpv7sI0ALne702UltzRKLHQZ7C4ZO9PdT38H LiH4sDxRWYgFg== X-Virus-Scanned: amavisd-new at 4d2.org Authentication-Results: bayard.4d2.org (amavisd-new); dkim=pass (2048-bit key) header.d=4d2.org Received: from bayard.4d2.org ([127.0.0.1]) by bayard.4d2.org (bayard.4d2.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dQzszsTujUZg; Thu, 8 May 2025 04:16:43 -0700 (PDT) Received: from localhost.localdomain (unknown [183.217.82.204]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) (Authenticated sender: heylenay@4d2.org) by bayard.4d2.org (Postfix) with ESMTPSA id BC78712FB404; Thu, 08 May 2025 04:16:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=4d2.org; s=mail; t=1746703003; bh=mm+CgjLs+rS3CPxZ9/r7vxj50BUPBgnFChiiDX6Gy/s=; h=From:To:Cc:Subject:Date:From; b=Vm8iKbXqVO8iIBwHm42a6OkEWN0tug+I8+ACFnx3/SCcwRI1azQqo3d99inSTlBBm 9MdpWKLO7VMHinZlA5yezaHI0cvYGP0DrIH8jfZlKbgNeU7MGA0cWH7qSR+d/UztEH DcCDmgvebzSAzCjr1SRz9Ag7WB7Tdi4cjYkHRdJ5ZSTDkRTLPHZfQ8teLm7nAT/Yr3 5Rw/PVNuqWGfzc4yDeOoP6CkZaMHMYX/C+YkK6OcvAxeBbsTifV071Z4olDY+Sn8uW O+SatnDWAvS0WwBMKkJ8bt6J8VdIvg+5GH6n3+rvakThmtJ+u7LLMjJYA1oCgougb4 rFNFF2FlK5eeA== From: Haylen Chu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Haylen Chu , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, Inochi Amaoto , Chen Wang , Jisheng Zhang , Meng Zhang , Haylen Chu , Alex Elder Subject: [PATCH v9] riscv: dts: spacemit: Add clock tree for SpacemiT K1 Date: Thu, 8 May 2025 11:15:29 +0000 Message-ID: <20250508111528.10508-2-heylenay@4d2.org> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describe the PLL and system controllers that're capable of generating clock signals in the devicetree. Signed-off-by: Haylen Chu Reviewed-by: Alex Elder Reviewed-by: Yixun Lan --- This originates the 5th patch from previous "Add clock controller support for SpacemiT K1" series[1] with node names of system controllers and PLL reworked[2]. The patch is based on linux-spacemit/k1/clk-for-6.16. Yixun, please drop the previous version and pick this patch instead. Thanks for your work! [1]: https://lore.kernel.org/spacemit/20250416135406.16284-1-heylenay@4d2.o= rg/ [2]: https://lore.kernel.org/spacemit/aBxF81yqPgHP5oA_@ketchup/ arch/riscv/boot/dts/spacemit/k1.dtsi | 75 ++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index c670ebf8fa12..85c9730dd082 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2024 Yangyu Chen */ =20 +#include + /dts-v1/; / { #address-cells =3D <2>; @@ -306,6 +308,36 @@ cluster1_l2_cache: l2-cache1 { }; }; =20 + clocks { + vctcxo_1m: clock-1m { + compatible =3D "fixed-clock"; + clock-frequency =3D <1000000>; + clock-output-names =3D "vctcxo_1m"; + #clock-cells =3D <0>; + }; + + vctcxo_24m: clock-24m { + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + clock-output-names =3D "vctcxo_24m"; + #clock-cells =3D <0>; + }; + + vctcxo_3m: clock-3m { + compatible =3D "fixed-clock"; + clock-frequency =3D <3000000>; + clock-output-names =3D "vctcxo_3m"; + #clock-cells =3D <0>; + }; + + osc_32k: clock-32k { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + clock-output-names =3D "osc_32k"; + #clock-cells =3D <0>; + }; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -314,6 +346,17 @@ soc { dma-noncoherent; ranges; =20 + syscon_apbc: system-controller@d4015000 { + compatible =3D "spacemit,k1-syscon-apbc"; + reg =3D <0x0 0xd4015000 0x0 0x1000>; + clocks =3D <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, + <&vctcxo_24m>; + clock-names =3D "osc", "vctcxo_1m", "vctcxo_3m", + "vctcxo_24m"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + uart0: serial@d4017000 { compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; reg =3D <0x0 0xd4017000 0x0 0x100>; @@ -409,6 +452,38 @@ pinctrl: pinctrl@d401e000 { reg =3D <0x0 0xd401e000 0x0 0x400>; }; =20 + syscon_mpmu: system-controller@d4050000 { + compatible =3D "spacemit,k1-syscon-mpmu"; + reg =3D <0x0 0xd4050000 0x0 0x209c>; + clocks =3D <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, + <&vctcxo_24m>; + clock-names =3D "osc", "vctcxo_1m", "vctcxo_3m", + "vctcxo_24m"; + #clock-cells =3D <1>; + #power-domain-cells =3D <1>; + #reset-cells =3D <1>; + }; + + pll: clock-controller@d4090000 { + compatible =3D "spacemit,k1-pll"; + reg =3D <0x0 0xd4090000 0x0 0x1000>; + clocks =3D <&vctcxo_24m>; + spacemit,mpmu =3D <&syscon_mpmu>; + #clock-cells =3D <1>; + }; + + syscon_apmu: system-controller@d4282800 { + compatible =3D "spacemit,k1-syscon-apmu"; + reg =3D <0x0 0xd4282800 0x0 0x400>; + clocks =3D <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, + <&vctcxo_24m>; + clock-names =3D "osc", "vctcxo_1m", "vctcxo_3m", + "vctcxo_24m"; + #clock-cells =3D <1>; + #power-domain-cells =3D <1>; + #reset-cells =3D <1>; + }; + plic: interrupt-controller@e0000000 { compatible =3D "spacemit,k1-plic", "sifive,plic-1.0.0"; reg =3D <0x0 0xe0000000 0x0 0x4000000>; --=20 2.49.0