From nobody Mon Feb 9 19:38:10 2026 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C0B0265CA3; Thu, 8 May 2025 09:15:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746695719; cv=none; b=F5Ebzl+vxfvZhslE01T1tOBRxA6OR5GEkrx1Bs74jMSyGTgRd9vvwtOen/pQvwE6fuu4DbukdQcQxAyuA//14GOll60+bBJJ1KcUE3sfXCbUv58MAAGuc8GNLhc681slq6+qN2gWnT5XayS0lfoDLj36QZqBtzyYKebn7avgFE4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746695719; c=relaxed/simple; bh=1A9CY0H/kYTojtxll//4SQPbJ+jWznvduyifJPT4qpI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nzEefIdbi9jzKlH7plZUsX4EiXKBsByjWbkXxn8CM9Ec6GdM4ieFQ96rUdvzR/pAnI5+oLuR9DscTePUiz6VK1e12jm31Mjo0pfxWF82iEefI4gkSbY55OUbwW4vpWQz46ivEAOBPcJZyOyXxasrckCuizs2ZRH9K0EtwEFrMpc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=IDTusWEu; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="IDTusWEu" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5489ExD91055013 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 8 May 2025 04:14:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746695699; bh=2nB2XrYs3/yr4cfRNXfAXTu6rjkWvNQLgoMjODS48vE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IDTusWEuI4yZ0J3mnyTZFDRbJ9FtimfNiCbcVW0PJYuFaSVfmIb6i8a8mFb+KhW/P QFs2uzt4pEWYQmb30vN5kWBw7mUpDRp9G1LSuSLTT3MiDX+3g5Y8UuvwO1tsBJKx7S fy3bVJgNcTWEzDfnyc2tnQoSJK23TOei+zmjvkhI= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5489ExFq092212 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 May 2025 04:14:59 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 May 2025 04:14:58 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 May 2025 04:14:58 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5489Ew2S110344; Thu, 8 May 2025 04:14:58 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , Subject: [PATCH v3 2/3] arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs Date: Thu, 8 May 2025 14:44:21 +0530 Message-ID: <20250508091422.288876-3-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250508091422.288876-1-p-bhagat@ti.com> References: <20250508091422.288876-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Update k3-pinctrl file to include pin definitions for AM62D2 family of SoCs. Signed-off-by: Paresh Bhagat --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index cac7cccc1112..0cf57179c974 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -63,6 +63,9 @@ #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 +#define AM62DX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) +#define AM62DX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) + #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 --=20 2.34.1