From nobody Sun Dec 14 23:24:49 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95532235C17 for ; Thu, 8 May 2025 08:23:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746692604; cv=none; b=q+TypEltmiRhp0fHQ3fwl0bWwDb/uVKnfXDCSY9GTxyKtUhdw3CZW2vNPMYNeJMvK4UN1m4AUokfb1xBWIdpHBm3YAIFXlR3C2usn57cwbsFwYBCNxjXuL6JZlQ1wwpB4DJ5gsENXEY9jY5FB4TsX7e1cvpbRBhKxGoaSZFwBYk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746692604; c=relaxed/simple; bh=euZ0Zj5ymVvdjh/3qOybPwtuZ+o3GzvdIi2/M+/nE94=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=lFVDQzge2dMJ4kvrBLvpNaGWdR7pgNOyXY0WVd6CDwrdgkoRc5FCoQR6WeQc6CwuwXkdccx939Ex1sPdIdg0Ols9RPknbMSBnCla/crvHCCTsuyBvHmdEfKnMLl2KjBoiahh4dn7Coz7FTKoiPnvYWuZ66zb15Xtt1hS9846BLw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Ewp6mIq2; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Ewp6mIq2" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-43d2d952eb1so4469515e9.1 for ; Thu, 08 May 2025 01:23:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1746692601; x=1747297401; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vh7Nh/LNhUg5Xl+qiW1/QFk8dwafIYEiWF4enwv0UK4=; b=Ewp6mIq2i/Q7EGITDRKE/mFxgnjZwnAXvGayCTL+yxOpGTzCcbQm8omRNXLCdwH0zB h8aNMzsjOVpj6xAqPGo5WPh3E5bTOJEqyN+CWFQk/llV3o/JSMGbJzhDIhqfIh6eSewm orTGR+GPAxgpzV7arn5HuHx8JiBAqHV793BbT6tVgSGblwQ4yxKq5ZDXZ0Ql2EHzJ/c4 RWp/EzDkkn5tPgTpCRkNaDYQ28FGT+t9UHlLf8FoyEjy8+6PoD9dfovXZ6shUeVKO+bx /cZKYXiLjeLWrx14sciqVQ2+AzZ3TSadmPnX8LTWkmnqFrdC6YcBdwQc0XQgen7mxk8g A9RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746692601; x=1747297401; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vh7Nh/LNhUg5Xl+qiW1/QFk8dwafIYEiWF4enwv0UK4=; b=a0gKatnmtLn6jUfTB4499nMqQSrtlnv1wB8gleXMoOjDK8QOoF0y8dC8XwlqlO82rf jXVlFr+7If/8/06IJffBhWCzhXn1B2MMO/UUS3GeWjbl1kimP94EZArDEFNBbOIweJdM TXRpMvp+Ukz523OMJMorq8Gohn6IWtYg02nRIcyjDCR41v7HYvtNbPNXmVVRg3H3cx7Y sl3k7827jyUId0sIsaG/0bfFL07dr/ua1o5wROKwJBkeU+DVLVHYQLWjCTkD25nJ5mXj cky8VJkCJvXHTytxLHBJBs8+sysWG2lt1zLdw9Gj5CW0Bk/YnkeN7Uhishg4e9L/O4Zb P3PA== X-Forwarded-Encrypted: i=1; AJvYcCVORcBfMdFdlofjSJfRcFnzzq10jMVuplbVWDH32WNWuoJaCmsAGSyC0V5dvw4jhcF23iYL9GC12jWVRDQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yx2KKCioqNsCLOoKd9fAnAU8tUOfYkHsCA/GJG5LhUu37Zy25WN Bo5r5YngC0DqG7CqeGZOEC78fE9zGNqIuDN8Axvg1ILlBkJlY1JN1J+nKbTO9aM= X-Gm-Gg: ASbGncuU2SleLDbYcEDw8lIPHPR8NJpU2J3LE1snptN5mjjtJgAUcYPSxJ9ka3LoQl5 ubThKttRJUitS+K3wHREK2DUmU5knLAlBBN9knlMzpFDJ51Z950BRtHhbFrThz/ivA9XBbxq5j9 xX+ZCl4Gn1JreI+bOtria7XSH0nlbUekwqBP9tzcNUAbv3u2DzEBXnAaAPx+HOxiCCYLsaA5D1n dVDDkn0ier9v/TxYwhbEboIOXsgL4k+H4Q20SCHm732RmIE7/A+Zl5qRmkguE2P5QiTH+WgpWrg DSgMcxIQpT9Hg0H3Jv5wSLuw6+ONOQMYQoLZUH4KiprxAchVfVx+l5qORkaxTg== X-Google-Smtp-Source: AGHT+IEaepCUF0s1jaV8f2x9+3A/ICFXfGBKrXbBRgf8EnrZFcBImB0rnl0HY1gtvoGRDu1Jbp/ttg== X-Received: by 2002:a05:600c:4e16:b0:43b:c5a3:2e1a with SMTP id 5b1f17b1804b1-441d44bb815mr54224835e9.2.1746692600740; Thu, 08 May 2025 01:23:20 -0700 (PDT) Received: from alex-rivos.lan ([2001:861:3382:ef90:e3eb:2939:f761:f7f1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd32f331sm28697035e9.13.2025.05.08.01.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 01:23:20 -0700 (PDT) From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: Alexandre Ghiti , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Jones Subject: [PATCH v2 1/3] riscv: Fix typo EXRACT -> EXTRACT Date: Thu, 8 May 2025 10:22:13 +0200 Message-Id: <20250508082215.88658-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250508082215.88658-1-alexghiti@rivosinc.com> References: <20250508082215.88658-1-alexghiti@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Simply fix a typo. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jones Signed-off-by: Alexandre Ghiti --- arch/riscv/include/asm/insn.h | 2 +- arch/riscv/kernel/vector.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index 09fde95a5e8f..2a589a58b291 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -352,7 +352,7 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 co= de) ({typeof(x) x_ =3D (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \ RVFDQ_FL_FS_WIDTH_MASK); }) =20 -#define RVV_EXRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x) +#define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x) =20 /* * Get the immediate from a J-type instruction. diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 184f780c932d..901e67adf576 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -93,7 +93,7 @@ bool insn_is_vector(u32 insn_buf) return true; case RVV_OPCODE_VL: case RVV_OPCODE_VS: - width =3D RVV_EXRACT_VL_VS_WIDTH(insn_buf); + width =3D RVV_EXTRACT_VL_VS_WIDTH(insn_buf); if (width =3D=3D RVV_VL_VS_WIDTH_8 || width =3D=3D RVV_VL_VS_WIDTH_16 || width =3D=3D RVV_VL_VS_WIDTH_32 || width =3D=3D RVV_VL_VS_WIDTH_64) return true; --=20 2.39.2 From nobody Sun Dec 14 23:24:49 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C595E238C3D for ; Thu, 8 May 2025 08:24:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746692665; cv=none; b=cdQFNBckyU/ZdsU/1FISQy0X6rhoqW8wqwq8ojzSF0BSGY7jWBvyN4jvC9GJikWjm/pJ6FdB7spB58UCLZopmLXxLjU9n1uWU4y9FoR+cX0/j+46HTZANDXC8KHwGnT6YzAq3eespYRE6der890GZAi2qVEF8l6mGaMtxQxwqQI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746692665; c=relaxed/simple; bh=F1Tpw/FDQiobHbn1ogwM1Y/7MZIw2LV9VxrfdFmVGHY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MIl7IS8ghXIlDrTfIKMCy83uhb8MGrFdiN//SzwRCakN7vIqvxqoqRk7ZEHiSg4nECPAbbNh/RrhD5XaWqGaUzUbQbE/9JDG3iV2XxDtW+GzqUBXOiHccDhq8wL+zadYDp8+RuRIKrV5bnNXwoOow7qBo4VYGf/zMzOjyDZzPT4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=gfZWW6CM; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="gfZWW6CM" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-43cf05f0c3eso4162635e9.0 for ; Thu, 08 May 2025 01:24:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1746692662; x=1747297462; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OuPapDRP/OJYb/JxVpYS+I7DwtI999Hhv/OzI9C3VrY=; b=gfZWW6CMpFvS/a6H1xQ4Jxa0qylEN75T7X406mNd+UYmqOxNsQxbQokup2g3q4fgMS SQ1Rgv3s0Po7keqHii9d0KUObi10UQrSwqMHVRYARcb/+r9Ge1o4agyNr29zhrJuX6Jy nC2bl8rqX2BVLT4qwDOU1svJGOtSzlcyfCJJejL/7bm9voHv7BOi/OGqUXqDd8I9+wD0 RHmi5sWc5RjABn+6d5Sj9b4M8blPwd31qeNXy5xvAGGnCFQ0mu6q+pptLuW0jOeK8jro nwU+/EZwFzmAhNTGvv933XWzGmBhARjkCILRN/nfGRe+nEPoEqfLLJnzEnnO2vIpUY4L ldiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746692662; x=1747297462; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OuPapDRP/OJYb/JxVpYS+I7DwtI999Hhv/OzI9C3VrY=; b=KpPPx+sB5CXiRknY7G424cGs3w6jIvfINvDHVlRT52lXaH0X0LsJ0FyqP8uoxwYdNs meakPtVeCsDQLsy2s8rzmVptjBEGmX7wDISPGkvkYz8mGiqoewCloghvcK21gPlN7bjc rHJAi6N2zqceZOfp+nNvR75SNxNYEgbZv5anaI8B1ja3GWGPYXpQKqhoeXfmd08Iz54t NR3nh5EJNky8snUV0DZ+LA5497I1OK8Ngz3pWIVlK+7k+Spdo7M0zBj6XfENkYbQfDl6 WP7+4wq4bnOZ4ybxdXf1k0b6cERLNkk/GCgxTdpGW7ngJQkCQtz+1hHfV/p9Ac/f2RMa 9CAQ== X-Forwarded-Encrypted: i=1; AJvYcCXH66ZLgiDp6v+4cXMQUjxwssIvsEBwogIKDm4McAE8nlmT+aBQlj/4OqMiNqJRvr7AFzXOPhN1YsjMo7k=@vger.kernel.org X-Gm-Message-State: AOJu0YzRdcbcRlmeDQOQb7fShmMTWT/hWcOvNDmqvKgMcpc5ExEuUxjs WLEtK93ThniFhGORBE9K9JyATWYlaxE3WTkqMQc4ndNRmSYI3nT3j96oSU1X5Tw= X-Gm-Gg: ASbGncu7VWhYbbo1ag2fFIKII2ok8hDDY/kN4eihWDcFbczgvMOZKxBxwyxjbqg2CkB pQYMjeP3i6a6uPX3iPku0ATkLo3/lss4CRUvkHYrNp2nEIiacWuKIjjqO+9ZqxKuHsatt3Ak00O VCoOgRzyFrlTqjpr2Uxvw3fGiETIwNeRbxIcy2Uv+Urcoai90TOPPNIB88BJRKh9fbQzaWa4y5h uRirXNmbMg+SU/d/gM4Rb8S4HIgcd+XD+OQWdatnup35x7tk+Ic/ZSRHQYGjv4FP8HP9EAXWkC1 TMoTzrouwMycfrfsOLT1uKlAV+xWAdPLabNhHPESLCs90r9PW+U= X-Google-Smtp-Source: AGHT+IEnEvDZVvyjWPKnOAG4dlx+tDzdySwIdn8aIF4iBX0NclzVjAzc6QAKF5pKumGu5cZ4Nhx5mw== X-Received: by 2002:a05:600c:1c93:b0:43c:f70a:2af0 with SMTP id 5b1f17b1804b1-442d02f82d6mr24406445e9.16.1746692661936; Thu, 08 May 2025 01:24:21 -0700 (PDT) Received: from alex-rivos.lan ([2001:861:3382:ef90:e3eb:2939:f761:f7f1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd351327sm28113895e9.24.2025.05.08.01.24.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 01:24:21 -0700 (PDT) From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v2 2/3] riscv: Strengthen duplicate and inconsistent definition of RV_X() Date: Thu, 8 May 2025 10:22:14 +0200 Message-Id: <20250508082215.88658-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250508082215.88658-1-alexghiti@rivosinc.com> References: <20250508082215.88658-1-alexghiti@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RV_X() macro is defined in two different ways which is error prone. So harmonize its first definition and add another macro RV_X_mask() for the second one. Signed-off-by: Alexandre Ghiti --- arch/riscv/include/asm/insn.h | 39 ++++++++++++++-------------- arch/riscv/kernel/elf_kexec.c | 1 - arch/riscv/kernel/traps_misaligned.c | 1 - arch/riscv/kvm/vcpu_insn.c | 1 - 4 files changed, 20 insertions(+), 22 deletions(-) diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index 2a589a58b291..ac3e606feca2 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -288,43 +288,44 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 = code) =20 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) #define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1)) -#define RV_X(X, s, mask) (((X) >> (s)) & (mask)) -#define RVC_X(X, s, mask) RV_X(X, s, mask) +#define RV_X_mask(X, s, mask) (((X) >> (s)) & (mask)) +#define RV_X(X, s, n) RV_X_mask(X, s, ((1 << (n)) - 1)) +#define RVC_X(X, s, mask) RV_X_mask(X, s, mask) =20 #define RV_EXTRACT_RS1_REG(x) \ ({typeof(x) x_ =3D (x); \ - (RV_X(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); }) + (RV_X_mask(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); }) =20 #define RV_EXTRACT_RD_REG(x) \ ({typeof(x) x_ =3D (x); \ - (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); }) + (RV_X_mask(x_, RVG_RD_OPOFF, RVG_RD_MASK)); }) =20 #define RV_EXTRACT_UTYPE_IMM(x) \ ({typeof(x) x_ =3D (x); \ - (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); }) + (RV_X_mask(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); }) =20 #define RV_EXTRACT_JTYPE_IMM(x) \ ({typeof(x) x_ =3D (x); \ - (RV_X(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) = | \ - (RV_X(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \ - (RV_X(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OF= F) | \ + (RV_X_mask(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_= OFF) | \ + (RV_X_mask(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) |= \ + (RV_X_mask(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_= 12_OFF) | \ (RV_IMM_SIGN(x_) << RV_J_IMM_SIGN_OFF); }) =20 #define RV_EXTRACT_ITYPE_IMM(x) \ ({typeof(x) x_ =3D (x); \ - (RV_X(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \ + (RV_X_mask(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \ (RV_IMM_SIGN(x_) << RV_I_IMM_SIGN_OFF); }) =20 #define RV_EXTRACT_BTYPE_IMM(x) \ ({typeof(x) x_ =3D (x); \ - (RV_X(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \ - (RV_X(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) = | \ - (RV_X(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \ + (RV_X_mask(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF= ) | \ + (RV_X_mask(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_= OFF) | \ + (RV_X_mask(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) |= \ (RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); }) =20 #define RVC_EXTRACT_C2_RS1_REG(x) \ ({typeof(x) x_ =3D (x); \ - (RV_X(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); }) + (RV_X_mask(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); }) =20 #define RVC_EXTRACT_JTYPE_IMM(x) \ ({typeof(x) x_ =3D (x); \ @@ -346,10 +347,10 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 = code) (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); }) =20 #define RVG_EXTRACT_SYSTEM_CSR(x) \ - ({typeof(x) x_ =3D (x); RV_X(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK)= ; }) + ({typeof(x) x_ =3D (x); RV_X_mask(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_= MASK); }) =20 #define RVFDQ_EXTRACT_FL_FS_WIDTH(x) \ - ({typeof(x) x_ =3D (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \ + ({typeof(x) x_ =3D (x); RV_X_mask(x_, RVFDQ_FL_FS_WIDTH_OFF, \ RVFDQ_FL_FS_WIDTH_MASK); }) =20 #define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x) @@ -375,10 +376,10 @@ static inline void riscv_insn_insert_jtype_imm(u32 *i= nsn, s32 imm) { /* drop the old IMMs, all jal IMM bits sit at 31:12 */ *insn &=3D ~GENMASK(31, 12); - *insn |=3D (RV_X(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_= 10_1_OPOFF) | - (RV_X(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) | - (RV_X(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_O= POFF) | - (RV_X(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF); + *insn |=3D (RV_X_mask(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J= _IMM_10_1_OPOFF) | + (RV_X_mask(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF= ) | + (RV_X_mask(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19= _12_OPOFF) | + (RV_X_mask(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF); } =20 /* diff --git a/arch/riscv/kernel/elf_kexec.c b/arch/riscv/kernel/elf_kexec.c index e783a72d051f..15e6a8f3d50b 100644 --- a/arch/riscv/kernel/elf_kexec.c +++ b/arch/riscv/kernel/elf_kexec.c @@ -336,7 +336,6 @@ static void *elf_kexec_load(struct kimage *image, char = *kernel_buf, return ret ? ERR_PTR(ret) : NULL; } =20 -#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) #define RISCV_IMM_BITS 12 #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS) #define RISCV_CONST_HIGH_PART(x) \ diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 4354c87c0376..fb2599d62752 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -105,7 +105,6 @@ #define SH_RS2 20 #define SH_RS2C 2 =20 -#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) #define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \ (RV_X(x, 10, 3) << 3) | \ (RV_X(x, 5, 1) << 6)) diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index 97dec18e6989..ba4813673f95 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -91,7 +91,6 @@ #define SH_RS2C 2 #define MASK_RX 0x1f =20 -#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) #define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \ (RV_X(x, 10, 3) << 3) | \ (RV_X(x, 5, 1) << 6)) --=20 2.39.2 From nobody Sun Dec 14 23:24:49 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEA7625393F for ; Thu, 8 May 2025 08:25:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746692727; cv=none; b=jfDR3zU9syyxE2djIr5Ov08G7LLKtU4JrDpuqR0zmv0S72W47kYyC8s495JwAay0VMYtV4c3CSu6QQapHxPuezWt4wE3pi1gzudqH1E5EnXiIYD+b/x7f+shwCftMPpjjg/EENd9In/lVdgpDtvudc1sENnddszKyhJ2g1WAYPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746692727; c=relaxed/simple; bh=xpausTW52T6QUum2SHzO0c82w1MmRqKCZTMWSPWLu/s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LvB80n8SueJv/4FNdkRoxt2hqeRIV8pjzdfBqdqRp3aOtSFJotCW6+WoDhW+xnXAqkDAlY/fuYER35OReIZ2DG74SeOHiUstHt05XyGQMk08wAA3si1KgYNfDpAH872+3wzOxrjAXd4/cbvF5Vb5J1IQM74LrEjI1axiCgCQebs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=v1NTIsXw; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="v1NTIsXw" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-3a0bd7f4cd5so255414f8f.0 for ; Thu, 08 May 2025 01:25:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1746692723; x=1747297523; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=83ZJ2xDDIO+7x3e9GhGmFoQkXYTEmqgtwUx0+1qfS7w=; b=v1NTIsXwm4gAbhtsM4ITwq+qaWjet8htvmsxGrw2+LGZvh7sRjSnEjTic+Vv5pk89y 1ypMBuQ5/88CIx5aLWK/AbGTWryKj6dzVYBM/s4VmF6sdf8y/53NSFCGlDTxjX96afXz BS/ZzZQv5cogUzqeTW84MgnItHQL4Hmdz5peV8c6Dyqhl07uw/emekwix4429EfmZCn2 kkvSmX1g1UHKh+kAtKa4iJEW4azfwRSIhmot3GBQzBkInps79D8mhXw5sxLQf3DmpQm4 ORQbi1sxR7KH8AfBkLwNPw9Gy1SakMHTKZ++u0bedMogBIA5SkjbYhrNiIvJctusR0sR pZJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746692723; x=1747297523; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=83ZJ2xDDIO+7x3e9GhGmFoQkXYTEmqgtwUx0+1qfS7w=; b=rmtp8fYLhvYt6Ldd+1LarLvs6xRLdoKF6GoNwZzWl2bmt/1m5RD6Kg7M4XcR5K1DS/ etARP6wyFMbPHX056Ig8crrwPGTeHHuUvnHwzJFxlk7pcvVBE38bQlilX8Ca2ALBRvh5 XR4IO4Lw9sT0mHadcI4biYoUAXKHgf2XaHiCwHq+VCe3tmLlHqbZxV4UuJFa9oQVsi+0 QGzZUHgQc3OmSA+0eBckm5YTh08VAud6WdGQB02w5w6JHZYH+2xDsezbTzXmCWBYMczZ 8GoVVarUM0bjdiRhGxSs1CgmnhsKv3skruGDwtNGHMhv0rOcHdQKctbFYKQXLGGdIol6 KgvQ== X-Forwarded-Encrypted: i=1; AJvYcCWhzRvpNCHwg6s3drtT34u7jAbxqfXYC9OYb18Wtl3/i1DWC35F5B//tSi66eO9JAiliVOpMfYrY5a5IYQ=@vger.kernel.org X-Gm-Message-State: AOJu0YyseS0r89OPLq5FwuHAO2ECxq7YIw1K+KdrkD7LoFKXoBIVhPKY pbjEGKXcoGpoEIlv04biqQwH7KhEqlW5hA1w2xaYnaEzga0TIMEVq2kJ4Y26Ow8= X-Gm-Gg: ASbGncvo/OEcFqdP7W4I5h/b4QMVc03lr3Mw7GvaSyiHXfScS5lZyJ/FGIr39LooEIY hA+DneL75qSnw4pBE4a/HDhUwhzBp4GNkzrjebP5/h61BKdkgl5kllZCljSSusVacQ+U0Q/vmrr qj5RQlfYpa5WDT0zxOI0fcZsZhJIjnJSwhZxkdEfurQGaKPhBJNzdzAzLdv0k7mPXrI5IaKuC1D 2QxiN2Afem+RttG3KCcgDEZ+OAuOX23DI8fttzsMuGs6F+YTNw+7wZwoZeuYhMZ7mf+1qR/vxCP v2/09H77Wsdue2DafiICRL7qFZ/hiDSUDBrDGQnijuiKfLRh5vU= X-Google-Smtp-Source: AGHT+IG1jQvL4RDNOb2GMUnNOmfOUxK1ylBMjO/Qpsll70YsWZxnpRBM0g4r8ToNOmhiGQaL9whKKw== X-Received: by 2002:a5d:47a6:0:b0:39f:b604:4691 with SMTP id ffacd0b85a97d-3a0b4a21939mr4590048f8f.58.1746692722970; Thu, 08 May 2025 01:25:22 -0700 (PDT) Received: from alex-rivos.lan ([2001:861:3382:ef90:e3eb:2939:f761:f7f1]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a099ae3ccdsm19669622f8f.38.2025.05.08.01.25.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 01:25:22 -0700 (PDT) From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: Alexandre Ghiti , Andrew Jones Subject: [PATCH v2 3/3] riscv: Move all duplicate insn parsing macros into asm/insn.h Date: Thu, 8 May 2025 10:22:15 +0200 Message-Id: <20250508082215.88658-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250508082215.88658-1-alexghiti@rivosinc.com> References: <20250508082215.88658-1-alexghiti@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" kernel/traps_misaligned.c and kvm/vcpu_insn.c define the same macros to extract information from the instructions. Let's move the definitions into asm/insn.h to avoid this duplication. Reviewed-by: Andrew Jones Signed-off-by: Alexandre Ghiti --- arch/riscv/include/asm/insn.h | 164 ++++++++++++++++++++++++++- arch/riscv/kernel/elf_kexec.c | 1 + arch/riscv/kernel/traps_misaligned.c | 136 +--------------------- arch/riscv/kvm/vcpu_insn.c | 127 +-------------------- 4 files changed, 162 insertions(+), 266 deletions(-) diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index ac3e606feca2..7c65fc8baeed 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -286,11 +286,165 @@ static __always_inline bool riscv_insn_is_c_jalr(u32= code) (code & RVC_INSN_J_RS1_MASK) !=3D 0; } =20 -#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) -#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1)) -#define RV_X_mask(X, s, mask) (((X) >> (s)) & (mask)) -#define RV_X(X, s, n) RV_X_mask(X, s, ((1 << (n)) - 1)) -#define RVC_X(X, s, mask) RV_X_mask(X, s, mask) +#define INSN_MATCH_LB 0x3 +#define INSN_MASK_LB 0x707f +#define INSN_MATCH_LH 0x1003 +#define INSN_MASK_LH 0x707f +#define INSN_MATCH_LW 0x2003 +#define INSN_MASK_LW 0x707f +#define INSN_MATCH_LD 0x3003 +#define INSN_MASK_LD 0x707f +#define INSN_MATCH_LBU 0x4003 +#define INSN_MASK_LBU 0x707f +#define INSN_MATCH_LHU 0x5003 +#define INSN_MASK_LHU 0x707f +#define INSN_MATCH_LWU 0x6003 +#define INSN_MASK_LWU 0x707f +#define INSN_MATCH_SB 0x23 +#define INSN_MASK_SB 0x707f +#define INSN_MATCH_SH 0x1023 +#define INSN_MASK_SH 0x707f +#define INSN_MATCH_SW 0x2023 +#define INSN_MASK_SW 0x707f +#define INSN_MATCH_SD 0x3023 +#define INSN_MASK_SD 0x707f + +#define INSN_MATCH_C_LD 0x6000 +#define INSN_MASK_C_LD 0xe003 +#define INSN_MATCH_C_SD 0xe000 +#define INSN_MASK_C_SD 0xe003 +#define INSN_MATCH_C_LW 0x4000 +#define INSN_MASK_C_LW 0xe003 +#define INSN_MATCH_C_SW 0xc000 +#define INSN_MASK_C_SW 0xe003 +#define INSN_MATCH_C_LDSP 0x6002 +#define INSN_MASK_C_LDSP 0xe003 +#define INSN_MATCH_C_SDSP 0xe002 +#define INSN_MASK_C_SDSP 0xe003 +#define INSN_MATCH_C_LWSP 0x4002 +#define INSN_MASK_C_LWSP 0xe003 +#define INSN_MATCH_C_SWSP 0xc002 +#define INSN_MASK_C_SWSP 0xe003 + +#define INSN_OPCODE_MASK 0x007c +#define INSN_OPCODE_SHIFT 2 +#define INSN_OPCODE_SYSTEM 28 + +#define INSN_MASK_WFI 0xffffffff +#define INSN_MATCH_WFI 0x10500073 + +#define INSN_MASK_WRS 0xffffffff +#define INSN_MATCH_WRS 0x00d00073 + +#define INSN_MATCH_CSRRW 0x1073 +#define INSN_MASK_CSRRW 0x707f +#define INSN_MATCH_CSRRS 0x2073 +#define INSN_MASK_CSRRS 0x707f +#define INSN_MATCH_CSRRC 0x3073 +#define INSN_MASK_CSRRC 0x707f +#define INSN_MATCH_CSRRWI 0x5073 +#define INSN_MASK_CSRRWI 0x707f +#define INSN_MATCH_CSRRSI 0x6073 +#define INSN_MASK_CSRRSI 0x707f +#define INSN_MATCH_CSRRCI 0x7073 +#define INSN_MASK_CSRRCI 0x707f + +#define INSN_MATCH_FLW 0x2007 +#define INSN_MASK_FLW 0x707f +#define INSN_MATCH_FLD 0x3007 +#define INSN_MASK_FLD 0x707f +#define INSN_MATCH_FLQ 0x4007 +#define INSN_MASK_FLQ 0x707f +#define INSN_MATCH_FSW 0x2027 +#define INSN_MASK_FSW 0x707f +#define INSN_MATCH_FSD 0x3027 +#define INSN_MASK_FSD 0x707f +#define INSN_MATCH_FSQ 0x4027 +#define INSN_MASK_FSQ 0x707f + +#define INSN_MATCH_C_FLD 0x2000 +#define INSN_MASK_C_FLD 0xe003 +#define INSN_MATCH_C_FLW 0x6000 +#define INSN_MASK_C_FLW 0xe003 +#define INSN_MATCH_C_FSD 0xa000 +#define INSN_MASK_C_FSD 0xe003 +#define INSN_MATCH_C_FSW 0xe000 +#define INSN_MASK_C_FSW 0xe003 +#define INSN_MATCH_C_FLDSP 0x2002 +#define INSN_MASK_C_FLDSP 0xe003 +#define INSN_MATCH_C_FSDSP 0xa002 +#define INSN_MASK_C_FSDSP 0xe003 +#define INSN_MATCH_C_FLWSP 0x6002 +#define INSN_MASK_C_FLWSP 0xe003 +#define INSN_MATCH_C_FSWSP 0xe002 +#define INSN_MASK_C_FSWSP 0xe003 + +#define INSN_16BIT_MASK 0x3 +#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) !=3D INSN_16BIT_MA= SK) +#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4) + +#define SHIFT_RIGHT(x, y) \ + ((y) < 0 ? ((x) << -(y)) : ((x) >> (y))) + +#define REG_MASK \ + ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES)) + +#define REG_OFFSET(insn, pos) \ + (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK) + +#define REG_PTR(insn, pos, regs) \ + ((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))) + +#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs)) +#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs)) +#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs)) +#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs)) +#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs)) +#define GET_SP(regs) (*REG_PTR(2, 0, regs)) +#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) =3D (val)) +#define IMM_I(insn) ((s32)(insn) >> 20) +#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \ + (s32)(((insn) >> 7) & 0x1f)) + +#define SH_RD 7 +#define SH_RS1 15 +#define SH_RS2 20 +#define SH_RS2C 2 +#define MASK_RX 0x1f + +#if defined(CONFIG_64BIT) +#define LOG_REGBYTES 3 +#else +#define LOG_REGBYTES 2 +#endif + +#define MASK_FUNCT3 0x7000 + +#define GET_FUNCT3(insn) (((insn) >> 12) & 7) + +#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) +#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1)) +#define RV_X_mask(X, s, mask) (((X) >> (s)) & (mask)) +#define RV_X(X, s, n) RV_X_mask(X, s, ((1 << (n)) - 1)) +#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \ + (RV_X(x, 10, 3) << 3) | \ + (RV_X(x, 5, 1) << 6)) +#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \ + (RV_X(x, 5, 2) << 6)) +#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \ + (RV_X(x, 12, 1) << 5) | \ + (RV_X(x, 2, 2) << 6)) +#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \ + (RV_X(x, 12, 1) << 5) | \ + (RV_X(x, 2, 3) << 6)) +#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \ + (RV_X(x, 7, 2) << 6)) +#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \ + (RV_X(x, 7, 3) << 6)) +#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3)) +#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3)) +#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5) +#define RVC_X(X, s, mask) RV_X_mask(X, s, mask) =20 #define RV_EXTRACT_RS1_REG(x) \ ({typeof(x) x_ =3D (x); \ diff --git a/arch/riscv/kernel/elf_kexec.c b/arch/riscv/kernel/elf_kexec.c index 15e6a8f3d50b..1c3b76a67356 100644 --- a/arch/riscv/kernel/elf_kexec.c +++ b/arch/riscv/kernel/elf_kexec.c @@ -21,6 +21,7 @@ #include #include #include +#include =20 int arch_kimage_file_post_load_cleanup(struct kimage *image) { diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index fb2599d62752..0151f670cd46 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -17,141 +17,7 @@ #include #include #include - -#define INSN_MATCH_LB 0x3 -#define INSN_MASK_LB 0x707f -#define INSN_MATCH_LH 0x1003 -#define INSN_MASK_LH 0x707f -#define INSN_MATCH_LW 0x2003 -#define INSN_MASK_LW 0x707f -#define INSN_MATCH_LD 0x3003 -#define INSN_MASK_LD 0x707f -#define INSN_MATCH_LBU 0x4003 -#define INSN_MASK_LBU 0x707f -#define INSN_MATCH_LHU 0x5003 -#define INSN_MASK_LHU 0x707f -#define INSN_MATCH_LWU 0x6003 -#define INSN_MASK_LWU 0x707f -#define INSN_MATCH_SB 0x23 -#define INSN_MASK_SB 0x707f -#define INSN_MATCH_SH 0x1023 -#define INSN_MASK_SH 0x707f -#define INSN_MATCH_SW 0x2023 -#define INSN_MASK_SW 0x707f -#define INSN_MATCH_SD 0x3023 -#define INSN_MASK_SD 0x707f - -#define INSN_MATCH_FLW 0x2007 -#define INSN_MASK_FLW 0x707f -#define INSN_MATCH_FLD 0x3007 -#define INSN_MASK_FLD 0x707f -#define INSN_MATCH_FLQ 0x4007 -#define INSN_MASK_FLQ 0x707f -#define INSN_MATCH_FSW 0x2027 -#define INSN_MASK_FSW 0x707f -#define INSN_MATCH_FSD 0x3027 -#define INSN_MASK_FSD 0x707f -#define INSN_MATCH_FSQ 0x4027 -#define INSN_MASK_FSQ 0x707f - -#define INSN_MATCH_C_LD 0x6000 -#define INSN_MASK_C_LD 0xe003 -#define INSN_MATCH_C_SD 0xe000 -#define INSN_MASK_C_SD 0xe003 -#define INSN_MATCH_C_LW 0x4000 -#define INSN_MASK_C_LW 0xe003 -#define INSN_MATCH_C_SW 0xc000 -#define INSN_MASK_C_SW 0xe003 -#define INSN_MATCH_C_LDSP 0x6002 -#define INSN_MASK_C_LDSP 0xe003 -#define INSN_MATCH_C_SDSP 0xe002 -#define INSN_MASK_C_SDSP 0xe003 -#define INSN_MATCH_C_LWSP 0x4002 -#define INSN_MASK_C_LWSP 0xe003 -#define INSN_MATCH_C_SWSP 0xc002 -#define INSN_MASK_C_SWSP 0xe003 - -#define INSN_MATCH_C_FLD 0x2000 -#define INSN_MASK_C_FLD 0xe003 -#define INSN_MATCH_C_FLW 0x6000 -#define INSN_MASK_C_FLW 0xe003 -#define INSN_MATCH_C_FSD 0xa000 -#define INSN_MASK_C_FSD 0xe003 -#define INSN_MATCH_C_FSW 0xe000 -#define INSN_MASK_C_FSW 0xe003 -#define INSN_MATCH_C_FLDSP 0x2002 -#define INSN_MASK_C_FLDSP 0xe003 -#define INSN_MATCH_C_FSDSP 0xa002 -#define INSN_MASK_C_FSDSP 0xe003 -#define INSN_MATCH_C_FLWSP 0x6002 -#define INSN_MASK_C_FLWSP 0xe003 -#define INSN_MATCH_C_FSWSP 0xe002 -#define INSN_MASK_C_FSWSP 0xe003 - -#define INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4) - -#if defined(CONFIG_64BIT) -#define LOG_REGBYTES 3 -#define XLEN 64 -#else -#define LOG_REGBYTES 2 -#define XLEN 32 -#endif -#define REGBYTES (1 << LOG_REGBYTES) -#define XLEN_MINUS_16 ((XLEN) - 16) - -#define SH_RD 7 -#define SH_RS1 15 -#define SH_RS2 20 -#define SH_RS2C 2 - -#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \ - (RV_X(x, 10, 3) << 3) | \ - (RV_X(x, 5, 1) << 6)) -#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \ - (RV_X(x, 5, 2) << 6)) -#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \ - (RV_X(x, 12, 1) << 5) | \ - (RV_X(x, 2, 2) << 6)) -#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \ - (RV_X(x, 12, 1) << 5) | \ - (RV_X(x, 2, 3) << 6)) -#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \ - (RV_X(x, 7, 2) << 6)) -#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \ - (RV_X(x, 7, 3) << 6)) -#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3)) -#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3)) -#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5) - -#define SHIFT_RIGHT(x, y) \ - ((y) < 0 ? ((x) << -(y)) : ((x) >> (y))) - -#define REG_MASK \ - ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES)) - -#define REG_OFFSET(insn, pos) \ - (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK) - -#define REG_PTR(insn, pos, regs) \ - (ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)) - -#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs)) -#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs)) -#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs)) -#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs)) -#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs)) -#define GET_SP(regs) (*REG_PTR(2, 0, regs)) -#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) =3D (val)) -#define IMM_I(insn) ((s32)(insn) >> 20) -#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \ - (s32)(((insn) >> 7) & 0x1f)) -#define MASK_FUNCT3 0x7000 - -#define GET_PRECISION(insn) (((insn) >> 25) & 3) -#define GET_RM(insn) (((insn) >> 12) & 7) -#define PRECISION_S 0 -#define PRECISION_D 1 +#include =20 #ifdef CONFIG_FPU =20 diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index ba4813673f95..de1f96ea6225 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -8,132 +8,7 @@ #include =20 #include - -#define INSN_OPCODE_MASK 0x007c -#define INSN_OPCODE_SHIFT 2 -#define INSN_OPCODE_SYSTEM 28 - -#define INSN_MASK_WFI 0xffffffff -#define INSN_MATCH_WFI 0x10500073 - -#define INSN_MASK_WRS 0xffffffff -#define INSN_MATCH_WRS 0x00d00073 - -#define INSN_MATCH_CSRRW 0x1073 -#define INSN_MASK_CSRRW 0x707f -#define INSN_MATCH_CSRRS 0x2073 -#define INSN_MASK_CSRRS 0x707f -#define INSN_MATCH_CSRRC 0x3073 -#define INSN_MASK_CSRRC 0x707f -#define INSN_MATCH_CSRRWI 0x5073 -#define INSN_MASK_CSRRWI 0x707f -#define INSN_MATCH_CSRRSI 0x6073 -#define INSN_MASK_CSRRSI 0x707f -#define INSN_MATCH_CSRRCI 0x7073 -#define INSN_MASK_CSRRCI 0x707f - -#define INSN_MATCH_LB 0x3 -#define INSN_MASK_LB 0x707f -#define INSN_MATCH_LH 0x1003 -#define INSN_MASK_LH 0x707f -#define INSN_MATCH_LW 0x2003 -#define INSN_MASK_LW 0x707f -#define INSN_MATCH_LD 0x3003 -#define INSN_MASK_LD 0x707f -#define INSN_MATCH_LBU 0x4003 -#define INSN_MASK_LBU 0x707f -#define INSN_MATCH_LHU 0x5003 -#define INSN_MASK_LHU 0x707f -#define INSN_MATCH_LWU 0x6003 -#define INSN_MASK_LWU 0x707f -#define INSN_MATCH_SB 0x23 -#define INSN_MASK_SB 0x707f -#define INSN_MATCH_SH 0x1023 -#define INSN_MASK_SH 0x707f -#define INSN_MATCH_SW 0x2023 -#define INSN_MASK_SW 0x707f -#define INSN_MATCH_SD 0x3023 -#define INSN_MASK_SD 0x707f - -#define INSN_MATCH_C_LD 0x6000 -#define INSN_MASK_C_LD 0xe003 -#define INSN_MATCH_C_SD 0xe000 -#define INSN_MASK_C_SD 0xe003 -#define INSN_MATCH_C_LW 0x4000 -#define INSN_MASK_C_LW 0xe003 -#define INSN_MATCH_C_SW 0xc000 -#define INSN_MASK_C_SW 0xe003 -#define INSN_MATCH_C_LDSP 0x6002 -#define INSN_MASK_C_LDSP 0xe003 -#define INSN_MATCH_C_SDSP 0xe002 -#define INSN_MASK_C_SDSP 0xe003 -#define INSN_MATCH_C_LWSP 0x4002 -#define INSN_MASK_C_LWSP 0xe003 -#define INSN_MATCH_C_SWSP 0xc002 -#define INSN_MASK_C_SWSP 0xe003 - -#define INSN_16BIT_MASK 0x3 - -#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) !=3D INSN_16BIT_MA= SK) - -#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4) - -#ifdef CONFIG_64BIT -#define LOG_REGBYTES 3 -#else -#define LOG_REGBYTES 2 -#endif -#define REGBYTES (1 << LOG_REGBYTES) - -#define SH_RD 7 -#define SH_RS1 15 -#define SH_RS2 20 -#define SH_RS2C 2 -#define MASK_RX 0x1f - -#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \ - (RV_X(x, 10, 3) << 3) | \ - (RV_X(x, 5, 1) << 6)) -#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \ - (RV_X(x, 5, 2) << 6)) -#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \ - (RV_X(x, 12, 1) << 5) | \ - (RV_X(x, 2, 2) << 6)) -#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \ - (RV_X(x, 12, 1) << 5) | \ - (RV_X(x, 2, 3) << 6)) -#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \ - (RV_X(x, 7, 2) << 6)) -#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \ - (RV_X(x, 7, 3) << 6)) -#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3)) -#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3)) -#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5) - -#define SHIFT_RIGHT(x, y) \ - ((y) < 0 ? ((x) << -(y)) : ((x) >> (y))) - -#define REG_MASK \ - ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES)) - -#define REG_OFFSET(insn, pos) \ - (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK) - -#define REG_PTR(insn, pos, regs) \ - ((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))) - -#define GET_FUNCT3(insn) (((insn) >> 12) & 7) - -#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs)) -#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs)) -#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs)) -#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs)) -#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs)) -#define GET_SP(regs) (*REG_PTR(2, 0, regs)) -#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) =3D (val)) -#define IMM_I(insn) ((s32)(insn) >> 20) -#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \ - (s32)(((insn) >> 7) & 0x1f)) +#include =20 struct insn_func { unsigned long mask; --=20 2.39.2