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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000FCC4.mail.protection.outlook.com (10.167.242.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8722.18 via Frontend Transport; Thu, 8 May 2025 05:01:11 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 8 May 2025 00:01:09 -0500 Received: from xhdipdslab61.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Thu, 8 May 2025 00:01:05 -0500 From: Abhijit Gangurde To: , , , , , , , , , CC: , , , , , , Abhijit Gangurde , Andrew Boyer Subject: [PATCH v2 08/14] RDMA/ionic: Register auxiliary module for ionic ethernet adapter Date: Thu, 8 May 2025 10:29:51 +0530 Message-ID: <20250508045957.2823318-9-abhijit.gangurde@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250508045957.2823318-1-abhijit.gangurde@amd.com> References: <20250508045957.2823318-1-abhijit.gangurde@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: abhijit.gangurde@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC4:EE_|DS2PR12MB9638:EE_ X-MS-Office365-Filtering-Correlation-Id: 49b859cc-26de-4e1d-53fb-08dd8ded5a46 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 May 2025 05:01:11.6356 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49b859cc-26de-4e1d-53fb-08dd8ded5a46 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9638 Content-Type: text/plain; charset="utf-8" Register auxiliary module to create ibdevice for ionic ethernet adapter. Co-developed-by: Andrew Boyer Signed-off-by: Andrew Boyer Co-developed-by: Allen Hubbe Signed-off-by: Allen Hubbe Signed-off-by: Abhijit Gangurde --- v1->v2 - Removed netdev references from ionic RDMA driver - Moved to ionic_lif* instead of void* to convey information between aux devices and drivers. drivers/infiniband/hw/ionic/ionic_ibdev.c | 135 ++++++++++++++++++++ drivers/infiniband/hw/ionic/ionic_ibdev.h | 21 +++ drivers/infiniband/hw/ionic/ionic_lif_cfg.c | 121 ++++++++++++++++++ drivers/infiniband/hw/ionic/ionic_lif_cfg.h | 65 ++++++++++ 4 files changed, 342 insertions(+) create mode 100644 drivers/infiniband/hw/ionic/ionic_ibdev.c create mode 100644 drivers/infiniband/hw/ionic/ionic_ibdev.h create mode 100644 drivers/infiniband/hw/ionic/ionic_lif_cfg.c create mode 100644 drivers/infiniband/hw/ionic/ionic_lif_cfg.h diff --git a/drivers/infiniband/hw/ionic/ionic_ibdev.c b/drivers/infiniband= /hw/ionic/ionic_ibdev.c new file mode 100644 index 000000000000..ca047a789378 --- /dev/null +++ b/drivers/infiniband/hw/ionic/ionic_ibdev.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */ + +#include +#include +#include + +#include "ionic_ibdev.h" + +#define DRIVER_DESCRIPTION "AMD Pensando RoCE HCA driver" +#define DEVICE_DESCRIPTION "AMD Pensando RoCE HCA" + +MODULE_AUTHOR("Allen Hubbe "); +MODULE_DESCRIPTION(DRIVER_DESCRIPTION); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("NET_IONIC"); + +static const struct auxiliary_device_id ionic_aux_id_table[] =3D { + { .name =3D "ionic.rdma", }, + {}, +}; + +MODULE_DEVICE_TABLE(auxiliary, ionic_aux_id_table); + +static void ionic_destroy_ibdev(struct ionic_ibdev *dev) +{ + ib_unregister_device(&dev->ibdev); + ib_dealloc_device(&dev->ibdev); +} + +static struct ionic_ibdev *ionic_create_ibdev(struct ionic_aux_dev *ionic_= adev) +{ + struct ib_device *ibdev; + struct ionic_ibdev *dev; + int rc; + + rc =3D ionic_version_check(&ionic_adev->adev.dev, ionic_adev->lif); + if (rc) + goto err_dev; + + dev =3D ib_alloc_device(ionic_ibdev, ibdev); + if (!dev) { + rc =3D -ENOMEM; + goto err_dev; + } + + ionic_fill_lif_cfg(ionic_adev->lif, &dev->lif_cfg); + + ibdev =3D &dev->ibdev; + ibdev->dev.parent =3D dev->lif_cfg.hwdev; + + strscpy(ibdev->name, "ionic_%d", IB_DEVICE_NAME_MAX); + strscpy(ibdev->node_desc, DEVICE_DESCRIPTION, IB_DEVICE_NODE_DESC_MAX); + + ibdev->node_type =3D RDMA_NODE_IB_CA; + ibdev->phys_port_cnt =3D 1; + + /* the first two eq are reserved for async events */ + ibdev->num_comp_vectors =3D dev->lif_cfg.eq_count - 2; + + addrconf_ifid_eui48((u8 *)&ibdev->node_guid, + ionic_lif_netdev(ionic_adev->lif)); + + rc =3D ib_device_set_netdev(ibdev, ionic_lif_netdev(ionic_adev->lif), 1); + if (rc) + goto err_admin; + + rc =3D ib_register_device(ibdev, "ionic_%d", ibdev->dev.parent); + if (rc) + goto err_register; + + return dev; + +err_register: +err_admin: + ib_dealloc_device(&dev->ibdev); +err_dev: + return ERR_PTR(rc); +} + +static int ionic_aux_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct ionic_aux_dev *ionic_adev; + struct ionic_ibdev *dev; + + ionic_adev =3D container_of(adev, struct ionic_aux_dev, adev); + dev =3D ionic_create_ibdev(ionic_adev); + if (IS_ERR(dev)) + return dev_err_probe(&adev->dev, PTR_ERR(dev), + "Failed to register ibdev\n"); + + auxiliary_set_drvdata(adev, dev); + ibdev_dbg(&dev->ibdev, "registered\n"); + + return 0; +} + +static void ionic_aux_remove(struct auxiliary_device *adev) +{ + struct ionic_ibdev *dev =3D auxiliary_get_drvdata(adev); + + dev_dbg(&adev->dev, "unregister ibdev\n"); + ionic_destroy_ibdev(dev); + dev_dbg(&adev->dev, "unregistered\n"); +} + +static struct auxiliary_driver ionic_aux_r_driver =3D { + .name =3D "rdma", + .probe =3D ionic_aux_probe, + .remove =3D ionic_aux_remove, + .id_table =3D ionic_aux_id_table, +}; + +static int __init ionic_mod_init(void) +{ + int rc; + + rc =3D auxiliary_driver_register(&ionic_aux_r_driver); + if (rc) + goto err_aux; + + return 0; + +err_aux: + return rc; +} + +static void __exit ionic_mod_exit(void) +{ + auxiliary_driver_unregister(&ionic_aux_r_driver); +} + +module_init(ionic_mod_init); +module_exit(ionic_mod_exit); diff --git a/drivers/infiniband/hw/ionic/ionic_ibdev.h b/drivers/infiniband= /hw/ionic/ionic_ibdev.h new file mode 100644 index 000000000000..e13adff390d7 --- /dev/null +++ b/drivers/infiniband/hw/ionic/ionic_ibdev.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */ + +#ifndef _IONIC_IBDEV_H_ +#define _IONIC_IBDEV_H_ + +#include +#include + +#include "ionic_lif_cfg.h" + +#define IONIC_MIN_RDMA_VERSION 0 +#define IONIC_MAX_RDMA_VERSION 2 + +struct ionic_ibdev { + struct ib_device ibdev; + + struct ionic_lif_cfg lif_cfg; +}; + +#endif /* _IONIC_IBDEV_H_ */ diff --git a/drivers/infiniband/hw/ionic/ionic_lif_cfg.c b/drivers/infiniba= nd/hw/ionic/ionic_lif_cfg.c new file mode 100644 index 000000000000..a02eb2f5bd45 --- /dev/null +++ b/drivers/infiniband/hw/ionic/ionic_lif_cfg.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */ + +#include + +#include +#include + +#include "ionic_lif_cfg.h" + +#define IONIC_MIN_RDMA_VERSION 0 +#define IONIC_MAX_RDMA_VERSION 2 + +static u8 ionic_get_expdb(struct ionic_lif *lif) +{ + u8 expdb_support =3D 0; + + if (lif->ionic->idev.phy_cmb_expdb64_pages) + expdb_support |=3D IONIC_EXPDB_64B_WQE; + if (lif->ionic->idev.phy_cmb_expdb128_pages) + expdb_support |=3D IONIC_EXPDB_128B_WQE; + if (lif->ionic->idev.phy_cmb_expdb256_pages) + expdb_support |=3D IONIC_EXPDB_256B_WQE; + if (lif->ionic->idev.phy_cmb_expdb512_pages) + expdb_support |=3D IONIC_EXPDB_512B_WQE; + + return expdb_support; +} + +void ionic_fill_lif_cfg(struct ionic_lif *lif, struct ionic_lif_cfg *cfg) +{ + union ionic_lif_identity *ident =3D &lif->ionic->ident.lif; + + cfg->lif =3D lif; + cfg->hwdev =3D &lif->ionic->pdev->dev; + cfg->lif_index =3D lif->index; + cfg->lif_hw_index =3D lif->hw_index; + + cfg->dbid =3D lif->kern_pid; + cfg->dbid_count =3D le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); + cfg->dbpage =3D lif->kern_dbpage; + cfg->intr_ctrl =3D lif->ionic->idev.intr_ctrl; + + cfg->db_phys =3D lif->ionic->bars[IONIC_PCI_BAR_DBELL].bus_addr; + + if (IONIC_VERSION(ident->rdma.version, ident->rdma.minor_version) >=3D + IONIC_VERSION(2, 1)) + cfg->page_size_supported =3D + cpu_to_le64(ident->rdma.page_size_cap); + else + cfg->page_size_supported =3D IONIC_PAGE_SIZE_SUPPORTED; + + cfg->rdma_version =3D ident->rdma.version; + cfg->qp_opcodes =3D ident->rdma.qp_opcodes; + cfg->admin_opcodes =3D ident->rdma.admin_opcodes; + + cfg->stats_type =3D cpu_to_le16(ident->rdma.stats_type); + cfg->npts_per_lif =3D le32_to_cpu(ident->rdma.npts_per_lif); + cfg->nmrs_per_lif =3D le32_to_cpu(ident->rdma.nmrs_per_lif); + cfg->nahs_per_lif =3D le32_to_cpu(ident->rdma.nahs_per_lif); + + cfg->aq_base =3D le32_to_cpu(ident->rdma.aq_qtype.qid_base); + cfg->cq_base =3D le32_to_cpu(ident->rdma.cq_qtype.qid_base); + cfg->eq_base =3D le32_to_cpu(ident->rdma.eq_qtype.qid_base); + + /* + * ionic_create_rdma_admin() may reduce aq_count or eq_count if + * it is unable to allocate all that were requested. + * aq_count is tunable; see ionic_aq_count + * eq_count is tunable; see ionic_eq_count + */ + cfg->aq_count =3D le32_to_cpu(ident->rdma.aq_qtype.qid_count); + cfg->eq_count =3D le32_to_cpu(ident->rdma.eq_qtype.qid_count); + cfg->cq_count =3D le32_to_cpu(ident->rdma.cq_qtype.qid_count); + cfg->qp_count =3D le32_to_cpu(ident->rdma.sq_qtype.qid_count); + cfg->dbid_count =3D le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); + + cfg->aq_qtype =3D ident->rdma.aq_qtype.qtype; + cfg->sq_qtype =3D ident->rdma.sq_qtype.qtype; + cfg->rq_qtype =3D ident->rdma.rq_qtype.qtype; + cfg->cq_qtype =3D ident->rdma.cq_qtype.qtype; + cfg->eq_qtype =3D ident->rdma.eq_qtype.qtype; + cfg->udma_qgrp_shift =3D ident->rdma.udma_shift; + cfg->udma_count =3D 2; + + cfg->max_stride =3D ident->rdma.max_stride; + cfg->expdb_mask =3D ionic_get_expdb(lif); + + cfg->sq_expdb =3D + !!(lif->qtype_info[IONIC_QTYPE_TXQ].features & IONIC_QIDENT_F_EXPDB); + cfg->rq_expdb =3D + !!(lif->qtype_info[IONIC_QTYPE_RXQ].features & IONIC_QIDENT_F_EXPDB); +} + +struct net_device *ionic_lif_netdev(struct ionic_lif *lif) +{ + return lif->netdev; +} + +int ionic_version_check(const struct device *dev, struct ionic_lif *lif) +{ + union ionic_lif_identity *ident =3D &lif->ionic->ident.lif; + int rc; + + if (ident->rdma.version < IONIC_MIN_RDMA_VERSION || + ident->rdma.version > IONIC_MAX_RDMA_VERSION) { + rc =3D -EINVAL; + dev_err_probe(dev, rc, + "ionic_rdma: incompatible version, fw ver %u\n", + ident->rdma.version); + dev_err_probe(dev, rc, + "ionic_rdma: Driver Min Version %u\n", + IONIC_MIN_RDMA_VERSION); + dev_err_probe(dev, rc, + "ionic_rdma: Driver Max Version %u\n", + IONIC_MAX_RDMA_VERSION); + return rc; + } + + return 0; +} diff --git a/drivers/infiniband/hw/ionic/ionic_lif_cfg.h b/drivers/infiniba= nd/hw/ionic/ionic_lif_cfg.h new file mode 100644 index 000000000000..b095637c54cf --- /dev/null +++ b/drivers/infiniband/hw/ionic/ionic_lif_cfg.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */ + +#ifndef _IONIC_LIF_CFG_H_ + +#define IONIC_VERSION(a, b) (((a) << 16) + ((b) << 8)) +#define IONIC_PAGE_SIZE_SUPPORTED 0x40201000 /* 4kb, 2Mb, 1Gb */ + +#define IONIC_EXPDB_64B_WQE BIT(0) +#define IONIC_EXPDB_128B_WQE BIT(1) +#define IONIC_EXPDB_256B_WQE BIT(2) +#define IONIC_EXPDB_512B_WQE BIT(3) + +struct ionic_lif_cfg { + struct device *hwdev; + struct ionic_lif *lif; + + int lif_index; + int lif_hw_index; + + u32 dbid; + int dbid_count; + u64 __iomem *dbpage; + struct ionic_intr __iomem *intr_ctrl; + phys_addr_t db_phys; + + u64 page_size_supported; + u32 npts_per_lif; + u32 nmrs_per_lif; + u32 nahs_per_lif; + + u32 aq_base; + u32 cq_base; + u32 eq_base; + + int aq_count; + int eq_count; + int cq_count; + int qp_count; + + u16 stats_type; + u8 aq_qtype; + u8 sq_qtype; + u8 rq_qtype; + u8 cq_qtype; + u8 eq_qtype; + + u8 udma_count; + u8 udma_qgrp_shift; + + u8 rdma_version; + u8 qp_opcodes; + u8 admin_opcodes; + + u8 max_stride; + bool sq_expdb; + bool rq_expdb; + u8 expdb_mask; +}; + +int ionic_version_check(const struct device *dev, struct ionic_lif *lif); +void ionic_fill_lif_cfg(struct ionic_lif *lif, struct ionic_lif_cfg *cfg); +struct net_device *ionic_lif_netdev(struct ionic_lif *lif); + +#endif /* _IONIC_LIF_CFG_H_ */ --=20 2.34.1