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[87.8.31.78]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd363940sm31699665e9.25.2025.05.08.03.07.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 03:07:22 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 08 May 2025 12:06:05 +0200 Subject: [PATCH v4 1/5] Documentation: ABI: IIO: add calibconv_delay documentation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250508-wip-bl-ad7606-calibration-v4-1-91a3f2837e6b@baylibre.com> References: <20250508-wip-bl-ad7606-calibration-v4-0-91a3f2837e6b@baylibre.com> In-Reply-To: <20250508-wip-bl-ad7606-calibration-v4-0-91a3f2837e6b@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1880; i=adureghello@baylibre.com; h=from:subject:message-id; bh=oTr2y1KzI44sJPbPH4SmBsKovzD+NKhk9SBNTTYhjpc=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiQaeJXEP2mWPkgsFDgmEK/6uYUhUV7bh0v5c0LfyxQn PHR9+D3jlIWBjEuBlkxRZa6xAiT0NuhUsoLGGfDzGFlAhnCwMUpABPJaWJkuBzOtcj4a19uVtaG xZ3u87R3rhSI2y41teLHR1bneIelUxn+V7E6v9rw6qbZrbSdHLtPG1pM/KDzoL5lrfgKjq/9BxY 4swIA X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add new IIO calibconv_delay documentation. The ad7606 implements a phase calibation feature, in nanoseconds. Being this a time delay, using the conv_delay suffix. Signed-off-by: Angelo Dureghello --- Documentation/ABI/testing/sysfs-bus-iio | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index 190bfcc1e836b69622692d7c056c0092e00f1a9b..9ced916895fbef146d46d17b5fd= c932784b4c1df 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -559,6 +559,30 @@ Description: - a small discrete set of values like "0 2 4 6 8" - a range specified as "[min step max]" =20 +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_convdelay +KernelVersion: 6.16 +Contact: linux-iio@vger.kernel.org +Description: + Delay of start of conversion in seconds from common reference + point shared by all channels. Can be writable when used to + compensate for delay variation introduced by external filters + feeding a simultaneous sampling ADC. + + I.e., for the ad7606 ADC series, this value is intended as a + configurable time delay in seconds, to correct delay introduced + by an optional external filtering circuit. + +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_convdelay_available +KernelVersion: 6.16 +Contact: linux-iio@vger.kernel.org +Description: + Available values of convdelay. Maybe expressed as: + + - a range specified as "[min step max]" + + If shared across all channels, _calibconv_delay_available + is used. + What: /sys/bus/iio/devices/iio:deviceX/in_accel_x_calibscale What: /sys/bus/iio/devices/iio:deviceX/in_accel_y_calibscale What: /sys/bus/iio/devices/iio:deviceX/in_accel_z_calibscale --=20 2.49.0 From nobody Tue Dec 16 05:57:00 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E08AE1C84CF for ; Thu, 8 May 2025 10:07:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746698848; cv=none; b=CSOtOiYFidgnJjPfTmd0h76Dvyp9ALDL8xbQVObcfTwLx2aQvIQLDHYL7GdXHInjiOeCickADMsty8g7a79b9YDwS+AqOITuVarxXWwoZihApINgwKUEGDH7rc8sV4kzj3HqP0hwHcrzbluzBy2Prh17Jx25iHaJFThMsWV2MKA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746698848; c=relaxed/simple; bh=8DecWNX9a+g7ci97Vv7IU6U85+eTrGoiJDNqhMLAwD0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KEKKz4Onjg/o4k0/O6xvAqXYS2gSWRh1i3vXGpuWnWQOv9IJmOxTWxmUh9j9DJPy0TTq2xcdvPTZpQx2QjzZrGqPlLPUwGTfYhUgnq+4hADv8EhFBZuRz26qK6wZu1bvPODxKijU3usmGUTn3M8/uPJZsqNP9kx7k37eWTI3TBo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=lyvpKTOX; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="lyvpKTOX" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-43d0618746bso5874205e9.2 for ; Thu, 08 May 2025 03:07:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1746698845; x=1747303645; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gQIoahuutc2qqjFxwM4CJBJC7cg2fQ/5cUj9Q0XSXuA=; b=lyvpKTOXERZ29rWXJ5wzwrZ2hulMV9XCRo5DTrp9vK65+zVjXQCcSg6UBXTHgkknoe EnB9vYFCvYE3oJklxQGKHEWMYjQ02rLjnDFmisX+z09jIYQml2j82MSwELVnn3OZbnfZ 1S0XGV2iKaaeBG31EgMidbk494/69mI+J0E5soFD6LcEYWqV6wUhBihx94uyu7MVKA+O YSefer75+A+t2nQZ1FqnGvg21kW36kLfP8Ynsa236EUZVRWR3V4U4PQYf2ZiaDLEPVeM aiNuLEQ96DsMNQVRwpSTu1eeL+Ouh1CYg2UIv/u86R4WloYb2KD4ojnaRcD13AX1PA5A FhOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746698845; x=1747303645; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gQIoahuutc2qqjFxwM4CJBJC7cg2fQ/5cUj9Q0XSXuA=; b=bKKnkXVRvVGj4jerft04gwmSft4i1l18i0cbJbTWqlXceZN6shwt/MLahuL+zmZeog khaWFWgjsWmRoMUOZLwH83mcOQYt1M2ETIdfI7oZQEIKBr6hKXAO22+HxDvl3eoNQE+y rQDLIEfB96EbqVA6fG3B4luEjSXPIcQVQw8VFwfKXSGX6wA3pVvvU1xRbFCUMZyC0ZL3 G/5/oB5jpQO0lolmKvJ3kCbFiQxRfqWyPmq5t9Fn7fzQjFFQ5Q2fqhX4k2hHxJy7CXtc C7gM76V9bYrizok0AyRC5NOB79PHmpunwDja4eMMyJwM07RG67Cp0McDboCn4/Lm1+GC BAXg== X-Forwarded-Encrypted: i=1; AJvYcCUSyeTQwGqKmkuqNL1peCbvWfIzwEKcHPV/bdgptBbrywf7uNm4rGEggOuyOnvRssfO8bRvHR+Q/OWJk48=@vger.kernel.org X-Gm-Message-State: AOJu0YxGPNc9RE6+loFXXW5F0sdBH8+x4IgLqQgJB8wUqls0DdkW6ofr Vxj5+TJVwSlt2+1hSf0CV7i5c3UanZxV64uXNxugnyjjAkcADL4qWzBilOJd5c4= X-Gm-Gg: ASbGncuxCVccZwmzSj9CjtGJl4XFBAKeNd9XvPvnqT5Z9q3BH/dLMUkL7bIwWvwffeM zEybNDGGvGx2xUIO5rupfYa+tmlh2OTmH0khxTDY0VBG/jJ7kCovylufUOBicrarBI0zMxTbE+M jOmwnjySnOI9UkWbMUIVD00meq/yXp232AcLFQk4kk0BCsFqS6nbR1j/yWTyGMKZf0WmK8FPBAR y60TxRQ8F8FRLACuRt1hqmTsv4UTlSFsR+Wgma62M2nnm3naw29Ehq18QQtKVi3rangK+bS7R+6 8NOPaXmwzqjvz+HYYpmy6Y4dUQXHqNSecAEdE3HLO4tnazo581abWC2KVgwPY582tRF15wvO3FJ eZPnOHV2EYK2X X-Google-Smtp-Source: AGHT+IF9EQT4M5SmZsHAxZZKz+TKrhTiH7Tl3JMTlzBWU/8jiEAgKt5PKxZvsg6SfE8e2vmOVcIRAA== X-Received: by 2002:a05:600c:4454:b0:43c:fffc:7886 with SMTP id 5b1f17b1804b1-441d44c2d62mr50234245e9.8.1746698845213; Thu, 08 May 2025 03:07:25 -0700 (PDT) Received: from [192.168.0.2] (host-87-8-31-78.retail.telecomitalia.it. [87.8.31.78]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd363940sm31699665e9.25.2025.05.08.03.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 03:07:24 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 08 May 2025 12:06:06 +0200 Subject: [PATCH v4 2/5] iio: core: add ADC delay calibration definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250508-wip-bl-ad7606-calibration-v4-2-91a3f2837e6b@baylibre.com> References: <20250508-wip-bl-ad7606-calibration-v4-0-91a3f2837e6b@baylibre.com> In-Reply-To: <20250508-wip-bl-ad7606-calibration-v4-0-91a3f2837e6b@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1303; i=adureghello@baylibre.com; h=from:subject:message-id; bh=4Hb5fAw6wk9UOyjGvMGWLBgqM5yKlaYwdF7azoNoMts=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiQaeK3vt9n+1tV3Di9/5Oc2K9Ic+GA1iMWR7On33x84 8zu68ePdZSyMIhxMciKKbLUJUaYhN4OlVJewDgbZg4rE8gQBi5OAZiITQbDP4M/xbWukXt2RIgu cU5kzJyrY8l2uIjx6PvChiq/GV7HhBn+2aYJ/Zlyf1PT5vDHBSXdrD2n7j3h2ZBbxJPZ1ca7IOE hKwA= X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello ADCs as ad7606 implement a phase calibration as a delay. Add such definition, needed for ad7606. Signed-off-by: Angelo Dureghello --- drivers/iio/industrialio-core.c | 1 + include/linux/iio/types.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-cor= e.c index 178e99b111debc59a247fcc3a6037e429db3bebf..f13c3aa470d774bfe655d6a9fb0= 0c263789db637 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -188,6 +188,7 @@ static const char * const iio_chan_info_postfix[] =3D { [IIO_CHAN_INFO_CALIBAMBIENT] =3D "calibambient", [IIO_CHAN_INFO_ZEROPOINT] =3D "zeropoint", [IIO_CHAN_INFO_TROUGH] =3D "trough_raw", + [IIO_CHAN_INFO_CONVDELAY] =3D "convdelay", }; /** * iio_device_id() - query the unique ID for the device diff --git a/include/linux/iio/types.h b/include/linux/iio/types.h index d89982c98368cf72c0fc30fa66ab001e48af4e8b..ad2761efcc8315e1f9907d2a715= 9447fb463333e 100644 --- a/include/linux/iio/types.h +++ b/include/linux/iio/types.h @@ -69,6 +69,7 @@ enum iio_chan_info_enum { IIO_CHAN_INFO_CALIBAMBIENT, IIO_CHAN_INFO_ZEROPOINT, IIO_CHAN_INFO_TROUGH, + IIO_CHAN_INFO_CONVDELAY, }; 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[87.8.31.78]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd363940sm31699665e9.25.2025.05.08.03.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 03:07:26 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 08 May 2025 12:06:07 +0200 Subject: [PATCH v4 3/5] iio: adc: ad7606: add offset and phase calibration support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250508-wip-bl-ad7606-calibration-v4-3-91a3f2837e6b@baylibre.com> References: <20250508-wip-bl-ad7606-calibration-v4-0-91a3f2837e6b@baylibre.com> In-Reply-To: <20250508-wip-bl-ad7606-calibration-v4-0-91a3f2837e6b@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9430; i=adureghello@baylibre.com; h=from:subject:message-id; bh=3PXmVxCz6657mCdpDOhkR+/JCD3hi9i1/g3nOKo+7HM=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiQaeKX37GolbfU+7XPJc1aj5xdRnfW3GC5lvnSpCTCe of1RsfyjlIWBjEuBlkxRZa6xAiT0NuhUsoLGGfDzGFlAhnCwMUpABPZfoDhf/AzDeWkqPVl6k0L Aj7vujDzQ5DRVZ8MgYVKZzlUHPanbWT4KyPVe11kzYYr+hOtLxw+zsP3MuhpfWzzbXve5VazX/3 ZwA4A X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add support for offset and phase calibration, only for devices that support software mode, that are: ad7606b ad7606c-16 ad7606c-18 Tested-by: David Lechner Reviewed-by: Nuno S=C3=A1 Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 160 +++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/iio/adc/ad7606.h | 9 +++ 2 files changed, 169 insertions(+) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 2aa59481c52c07537110e7fc1fd1aedbab6b098d..a986eb1284106da4980ac36cb0b= 5990e4e3bd948 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -95,6 +95,22 @@ static const unsigned int ad7616_oversampling_avail[8] = =3D { 1, 2, 4, 8, 16, 32, 64, 128, }; =20 +static const int ad7606_calib_offset_avail[3] =3D { + -128, 1, 127, +}; + +static const int ad7606c_18bit_calib_offset_avail[3] =3D { + -512, 4, 508, +}; + +static const int ad7606b_calib_phase_avail[][2] =3D { + { 0, 0 }, { 0, 1250 }, { 0, 318750 }, +}; + +static const int ad7606c_calib_phase_avail[][2] =3D { + { 0, 0 }, { 0, 1000 }, { 0, 255000 }, +}; + static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan); static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev, @@ -164,6 +180,8 @@ const struct ad7606_chip_info ad7606b_info =3D { .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606_calib_offset_avail, + .calib_phase_avail =3D ad7606b_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606"); =20 @@ -177,6 +195,8 @@ const struct ad7606_chip_info ad7606c_16_info =3D { .scale_setup_cb =3D ad7606c_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606_calib_offset_avail, + .calib_phase_avail =3D ad7606c_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606"); =20 @@ -226,6 +246,8 @@ const struct ad7606_chip_info ad7606c_18_info =3D { .scale_setup_cb =3D ad7606c_18bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606c_18bit_calib_offset_avail, + .calib_phase_avail =3D ad7606c_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606"); =20 @@ -683,6 +705,40 @@ static int ad7606_scan_direct(struct iio_dev *indio_de= v, unsigned int ch, return ret; } =20 +static int ad7606_get_calib_offset(struct ad7606_state *st, int ch, int *v= al) +{ + int ret; + + ret =3D st->bops->reg_read(st, AD7606_CALIB_OFFSET(ch)); + if (ret < 0) + return ret; + + *val =3D st->chip_info->calib_offset_avail[0] + ret * + st->chip_info->calib_offset_avail[1]; + + return 0; +} + +static int ad7606_get_calib_phase(struct ad7606_state *st, int ch, int *va= l, + int *val2) +{ + int ret; + + ret =3D st->bops->reg_read(st, AD7606_CALIB_PHASE(ch)); + if (ret < 0) + return ret; + + *val =3D 0; + + /* + * ad7606b: phase delay from 0 to 318.75 =CE=BCs in steps of 1.25 =CE=BCs. + * ad7606c-16/18: phase delay from 0 =C2=B5s to 255 =C2=B5s in steps of 1= =C2=B5s. + */ + *val2 =3D ret * st->chip_info->calib_phase_avail[1][1]; + + return 0; +} + static int ad7606_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, @@ -717,6 +773,22 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); *val =3D DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period); return IIO_VAL_INT; + case IIO_CHAN_INFO_CALIBBIAS: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_get_calib_offset(st, chan->scan_index, val); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_get_calib_phase(st, chan->scan_index, val, val2); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + return IIO_VAL_INT_PLUS_NANO; } return -EINVAL; } @@ -767,6 +839,64 @@ static int ad7606_write_os_hw(struct iio_dev *indio_de= v, int val) return 0; } =20 +static int ad7606_set_calib_offset(struct ad7606_state *st, int ch, int va= l) +{ + int start_val, step_val, stop_val; + + start_val =3D st->chip_info->calib_offset_avail[0]; + step_val =3D st->chip_info->calib_offset_avail[1]; + stop_val =3D st->chip_info->calib_offset_avail[2]; + + if (val < start_val || val > stop_val) + return -EINVAL; + + val -=3D start_val; + val /=3D step_val; + + return st->bops->reg_write(st, AD7606_CALIB_OFFSET(ch), val); +} + +static int ad7606_set_calib_phase(struct ad7606_state *st, int ch, int val, + int val2) +{ + int wreg, start_ns, step_ns, stop_ns; + + if (val !=3D 0) + return -EINVAL; + + start_ns =3D st->chip_info->calib_phase_avail[0][1]; + step_ns =3D st->chip_info->calib_phase_avail[1][1]; + stop_ns =3D st->chip_info->calib_phase_avail[2][1]; + + /* + * ad7606b: phase delay from 0 to 318.75 =CE=BCs in steps of 1.25 =CE=BCs. + * ad7606c-16/18: phase delay from 0 =C2=B5s to 255 =C2=B5s in steps of 1= =C2=B5s. + */ + if (val2 < start_ns || val2 > stop_ns) + return -EINVAL; + + wreg =3D val2 / step_ns; + + return st->bops->reg_write(st, AD7606_CALIB_PHASE(ch), wreg); +} + +static int ad7606_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long info) +{ + switch (info) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_SAMP_FREQ: + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + case IIO_CHAN_INFO_CALIBBIAS: + return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: + return IIO_VAL_INT_PLUS_NANO; + default: + return -EINVAL; + } +} + static int ad7606_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, @@ -820,6 +950,18 @@ static int ad7606_write_raw(struct iio_dev *indio_dev, if (val < 0 && val2 !=3D 0) return -EINVAL; return ad7606_set_sampling_freq(st, val); + case IIO_CHAN_INFO_CALIBBIAS: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_set_calib_offset(st, chan->scan_index, val); + iio_device_release_direct(indio_dev); + return ret; + case IIO_CHAN_INFO_CONVDELAY: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_set_calib_phase(st, chan->scan_index, val, val2); + iio_device_release_direct(indio_dev); + return ret; default: return -EINVAL; } @@ -998,6 +1140,14 @@ static int ad7606_read_avail(struct iio_dev *indio_de= v, *type =3D IIO_VAL_INT_PLUS_MICRO; =20 return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_CALIBBIAS: + *vals =3D st->chip_info->calib_offset_avail; + *type =3D IIO_VAL_INT; + return IIO_AVAIL_RANGE; + case IIO_CHAN_INFO_CONVDELAY: + *vals =3D (const int *)st->chip_info->calib_phase_avail; + *type =3D IIO_VAL_INT_PLUS_NANO; + return IIO_AVAIL_RANGE; } return -EINVAL; } @@ -1060,6 +1210,7 @@ static const struct iio_info ad7606_info_sw_mode =3D { .read_raw =3D &ad7606_read_raw, .write_raw =3D &ad7606_write_raw, .read_avail =3D &ad7606_read_avail, + .write_raw_get_fmt =3D ad7606_write_raw_get_fmt, .debugfs_reg_access =3D &ad7606_reg_access, .validate_trigger =3D &ad7606_validate_trigger, .update_scan_mode =3D &ad7606_update_scan_mode, @@ -1252,6 +1403,15 @@ static int ad7606_probe_channels(struct iio_dev *ind= io_dev) chan->info_mask_separate_available |=3D BIT(IIO_CHAN_INFO_SCALE); =20 + if (st->chip_info->calib_offset_avail) { + chan->info_mask_separate |=3D + BIT(IIO_CHAN_INFO_CALIBBIAS) | + BIT(IIO_CHAN_INFO_CONVDELAY); + chan->info_mask_separate_available |=3D + BIT(IIO_CHAN_INFO_CALIBBIAS) | + BIT(IIO_CHAN_INFO_CONVDELAY); + } + /* * All chips with software mode support oversampling, * so we skip the oversampling_available check. And the diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 441e62c521bcbea69b4f70bb2d55f65334d22276..f613583a7fa4095115b0b28e3f8= e51cd32b93524 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -40,6 +40,11 @@ #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) #define AD7606_OS_MODE 0x08 =20 +#define AD7606_CALIB_GAIN(ch) (0x09 + (ch)) +#define AD7606_CALIB_GAIN_MASK GENMASK(5, 0) +#define AD7606_CALIB_OFFSET(ch) (0x11 + (ch)) +#define AD7606_CALIB_PHASE(ch) (0x19 + (ch)) + struct ad7606_state; =20 typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, @@ -61,6 +66,8 @@ typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio= _dev); * @init_delay_ms: required delay in milliseconds for initialization * after a restart * @offload_storagebits: storage bits used by the offload hw implementation + * @calib_offset_avail: pointer to offset calibration range/limits array + * @calib_phase_avail: pointer to phase calibration range/limits array */ struct ad7606_chip_info { unsigned int max_samplerate; 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[87.8.31.78]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd363940sm31699665e9.25.2025.05.08.03.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 03:07:27 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 08 May 2025 12:06:08 +0200 Subject: [PATCH v4 4/5] dt-bindings: iio: adc: adi,ad7606: add gain calibration support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250508-wip-bl-ad7606-calibration-v4-4-91a3f2837e6b@baylibre.com> References: <20250508-wip-bl-ad7606-calibration-v4-0-91a3f2837e6b@baylibre.com> In-Reply-To: <20250508-wip-bl-ad7606-calibration-v4-0-91a3f2837e6b@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2030; i=adureghello@baylibre.com; h=from:subject:message-id; bh=mK1GoQiX2hS20/yC/1czrPjfc5t1uAwSltJDkMx72Mc=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiQaeLn/HnBYqH6+X9lTv882Ez2PTadkePx7Bbbj5ytp 7VW3RBP7yhlYRDjYpAVU2SpS4wwCb0dKqW8gHE2zBxWJpAhDFycAjARWR2G/8UtIUePNRSzbeba /dvxwOpY3qXGAUL3Dvzu8ZcKuOx8SIDhv+d0LeGkEn9ly/qiNy1x6y2Cu4MNSwqTk3e9b8y+fra KFwA= X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add gain calibration support by a per-channel resistor value. Acked-by: Conor Dooley Signed-off-by: Angelo Dureghello --- .../devicetree/bindings/iio/adc/adi,ad7606.yaml | 29 ++++++++++++++++++= ++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 29f12d650442b8ff2eb455306ce59a0e87867ddd..6926f5f090ad6bbbe7bfd9327dc= 5ae17dafcd1fd 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -204,6 +204,15 @@ patternProperties: considered a bipolar differential channel. Otherwise it is bipol= ar single-ended. =20 + adi,rfilter-ohms: + description: + For ADCs that supports gain calibration, this property must be s= et to + the value of the external RFilter resistor. Proper gain error + correction is applied based on this value. + default: 0 + minimum: 0 + maximum: 64512 + required: - reg - bipolar @@ -256,6 +265,25 @@ allOf: properties: adi,oversampling-ratio-gpios: false =20 + - if: + properties: + compatible: + contains: + enum: + - adi,ad7605-4 + - adi,ad7606-4 + - adi,ad7606-6 + - adi,ad7606-8 + - adi,ad7607 + - adi,ad7608 + - adi,ad7609 + - adi,ad7616 + then: + patternProperties: + "^channel@[0-9a-f]+$": + properties: + adi,rfilter-ohms: false + - if: properties: compatible: @@ -398,6 +426,7 @@ examples: reg =3D <8>; diff-channels =3D <8 8>; bipolar; + adi,rfilter-ohms =3D <2048>; }; =20 }; --=20 2.49.0 From nobody Tue Dec 16 05:57:00 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3715221FAA for ; Thu, 8 May 2025 10:07:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746698854; cv=none; b=aW19HOtdFl8SzlJvaDeB86JLgrYEFkzNkB9RgrkWiuPaaGDBuetKOtBlj6GUVKJvvq+t4AaXS8fFRTn9cZOCTCTgl6EgBDVfCoIbJA2WHANbMlM9rzhgKsc7aZybKqzBoIRx0ZbttJ2UkUC9mbGrcVBISY9hCR97Kpq+NvvmMlk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746698854; c=relaxed/simple; bh=LaGh0Kujnup56yjDawQUQI97S1eYBLbTsxHVwVAGhQA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WBktE23t5oLvaENfEzTwBWux3NqfLo7jFoelvIs9b+yQwGXRA3P1qzVZiHqFVAEV3iPQNlRpYv0/D3BQUf/jv4AhmWPZuaQyza0E0cHuviVZPk5t6L/CJehumZrgrdWwW2at3jWuKrbe64V89lCqxllhPVDehDWwdouU9woV6bs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=F9211VZI; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="F9211VZI" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-43d0782d787so5324675e9.0 for ; Thu, 08 May 2025 03:07:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1746698851; x=1747303651; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RCwW3EHexWqSBzmEUcVwhny0/+RhPmV0FH0hxwaO9ag=; b=F9211VZIiZdRmIMOTtLPe0cNGq8CVcGCgaW4uJNbJeCa0Awc9kYMvYrZnjanAYndCa iHE0zwoja5nQ4FgifeOrpFm7a45h/3I2szXcBurtWIwggkQbE4sHx4YKYUFcAj9dwK/M kqpsZFC4zNec7SD17AlC0qJQ1iAyL96Fb4HEVUZd/qqcmWa0A6hNxAqiHol2CqIXdAAV umB3vmL5Qsn0tYkK49vsOfZcDxQ5bQX7g2yZH4XCA+MFIaNnqYb/9/UObNIzdYlrT33w 9rp6A6vU0/VUuo5awiLQ498H1a93AWaTEGcULirSANcilmClVUSRAuUr31QRi7BuvDge +JPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746698851; x=1747303651; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RCwW3EHexWqSBzmEUcVwhny0/+RhPmV0FH0hxwaO9ag=; b=tEv1OoXjPiioVJ96TkDHxd7NuZoQ1hlrw3BuerojJ8HWejn6NNgTvMhFFr6CDQm58c DB37ameFGLFTMU545S6HbkLuKnBsdwGmR9Droucr2Ctlee/wd2S9/MxH6PRib9vFzrcK TACPfJ2inms3jMzBPa+5dLwRdDtDRqvOeNV4Zz5YoWYQyxhnVNOfU/mUaKmsg6Lnsxjj d1ooCVwQjdezUmRegG+xr6DgsKtTsn3rkcuF9BJzpYZoZDAjbPHAsIf+xk8TFL6/eAia VRnk103yBM6Y1YCVrVaHKvQvm/ezzcPtj6ZpDBbczQGXSQ7o66GejG/IBPjrzYODsOtc GbZA== X-Forwarded-Encrypted: i=1; AJvYcCWLVjTcYzhHaViP4bW9m1u9GqM43Jc9E6aW3ysntQAd3bcsO+SQn0jyceDxt5H/K5xl2VPMuftpzChYhRs=@vger.kernel.org X-Gm-Message-State: AOJu0Yws6amDPE/F1Ugf8YdYJKsrEkU692ynGDAFIJPXlx1slkpq8kX6 C05xKmfvRSFYb423Dv1rXRi1akJGOYHDvjfRTqb4RvXmIEXh3Rzwn6hvadcuoqY= X-Gm-Gg: ASbGncuRb73yAT6fkYJwG1iJc+D2d9Cb6xPKu4B39OVenJqcIyhLuKIgTZVesr3zFLL XxPpwE0VE/P3zD0y738OR3CLO0StRNzvciFMcVCysaatBoL8yKnCgUaoa2+WzI160nTrLfVY5OQ D5arlzGUxNIq26C9WH8qI8EC+NabfeIOvuFuvLxoffNDv5eyKCMVm2U1YPpqjhl2NRzWt+Tdj51 nRZ9ymQUBdNKQR0tqQ6ivCUE8E4WNyd7G7rTIpnHBbGkLgvCDsd3cZi0gW+rqhZ//8XKMFLPVaG X2drnsQQT9Xrt+Q36Xba1q2YCIeKWFZCrF5nVrmL0AuIhup+0ZW8nGcLcBCxHwv0eODBccr8FxJ ZbRG482p6fs1S X-Google-Smtp-Source: AGHT+IFHXa2KsEyS/1hw19kNchTVBACJ7US3YxgxvrYog0GndSzf22ZeUUFPoP0SJ8iME5FDsfeUEA== X-Received: by 2002:a05:600d:1b:b0:43c:ef55:f1e8 with SMTP id 5b1f17b1804b1-442d19207ebmr19677655e9.13.1746698851008; Thu, 08 May 2025 03:07:31 -0700 (PDT) Received: from [192.168.0.2] (host-87-8-31-78.retail.telecomitalia.it. [87.8.31.78]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd363940sm31699665e9.25.2025.05.08.03.07.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 03:07:30 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 08 May 2025 12:06:09 +0200 Subject: [PATCH v4 5/5] iio: adc: ad7606: add gain calibration support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250508-wip-bl-ad7606-calibration-v4-5-91a3f2837e6b@baylibre.com> References: <20250508-wip-bl-ad7606-calibration-v4-0-91a3f2837e6b@baylibre.com> In-Reply-To: <20250508-wip-bl-ad7606-calibration-v4-0-91a3f2837e6b@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5809; i=adureghello@baylibre.com; h=from:subject:message-id; bh=V2tKK2iV+MzCpP+CvjJLJlOfjDRuO88z48EIieZNapU=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiQaRKo7pqUESMewPJdQdv+4mcX7oToq+uOqIYznC9qW MuoneHYUcrCIMbFICumyFKXGGESejtUSnkB42yYOaxMIEMYuDgFYCI3LjH8D+iz/X9Q5Pip+Hdz Izu17933+JpTY5inWMhiLSG35OaTDQx/pV9qNvJ9e8b0Xl+t/tjC3guPBO9dkCxZ/nWzUaDfAqP 5DAA= X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add gain calibration support, using resistor values set on devicetree, values to be set accordingly with ADC external RFilter, as explained in the ad7606c-16 datasheet, rev0, page 37. Usage example in the fdt yaml documentation. Tested-by: David Lechner Reviewed-by: Nuno S=C3=A1 Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 61 ++++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/iio/adc/ad7606.h | 3 +++ 2 files changed, 64 insertions(+) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index a986eb1284106da4980ac36cb0b5990e4e3bd948..be86e14ba85d07398e870ad6807= 64958aa6ef471 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -33,6 +33,10 @@ =20 #include "ad7606.h" =20 +#define AD7606_CALIB_GAIN_MIN 0 +#define AD7606_CALIB_GAIN_STEP 1024 +#define AD7606_CALIB_GAIN_MAX (63 * AD7606_CALIB_GAIN_STEP) + /* * Scales are computed as 5000/32768 and 10000/32768 respectively, * so that when applied to the raw values they provide mV values. @@ -125,6 +129,7 @@ static int ad7609_chan_scale_setup(struct iio_dev *indi= o_dev, struct iio_chan_spec *chan); static int ad7616_sw_mode_setup(struct iio_dev *indio_dev); static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev); +static int ad7606_chan_calib_gain_setup(struct iio_dev *indio_dev); =20 const struct ad7606_chip_info ad7605_4_info =3D { .max_samplerate =3D 300 * KILO, @@ -180,6 +185,7 @@ const struct ad7606_chip_info ad7606b_info =3D { .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606_calib_offset_avail, .calib_phase_avail =3D ad7606b_calib_phase_avail, }; @@ -195,6 +201,7 @@ const struct ad7606_chip_info ad7606c_16_info =3D { .scale_setup_cb =3D ad7606c_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606_calib_offset_avail, .calib_phase_avail =3D ad7606c_calib_phase_avail, }; @@ -246,6 +253,7 @@ const struct ad7606_chip_info ad7606c_18_info =3D { .scale_setup_cb =3D ad7606c_18bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606c_18bit_calib_offset_avail, .calib_phase_avail =3D ad7606c_calib_phase_avail, }; @@ -357,6 +365,52 @@ static int ad7606_get_chan_config(struct iio_dev *indi= o_dev, int ch, return 0; } =20 +static int ad7606_chan_calib_gain_setup(struct iio_dev *indio_dev) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + unsigned int num_channels =3D st->chip_info->num_adc_channels; + struct device *dev =3D st->dev; + int ret; + + /* + * This function is called once, and parses all the channel nodes, + * so continuing on next channel node on errors, informing of them. + */ + device_for_each_child_node_scoped(dev, child) { + u32 reg, r_gain; + + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret) + continue; + + /* Chan reg is a 1-based index. */ + if (reg < 1 || reg > num_channels) { + dev_warn(dev, "wrong ch number (ignoring): %d\n", reg); + continue; + } + + ret =3D fwnode_property_read_u32(child, "adi,rfilter-ohms", + &r_gain); + if (ret) + /* Keep the default register value. */ + continue; + + if (r_gain > AD7606_CALIB_GAIN_MAX) { + dev_warn(dev, "wrong gain calibration value"); + continue; + } + + ret =3D st->bops->reg_write(st, AD7606_CALIB_GAIN(reg - 1), + DIV_ROUND_CLOSEST(r_gain, AD7606_CALIB_GAIN_STEP)); + if (ret) { + dev_warn(dev, "error writing r_gain"); + continue; + } + } + + return 0; +} + static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan) { @@ -1448,6 +1502,13 @@ static int ad7606_probe_channels(struct iio_dev *ind= io_dev) if (slow_bus) channels[i] =3D (struct iio_chan_spec)IIO_CHAN_SOFT_TIMESTAMP(i); =20 + /* Setting up gain calibration for all channels. */ + if (st->sw_mode_en && st->chip_info->calib_offset_avail) { + ret =3D st->chip_info->calib_gain_setup_cb(indio_dev); + if (ret) + return ret; + } + indio_dev->channels =3D channels; =20 return 0; diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index f613583a7fa4095115b0b28e3f8e51cd32b93524..6313eea2bd0ccf97222a50dc26d= 8ec65042d0db7 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -50,6 +50,7 @@ struct ad7606_state; typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, struct iio_chan_spec *chan); typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio_dev); +typedef int (*ad7606_calib_gain_setup_cb_t)(struct iio_dev *indio_dev); =20 /** * struct ad7606_chip_info - chip specific information @@ -66,6 +67,7 @@ typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio= _dev); * @init_delay_ms: required delay in milliseconds for initialization * after a restart * @offload_storagebits: storage bits used by the offload hw implementation + * @calib_gain_setup_cb: callback to setup of gain calibration * @calib_offset_avail: pointer to offset calibration range/limits array * @calib_phase_avail: pointer to phase calibration range/limits array */ @@ -81,6 +83,7 @@ struct ad7606_chip_info { bool os_req_reset; unsigned long init_delay_ms; u8 offload_storagebits; + ad7606_calib_gain_setup_cb_t calib_gain_setup_cb; const int *calib_offset_avail; const int (*calib_phase_avail)[2]; }; --=20 2.49.0