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Thu, 8 May 2025 19:49:07 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 734E8480044; Thu, 08 May 2025 19:49:07 +0200 (CEST) From: Sebastian Reichel Date: Thu, 08 May 2025 19:48:53 +0200 Subject: [PATCH v2 4/5] arm64: dts: rockchip: add Rock 5B+ Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250508-rock5bp-for-upstream-v2-4-677033cc1ac2@kernel.org> References: <20250508-rock5bp-for-upstream-v2-0-677033cc1ac2@kernel.org> In-Reply-To: <20250508-rock5bp-for-upstream-v2-0-677033cc1ac2@kernel.org> To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; 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fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Add ROCK 5B+, which is an improved version of the ROCK 5B with the following changes: * Memory LPDDR4X -> LPDDR5 * HDMI input connector size * eMMC socket -> onboard * M.2 E-Key is replaced by onboard RTL8852BE WLAN/BT * M.2 M-Key 1x4 lanes is replaced by 2x2 lanes * Added M.2 B-Key for USB connected WWAN modules (untested) * Add second camera port (not yet supported in upstream Linux) * Add dedicated USB-C port for device power (no impact in DT; the existing port has not been changed and the new port is handled by CH224D standalone chip) Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-rock-5b-plus.dts | 113 +++++++++++++++++= ++++ 2 files changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 7948522cb225cbbe54099fb7537fc70357164f13..7a05bd885d5ecb96c3decbd3f48= 3a6c58b81e0ab 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -165,6 +165,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5-itx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b-pcie-ep.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b-pcie-srns.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-tiger-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-toybrick-x0.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts b/arch/ar= m64/boot/dts/rockchip/rk3588-rock-5b-plus.dts new file mode 100644 index 0000000000000000000000000000000000000000..74c7b6502e4dda4b774f43c704e= baee350703c0d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3588-rock-5b.dtsi" + +/ { + model =3D "Radxa ROCK 5B+"; + compatible =3D "radxa,rock-5b-plus", "rockchip,rk3588"; + + rfkill-wwan { + compatible =3D "rfkill-gpio"; + label =3D "rfkill-m2-wwan"; + radio-type =3D "wwan"; + shutdown-gpios =3D <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + + vcc3v3_4g: regulator-vcc3v3-4g { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + /* pinctrl for the GPIO is requested by vcc3v3_pcie2x1l0 */ + regulator-name =3D "vcc3v3_4g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <50000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_wwan_pwr: regulator-vcc3v3-wwan { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wwan_power_en>; + regulator-name =3D "vcc3v3_wwan_pwr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc3v3_4g>; + }; +}; + +&gpio0 { + wwan-disable2-n-hog { + gpios =3D ; + output-low; + line-name =3D "M.2 B-key W_DISABLE2#"; + gpio-hog; + }; +}; + +&gpio2 { + wwan-reset-n-hog { + gpios =3D ; + output-low; + line-name =3D "M.2 B-key RESET#"; + gpio-hog; + }; + + wwan-wake-n-hog { + gpios =3D ; + input; + line-name =3D "M.2 B-key WoWWAN#"; + gpio-hog; + }; +}; + +&pcie30phy { + data-lanes =3D <1 1 2 2>; +}; + +&pcie3x2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie3x2_rst>; + reset-gpios =3D <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie30>; + status =3D "okay"; +}; + +&pcie3x4 { + num-lanes =3D <2>; +}; + +&pinctrl { + wwan { + wwan_power_en: wwan-pwr-en { + rockchip,pins =3D <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3x2_rst: pcie3x2-rst { + rockchip,pins =3D <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins =3D <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc5v0_host { + enable-active-high; + gpio =3D <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_host_en>; +}; --=20 2.47.2