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[46.193.69.61]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a099b178absm19500236f8f.97.2025.05.08.00.10.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 00:10:35 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 08 May 2025 12:40:30 +0530 Subject: [PATCH v4 1/5] PCI/ERR: Remove misleading TODO regarding kernel panic Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250508-pcie-reset-slot-v4-1-7050093e2b50@linaro.org> References: <20250508-pcie-reset-slot-v4-0-7050093e2b50@linaro.org> In-Reply-To: <20250508-pcie-reset-slot-v4-0-7050093e2b50@linaro.org> To: Mahesh J Salgaonkar , Oliver O'Halloran , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Zhou Wang , Will Deacon , Robert Richter , Alyssa Rosenzweig , Marc Zyngier , Conor Dooley , Daire McNamara Cc: dingwei@marvell.com, cassel@kernel.org, Lukas Wunner , Krishna Chaitanya Chundru , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=789; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=Aq+BoDTRwjfmiHKRLtODTEbwNFS8yDdFMEIJ4A/Pkz4=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBoHFjp3+Y0C7nYToqJfWiLXSkKAM5YKgVxrQcgv dew07ahS2+JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaBxY6QAKCRBVnxHm/pHO 9bheB/9ACtGdPZ3LmfihI48+MK1ALP0+Bx6+UetxxXKaahBYzIQ5gDCkxVfgOgnxWWQewlNuhzp LkZw3nCIYvdYAZ7/RT6FkDdBk4lRXh8t4QhrVlil8KmoN8umYdxyDDZutpu8RDRf9b5H84xabGV tt9QfWQz9sKtIRWtac2DBCJCM4vwuvtSDxEUlUvJkdec5PwCN8ffMmJBN3NQ+vSvJtmkY8CKX8o ZT1VVrEU3tuPcd3IaetbkOs7WBG2+W8B9TJkzU8p+4MnsQUmp41iy5Y6yO6mf3fDQ643DyRvmm+ 9X9+lTcKXgUsmH6hLBn6yhdJdN2ABj8XC+7vLejHvCUqYl4/ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 A PCI device is just another peripheral in a system. So failure to recover it, must not result in a kernel panic. So remove the TODO which is quite misleading. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Kuppuswamy Sathyanarayanan=20 Reviewed-by: Wilfred Mallawa --- drivers/pci/pcie/err.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index 31090770fffcc94e15ba6e89f649c6f84bfdf0d5..de6381c690f5c21f00021cdc7bd= e8d93a5c7db52 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -271,7 +271,6 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, =20 pci_uevent_ers(bridge, PCI_ERS_RESULT_DISCONNECT); =20 - /* TODO: Should kernel panic here? */ pci_info(bridge, "device recovery failed\n"); =20 return status; --=20 2.43.0 From nobody Thu Dec 18 03:20:34 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0792321D3D1 for ; Thu, 8 May 2025 07:10:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746688242; cv=none; b=e8rJTjH3QgX5dk4v1r3jzTNNWbDtA2hcX91UOmAky34HtG7vKan4CuXg4pkLO99T/WalYgTlqQUg0PEpOnSUPSzC7Ut5Q+R3mvhA+nuwc8/X0zMFnZtgFIv7pvf8ZItRqjr2OI3mR8z6FSiCfzCOgL0btw2CGuO3adnkDuDXN1Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746688242; c=relaxed/simple; bh=DxjgbttCz+WbWbTBQh3uh5PZxc6tk82mAeHt4QTMKaE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VgyH8NQGFFAEyPZ2TwNZSzrjoIpO85DPmu+jVvCbRqJH3AmEhECOFWDru/R6KoJ6gLNwbZWEVI36T7E/1ds0vXeizTv4DWATqyQ0e+Rszq6tDDcATwHy/YIc/h/kEoMrCqQIO9v6ISj8RbIObatuXEq+TYPexSCYtR9l4/vAG7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=TZugPGOn; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TZugPGOn" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-43edecbfb94so7315615e9.1 for ; Thu, 08 May 2025 00:10:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746688237; x=1747293037; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=z2xdDt4RdWfJikzYadK7Wm2Dj/LeNHY+o4TedGbXhPE=; b=TZugPGOnAnizTz7qkXkQGx3EpoBd+ZlQRTwhHexL/wf/YDJkBZi30eD7DJP353jows +unNSGkhyxsntZ2vAbJuF3Y89HZgyjrmkMPTY7GH6Vkbsbnoggh0aCK+jYBj+0zojwB3 +S3tnp4VoJvh7VEn7+0zoFC4U8oH3feZVbWI4tsSYHo/C8uki3XFvoX/ZJlSk0hykgXK afn70pzSJZcE7FS0cPl95q79TuX6JvpbydvWG2yKGhNrAarV2Js1tRzORyOtolPzpvhO YNQg4AhuDAdw13FWfuRbC6JfIkJIMs0ng24eeDC287Q99tOY9mEwkOHL3fmeCh7uYTKR /ptQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746688237; x=1747293037; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z2xdDt4RdWfJikzYadK7Wm2Dj/LeNHY+o4TedGbXhPE=; b=jZeTIRfCTOk6MKAuagapHIOG152436ecPLHJMzGsPDEbDmVVafRgPIzeFd/Qhml+Ej S0pfBmSUz7gGTf22a+lhZT3A0hho1OFlnRUjSIjJWCO3oXfndUNLEgnDm95yySC+hgCQ Oo9VdGMGwCc6A9hBK/LJnTb6tx8oOBNiDRG4lxoSjFjp1mz065mmHxs0Ip+Y4/iR0mFW VsSQEHk27geWDRfSeWeNhzu43rx+8iVcZKh9I3dK/xZ3Sj9AvhAcO8gfmpKSRxU+XFFY 0YYipXJAWVKlmuIW6RTr4zU6xTb9w/2PQMs7UoD9Z6G4/gLUkhTCUDxi5CTBJdgeAIZs sUlQ== X-Forwarded-Encrypted: i=1; AJvYcCX4362O/OjLS6X6YIC2j1PeKyQeEDG0Trdtue/y+cyHBW4lK/smG/Vy3EuysW/Exp03pY6AroXTgq0ECs4=@vger.kernel.org X-Gm-Message-State: AOJu0YycTqTimHRozNXWfkS09YOBnaPOIKj043xwru4dbFftK3zel388 v9Dbv2pZv2D5/knppGamVwdM+APoPa2Xp6ACHj8q0DEEE+nJSMOyR9/PXTr7gw== X-Gm-Gg: ASbGncvZXgt1yVmXfBsFriBE1rD2Ps4fzDFS/LLSIxa4pMN91C0gVAulCiTujU+b47q 1F1F4HXCPLud2FvrArIXS5dxD78chRsQCzWu0w4zfub+lKDnOdaRY6A3eiR6fl9YhHpBa/mHelK VqElddfH42G/M3Q1G9Y9BNQqpD5rCzMCW5+u95ssTrIcnhbg66VhzK24IpRFu0fe06TLQQ67CXK bS7nkOJBzQN0wk1/dN056TVRlvp5TGhvDql4cwwL/qaxIB9NS9xED1cRNDu9/h3Kzw27oQXnEbr FVyBVtJXn5NHfXsou+lc6zyW9SSndj0RZ2gnvmK5HYnoDKU48WDs+muOPeCYrBHc5p/2T4kO7fO 2o8q3SYG9BZvrAS/lucfJB1n14mruYgrUf8x1WA== X-Google-Smtp-Source: AGHT+IFU6Tfiix8kiA6qL1KyPENFK6H5A0dQpfBujyLXJD3m07n9Que2XUBEh0Jtu1ubwVrnoTFrSw== X-Received: by 2002:a05:600c:3d9b:b0:43c:f629:66f3 with SMTP id 5b1f17b1804b1-442d02f421emr16664105e9.18.1746688237328; Thu, 08 May 2025 00:10:37 -0700 (PDT) Received: from [127.0.1.1] (cust-east-par-46-193-69-61.cust.wifirst.net. [46.193.69.61]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a099b178absm19500236f8f.97.2025.05.08.00.10.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 00:10:36 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 08 May 2025 12:40:31 +0530 Subject: [PATCH v4 2/5] PCI/ERR: Add support for resetting the slots in a platform specific way Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250508-pcie-reset-slot-v4-2-7050093e2b50@linaro.org> References: <20250508-pcie-reset-slot-v4-0-7050093e2b50@linaro.org> In-Reply-To: <20250508-pcie-reset-slot-v4-0-7050093e2b50@linaro.org> To: Mahesh J Salgaonkar , Oliver O'Halloran , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Zhou Wang , Will Deacon , Robert Richter , Alyssa Rosenzweig , Marc Zyngier , Conor Dooley , Daire McNamara Cc: dingwei@marvell.com, cassel@kernel.org, Lukas Wunner , Krishna Chaitanya Chundru , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2766; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=DxjgbttCz+WbWbTBQh3uh5PZxc6tk82mAeHt4QTMKaE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBoHFjpfv/vQkWgyV/Hq0GucliJi+U/7FE1Skrvp pJ+nrHeneGJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaBxY6QAKCRBVnxHm/pHO 9UI+CACk0xFNBFRLakdLLAf9Ya1C7nW/+a/VQ4SxfviZzgiZSwQ3wAKQ1nn3pFJTctodOrYHrYt L3jspau7qSV/E69KaX8cHFBStVMmk8Ey9z4rzTqwgNJTiZu1osrkc0SiKydSeqMot1pRreGsKhv w6jmJPaJL6AL5/Wc44rKPtCqMktlSapMC4oZdAwUzr+ZolkNNdqp3Ptf12CclgABbIy0YDvrotC GnquyUFgI1V0jIOUvvcsv/n1eLtFUktxnxLDS83usEfAJ1WpRavyboLRCrmQ1K00Gvk58fZaWkN /w9ORtH6GykTqjVpzegZfHZz6+OjWKawa8B4PrmHhI29wJoR X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Some host bridge devices require resetting the slots in a platform specific way to recover them from error conditions such as Fatal AER errors, Link Down etc... So introduce pci_host_bridge::reset_slot callback and call it from pcibios_reset_secondary_bus() if available. The 'reset_slot' callback is responsible for resetting the given slot referenced by the 'pci_dev' pointer in a platform specific way and bring it back to the working state if possible. If any error occurs during the slot reset operation, relevant errno should be returned. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krishna Chaitanya Chundru Reviewed-by: Kuppuswamy Sathyanarayanan=20 Reviewed-by: Lukas Wunner Tested-by: Wilfred Mallawa --- drivers/pci/pci.c | 12 ++++++++++++ drivers/pci/pcie/err.c | 5 ----- include/linux/pci.h | 1 + 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4d7c9f64ea24ec754a135a2585c99489cfa641a9..13709bb898a967968540826a2b7= ee8ade6b7e082 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4982,7 +4982,19 @@ void pci_reset_secondary_bus(struct pci_dev *dev) =20 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) { + struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); + int ret; + + if (host->reset_slot) { + ret =3D host->reset_slot(host, dev); + if (ret) + pci_err(dev, "failed to reset slot: %d\n", ret); + + return; + } + pci_reset_secondary_bus(dev); + } =20 /** diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index de6381c690f5c21f00021cdc7bde8d93a5c7db52..b834fc0d705938540d3d7d3d873= 9770c09fe7cf1 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -234,11 +234,6 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, } =20 if (status =3D=3D PCI_ERS_RESULT_NEED_RESET) { - /* - * TODO: Should call platform-specific - * functions to reset slot before calling - * drivers' slot_reset callbacks? - */ status =3D PCI_ERS_RESULT_RECOVERED; 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[46.193.69.61]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a099b178absm19500236f8f.97.2025.05.08.00.10.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 00:10:37 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 08 May 2025 12:40:32 +0530 Subject: [PATCH v4 3/5] PCI: host-common: Make the driver as a common library for host controller drivers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250508-pcie-reset-slot-v4-3-7050093e2b50@linaro.org> References: <20250508-pcie-reset-slot-v4-0-7050093e2b50@linaro.org> In-Reply-To: <20250508-pcie-reset-slot-v4-0-7050093e2b50@linaro.org> To: Mahesh J Salgaonkar , Oliver O'Halloran , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Zhou Wang , Will Deacon , Robert Richter , Alyssa Rosenzweig , Marc Zyngier , Conor Dooley , Daire McNamara Cc: dingwei@marvell.com, cassel@kernel.org, Lukas Wunner , Krishna Chaitanya Chundru , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7440; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=9YTGSyyEjJBWzKcv9X508Ju9+VcoznZB2wd8RCZhBIA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBoHFjp1kFqMhXSTF/eBh/n6fZtF2vM5B0B0c5Ul nv49HMJlUuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaBxY6QAKCRBVnxHm/pHO 9du0B/sGQkAQ1jOTMZmz5FNWat7V9HdLSW4K3BY3FD4mEBtb8jIpZDNiJTYBb085icKcXYPQ31M FICFZzr47/EPEyJr5oHdHiHCT8+qdsDKMOpTy2RdIU+iNDY9GUhOtVFVMU28cHFcQsNAtOKy2kx 6Qf1JpijCSxiu+KVABIWBz/rhP8pvPTX2kP+U22LEeMkDtoPjU0HsKK9f3VWPQbHlWZlbO8zQtn G889qzgpaWL0nyW20O6LrdnY/6FAo53jRjxSzQvt9/ufEIqUyTj51abVn0y2cNfYfLC+v1SLdW7 HtCcl1pwMCMjjs3Q5IGertLvu1r/cz+TfDDhWWGVtWqkYZCl X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 This common library will be used as a placeholder for helper functions shared by the host controller drivers. This avoids placing the host controller drivers specific helpers in drivers/pci/*.c, to avoid enlarging the kernel Image on platforms that do not use host controller drivers at all (like x86/ACPI platforms). Suggested-by: Lukas Wunner Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/Kconfig | 8 ++++---- drivers/pci/controller/dwc/pcie-hisi.c | 1 + drivers/pci/controller/pci-host-common.c | 6 ++++-- drivers/pci/controller/pci-host-common.h | 16 ++++++++++++++++ drivers/pci/controller/pci-host-generic.c | 2 ++ drivers/pci/controller/pci-thunder-ecam.c | 2 ++ drivers/pci/controller/pci-thunder-pem.c | 1 + drivers/pci/controller/pcie-apple.c | 2 ++ drivers/pci/controller/plda/pcie-microchip-host.c | 1 + include/linux/pci-ecam.h | 6 ------ 10 files changed, 33 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 9800b768105402d6dd1ba4b134c2ec23da6e4201..9bb8bf669a807272777b6168d04= 2f8fd7490aeec 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -3,6 +3,10 @@ menu "PCI controller drivers" depends on PCI =20 +config PCI_HOST_COMMON + tristate + select PCI_ECAM + config PCI_AARDVARK tristate "Aardvark PCIe controller" depends on (ARCH_MVEBU && ARM64) || COMPILE_TEST @@ -119,10 +123,6 @@ config PCI_FTPCI100 depends on OF default ARCH_GEMINI =20 -config PCI_HOST_COMMON - tristate - select PCI_ECAM - config PCI_HOST_GENERIC tristate "Generic PCI host controller" depends on OF diff --git a/drivers/pci/controller/dwc/pcie-hisi.c b/drivers/pci/controlle= r/dwc/pcie-hisi.c index 8904b5b85ee589576afcb6c81bb4bd39ff960c15..3c17897e56fcb60ec08cf522ee1= 485f90a2f36a3 100644 --- a/drivers/pci/controller/dwc/pcie-hisi.c +++ b/drivers/pci/controller/dwc/pcie-hisi.c @@ -15,6 +15,7 @@ #include #include #include "../../pci.h" +#include "../pci-host-common.h" =20 #if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PC= I_QUIRKS)) =20 diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/control= ler/pci-host-common.c index f441bfd6f96a8bde1c07fcf97d43d0693c424a27..f93bc7034e697250711833a5151= f7ef177cd62a0 100644 --- a/drivers/pci/controller/pci-host-common.c +++ b/drivers/pci/controller/pci-host-common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Generic PCI host driver common code + * Common library for PCI host controller drivers * * Copyright (C) 2014 ARM Limited * @@ -15,6 +15,8 @@ #include #include =20 +#include "pci-host-common.h" + static void gen_pci_unmap_cfg(void *ptr) { pci_ecam_free((struct pci_config_window *)ptr); @@ -94,5 +96,5 @@ void pci_host_common_remove(struct platform_device *pdev) } EXPORT_SYMBOL_GPL(pci_host_common_remove); =20 -MODULE_DESCRIPTION("Generic PCI host common driver"); +MODULE_DESCRIPTION("Common library for PCI host controller drivers"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/pci/controller/pci-host-common.h b/drivers/pci/control= ler/pci-host-common.h new file mode 100644 index 0000000000000000000000000000000000000000..d8be024ca68d43afb147fd9104d= 632b907277144 --- /dev/null +++ b/drivers/pci/controller/pci-host-common.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Common library for PCI host controller drivers + * + * Copyright (C) 2014 ARM Limited + * + * Author: Will Deacon + */ + +#ifndef _PCI_HOST_COMMON_H +#define _PCI_HOST_COMMON_H + +int pci_host_common_probe(struct platform_device *pdev); +void pci_host_common_remove(struct platform_device *pdev); + +#endif diff --git a/drivers/pci/controller/pci-host-generic.c b/drivers/pci/contro= ller/pci-host-generic.c index 4051b9b61dace669422e5a6453cc9f58a081beb5..c1bc0d34348f44c9fdd549811f6= 37fb50fe89c64 100644 --- a/drivers/pci/controller/pci-host-generic.c +++ b/drivers/pci/controller/pci-host-generic.c @@ -14,6 +14,8 @@ #include #include =20 +#include "pci-host-common.h" + static const struct pci_ecam_ops gen_pci_cfg_cam_bus_ops =3D { .bus_shift =3D 16, .pci_ops =3D { diff --git a/drivers/pci/controller/pci-thunder-ecam.c b/drivers/pci/contro= ller/pci-thunder-ecam.c index 08161065a89c35a95714df935ef437dfc8845697..b5b4a958e6a22b21501cad45bb2= 42a95a784efc1 100644 --- a/drivers/pci/controller/pci-thunder-ecam.c +++ b/drivers/pci/controller/pci-thunder-ecam.c @@ -11,6 +11,8 @@ #include #include =20 +#include "pci-host-common.h" + #if defined(CONFIG_PCI_HOST_THUNDER_ECAM) || (defined(CONFIG_ACPI) && defi= ned(CONFIG_PCI_QUIRKS)) =20 static void set_val(u32 v, int where, int size, u32 *val) diff --git a/drivers/pci/controller/pci-thunder-pem.c b/drivers/pci/control= ler/pci-thunder-pem.c index f1bd5de67997cddac173723bc7f4ec20aaf20064..5fa037fb61dc356f3029d1b5cae= 632ae1da5bb9b 100644 --- a/drivers/pci/controller/pci-thunder-pem.c +++ b/drivers/pci/controller/pci-thunder-pem.c @@ -14,6 +14,7 @@ #include #include #include "../pci.h" +#include "pci-host-common.h" =20 #if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defin= ed(CONFIG_PCI_QUIRKS)) =20 diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/p= cie-apple.c index 18e11b9a7f46479348815c3f706319189e0a80b5..edd4c8c683c6a693401b47f5f05= 6641c13ae89f8 100644 --- a/drivers/pci/controller/pcie-apple.c +++ b/drivers/pci/controller/pcie-apple.c @@ -29,6 +29,8 @@ #include #include =20 +#include "pci-host-common.h" + #define CORE_RC_PHYIF_CTL 0x00024 #define CORE_RC_PHYIF_CTL_RUN BIT(0) #define CORE_RC_PHYIF_STAT 0x00028 diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pc= i/controller/plda/pcie-microchip-host.c index 3fdfffdf027001bf88df8e1c2538587298228220..24bbf93b8051fa0d9027ce6983e= ae34cad81065e 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -23,6 +23,7 @@ #include =20 #include "../../pci.h" +#include "../pci-host-common.h" #include "pcie-plda.h" =20 #define MC_MAX_NUM_INBOUND_WINDOWS 8 diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h index 3a10f8cfc3ad5c90585a8fc971be714011ed18fe..d930651473b4d0b406e657a24ed= e87e09517d091 100644 --- a/include/linux/pci-ecam.h +++ b/include/linux/pci-ecam.h @@ -93,10 +93,4 @@ extern const struct pci_ecam_ops al_pcie_ops; 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[46.193.69.61]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a099b178absm19500236f8f.97.2025.05.08.00.10.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 00:10:38 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 08 May 2025 12:40:33 +0530 Subject: [PATCH v4 4/5] PCI: host-common: Add link down handling for host bridges Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250508-pcie-reset-slot-v4-4-7050093e2b50@linaro.org> References: <20250508-pcie-reset-slot-v4-0-7050093e2b50@linaro.org> In-Reply-To: <20250508-pcie-reset-slot-v4-0-7050093e2b50@linaro.org> To: Mahesh J Salgaonkar , Oliver O'Halloran , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Zhou Wang , Will Deacon , Robert Richter , Alyssa Rosenzweig , Marc Zyngier , Conor Dooley , Daire McNamara Cc: dingwei@marvell.com, cassel@kernel.org, Lukas Wunner , Krishna Chaitanya Chundru , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5013; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=3LL1EMi315Z/B5zK3zsxrKW113WDL+SEaQ+1pl/P2Rg=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBoHFjpL07zvpNmz80RZq+CJ23rDNKQ4rbWHFYvk WEYaovGi+WJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaBxY6QAKCRBVnxHm/pHO 9TldB/0enq4tJZ2uTvuG8JYQU+8hIIEyWbBv64ohIiJ9BqvlzzpZxAmt8uyb0qahy2kubec5Boj avyvEzax3nAwi5ldUbHq7FXTSTXx8LCRlABHPcw9wmG91cGx16OfkgnM3FUKgIfEO9YVsD65aVW hB3ecw9FGLzTLX/x2ywNimLi3H2pQK5LFPgsfYyWd54qJ+oWgFNzT/OXKVDjzrgDDKMskxj2P7p QJ7/UAOOlUhxcSmCfawGsRN43aCRDBvW4uO0c6YViOIz/cfYgfrAhcmXt/ge3QP0PbwEGZvqfe+ bAfEPRFBQTvnwJgd3CK6yQ8dGSbCpx4cQgfIduSe8Ne8/aEQ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 The PCI link, when down, needs to be recovered to bring it back. But that cannot be done in a generic way as link recovery procedure is specific to host bridges. So add a new API pci_host_handle_link_down() that could be called by the host bridge drivers when the link goes down. The API will iterate through all the slots and calls the pcie_do_recovery() function with 'pci_channel_io_frozen' as the state. This will result in the execution of the AER Fatal error handling code. Since the link down recovery is pretty much the same as AER Fatal error handling, pcie_do_recovery() helper is reused here. First the AER error_detected callback will be triggered for the bridge and the downstream devices. Then, pci_host_reset_slot() will be called for the slot, which will reset the slot using 'reset_slot' callback to recover the link. Once that's done, resume message will be broadcasted to the bridge and the downstream devices indicating successful link recovery. In case if the AER support is not enabled in the kernel, only pci_bus_error_reset() will be called for each slots as there is no way we could inform the drivers about link recovery. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/pci-host-common.c | 58 ++++++++++++++++++++++++++++= ++++ drivers/pci/controller/pci-host-common.h | 1 + drivers/pci/pci.c | 1 + drivers/pci/pcie/err.c | 1 + 4 files changed, 61 insertions(+) diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/control= ler/pci-host-common.c index f93bc7034e697250711833a5151f7ef177cd62a0..f916f0a874a61ddfbfd99f96975= c00fb66dd224c 100644 --- a/drivers/pci/controller/pci-host-common.c +++ b/drivers/pci/controller/pci-host-common.c @@ -12,9 +12,11 @@ #include #include #include +#include #include #include =20 +#include "../pci.h" #include "pci-host-common.h" =20 static void gen_pci_unmap_cfg(void *ptr) @@ -96,5 +98,61 @@ void pci_host_common_remove(struct platform_device *pdev) } EXPORT_SYMBOL_GPL(pci_host_common_remove); =20 +#if IS_ENABLED(CONFIG_PCIEAER) +static pci_ers_result_t pci_host_reset_slot(struct pci_dev *dev) +{ + int ret; + + ret =3D pci_bus_error_reset(dev); + if (ret) { + pci_err(dev, "Failed to reset slot: %d\n", ret); + return PCI_ERS_RESULT_DISCONNECT; + } + + pci_info(dev, "Slot has been reset\n"); + + return PCI_ERS_RESULT_RECOVERED; +} + +static void pci_host_recover_slots(struct pci_host_bridge *host) +{ + struct pci_bus *bus =3D host->bus; + struct pci_dev *dev; + + for_each_pci_bridge(dev, bus) { + if (!pci_is_root_bus(bus)) + continue; + + pcie_do_recovery(dev, pci_channel_io_frozen, + pci_host_reset_slot); + } +} +#else +static void pci_host_recover_slots(struct pci_host_bridge *host) +{ + struct pci_bus *bus =3D host->bus; + struct pci_dev *dev; + int ret; + + for_each_pci_bridge(dev, bus) { + if (!pci_is_root_bus(bus)) + continue; + + ret =3D pci_bus_error_reset(dev); + if (ret) + pci_err(dev, "Failed to reset slot: %d\n", ret); + else + pci_info(dev, "Slot has been reset\n"); + } +} +#endif + +void pci_host_handle_link_down(struct pci_host_bridge *bridge) +{ + dev_info(&bridge->dev, "Recovering slots due to Link Down\n"); + pci_host_recover_slots(bridge); +} +EXPORT_SYMBOL_GPL(pci_host_handle_link_down); + MODULE_DESCRIPTION("Common library for PCI host controller drivers"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/pci/controller/pci-host-common.h b/drivers/pci/control= ler/pci-host-common.h index d8be024ca68d43afb147fd9104d632b907277144..904698c1a2695888a0fc9c2fac3= 60e456116eb1d 100644 --- a/drivers/pci/controller/pci-host-common.h +++ b/drivers/pci/controller/pci-host-common.h @@ -12,5 +12,6 @@ =20 int pci_host_common_probe(struct platform_device *pdev); void pci_host_common_remove(struct platform_device *pdev); +void pci_host_handle_link_down(struct pci_host_bridge *bridge); =20 #endif diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 13709bb898a967968540826a2b7ee8ade6b7e082..4d396bbab4a8f33cae0ffe8982d= a120a9f1d92c9 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5781,6 +5781,7 @@ int pci_bus_error_reset(struct pci_dev *bridge) mutex_unlock(&pci_slot_mutex); return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); } +EXPORT_SYMBOL_GPL(pci_bus_error_reset); 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[46.193.69.61]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a099b178absm19500236f8f.97.2025.05.08.00.10.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 00:10:39 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 08 May 2025 12:40:34 +0530 Subject: [PATCH v4 5/5] PCI: qcom: Add support for resetting the slot due to link down event Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250508-pcie-reset-slot-v4-5-7050093e2b50@linaro.org> References: <20250508-pcie-reset-slot-v4-0-7050093e2b50@linaro.org> In-Reply-To: <20250508-pcie-reset-slot-v4-0-7050093e2b50@linaro.org> To: Mahesh J Salgaonkar , Oliver O'Halloran , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Zhou Wang , Will Deacon , Robert Richter , Alyssa Rosenzweig , Marc Zyngier , Conor Dooley , Daire McNamara Cc: dingwei@marvell.com, cassel@kernel.org, Lukas Wunner , Krishna Chaitanya Chundru , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8188; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=Xhfd2aLgY7EkLO7Pad4MqFaMxVqdKEiC/l5bXSdXFT0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBoHFjqE6NUL0GQ03l5Ef29uZNrbNS1bDnMhx8cr lsEHGkeSamJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaBxY6gAKCRBVnxHm/pHO 9Tv1B/4koilg8iRNvCXVqQRwOxyYvaueq2dMyvXrQNYllkSrcD/o3052unTWYPESlsa5UOWEvaj 2y+HRo5lOulNl50qrUg8NWJ8W2yVYT0MrBR3cu1uCsyXcMibs3heRmjgGb+BIWbDAbsRg++uwYX Zj9pWydtNgT5VIdMeywoHG5gVG9pxDo5IKX2feIE/EYC8VvejRC1cZlGud4yf4jwwQTu6jAgbdx JaneNTS/ekYtNYM3H/rLGFXJa5LLrzBkFh2mIVfRJMJMUvNFBcVwaW+oEPIwOaJiXyQQCuX986o mJAxemkQmzkhYW2XafVUWnkimHGGHOnNpiV98tIh9c2WmK/N X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 The PCIe link can go down under circumstances such as the device firmware crash, link instability, etc... When that happens, the PCIe slot needs to be reset to make it operational again. Currently, the driver is not handling the link down event, due to which the users have to restart the machine to make PCIe link operational again. So fix it by detecting the link down event and resetting the slot. Since the Qcom PCIe controllers report the link down event through the 'global' IRQ, enable the link down event by setting PARF_INT_ALL_LINK_DOWN bit in PARF_INT_ALL_MASK register. Then in the case of the event, call pci_host_handle_link_down() API in the handler to let the PCI core handle the link down condition. Note that both link up and link down events could be set at a time when the handler runs. So always handle link down first. The API will internally call, 'pci_host_bridge::reset_slot()' callback to reset the slot in a platform specific way. So implement the callback to reset the slot by first resetting the PCIe core, followed by reinitializing the resources and then finally starting the link again. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 112 +++++++++++++++++++++++++++++= +--- 2 files changed, 105 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index d9f0386396edf66ad0e514a0f545ed24d89fcb6c..ce04ee6fbd99cbcce5d2f3a75eb= d72a17070b7b7 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -296,6 +296,7 @@ config PCIE_QCOM select PCIE_DW_HOST select CRC8 select PCIE_QCOM_COMMON + select PCI_HOST_COMMON help Say Y here to enable PCIe controller support on Qualcomm SoCs. The PCIe controller uses the DesignWare core plus Qualcomm-specific diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index dc98ae63362db0422384b1879a2b9a7dc564d091..e577619d0f8ceddf0955139ae6b= 939842f8cb7be 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -34,6 +34,7 @@ #include =20 #include "../../pci.h" +#include "../pci-host-common.h" #include "pcie-designware.h" #include "pcie-qcom-common.h" =20 @@ -55,6 +56,7 @@ #define PARF_INT_ALL_STATUS 0x224 #define PARF_INT_ALL_CLEAR 0x228 #define PARF_INT_ALL_MASK 0x22c +#define PARF_STATUS 0x230 #define PARF_SID_OFFSET 0x234 #define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_DBI_BASE_ADDR_V2 0x350 @@ -130,9 +132,14 @@ =20 /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) +#define SW_CLEAR_FLUSH_MODE BIT(10) +#define FLUSH_MODE BIT(11) =20 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ -#define PARF_INT_ALL_LINK_UP BIT(13) +#define INT_ALL_LINK_DOWN 1 +#define INT_ALL_LINK_UP 13 +#define PARF_INT_ALL_LINK_DOWN BIT(INT_ALL_LINK_DOWN) +#define PARF_INT_ALL_LINK_UP BIT(INT_ALL_LINK_UP) #define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23) =20 /* PARF_NO_SNOOP_OVERRIDE register fields */ @@ -145,6 +152,9 @@ /* PARF_BDF_TO_SID_CFG fields */ #define BDF_TO_SID_BYPASS BIT(0) =20 +/* PARF_STATUS fields */ +#define FLUSH_COMPLETED BIT(8) + /* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) =20 @@ -169,6 +179,7 @@ PCIE_CAP_SLOT_POWER_LIMIT_SCALE) =20 #define PERST_DELAY_US 1000 +#define FLUSH_TIMEOUT_US 100 =20 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) =20 @@ -274,11 +285,14 @@ struct qcom_pcie { struct icc_path *icc_cpu; const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; + int global_irq; bool suspended; bool use_pm_opp; }; =20 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) +static int qcom_pcie_reset_slot(struct pci_host_bridge *bridge, + struct pci_dev *pdev); =20 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { @@ -1263,6 +1277,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) goto err_assert_reset; } =20 + pp->bridge->reset_slot =3D qcom_pcie_reset_slot; + return 0; =20 err_assert_reset: @@ -1517,6 +1533,74 @@ static void qcom_pcie_icc_opp_update(struct qcom_pci= e *pcie) } } =20 +static int qcom_pcie_reset_slot(struct pci_host_bridge *bridge, + struct pci_dev *pdev) +{ + struct pci_bus *bus =3D bridge->bus; + struct dw_pcie_rp *pp =3D bus->sysdata; + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + struct device *dev =3D pcie->pci->dev; + u32 val; + int ret; + + /* Wait for the pending transactions to be completed */ + ret =3D readl_relaxed_poll_timeout(pcie->parf + PARF_STATUS, val, + val & FLUSH_COMPLETED, 10, + FLUSH_TIMEOUT_US); + if (ret) { + dev_err(dev, "Flush completion failed: %d\n", ret); + goto err_host_deinit; + } + + /* Clear the FLUSH_MODE to allow the core to be reset */ + val =3D readl(pcie->parf + PARF_LTSSM); + val |=3D SW_CLEAR_FLUSH_MODE; + writel(val, pcie->parf + PARF_LTSSM); + + /* Wait for the FLUSH_MODE to clear */ + ret =3D readl_relaxed_poll_timeout(pcie->parf + PARF_LTSSM, val, + !(val & FLUSH_MODE), 10, + FLUSH_TIMEOUT_US); + if (ret) { + dev_err(dev, "Flush mode clear failed: %d\n", ret); + goto err_host_deinit; + } + + qcom_pcie_host_deinit(pp); + + ret =3D qcom_pcie_host_init(pp); + if (ret) { + dev_err(dev, "Host init failed\n"); + return ret; + } + + ret =3D dw_pcie_setup_rc(pp); + if (ret) + goto err_host_deinit; + + /* + * Re-enable global IRQ events as the PARF_INT_ALL_MASK register is + * non-sticky. + */ + if (pcie->global_irq) + writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_ALL_LINK_DOWN | + PARF_INT_MSI_DEV_0_7, pcie->parf + PARF_INT_ALL_MASK); + + qcom_pcie_start_link(pci); + if (!dw_pcie_wait_for_link(pci)) + qcom_pcie_icc_opp_update(pcie); + + dev_dbg(dev, "Slot reset completed\n"); + + return 0; + +err_host_deinit: + qcom_pcie_host_deinit(pp); + + return ret; +} + static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) { struct qcom_pcie *pcie =3D (struct qcom_pcie *)dev_get_drvdata(s->private= ); @@ -1559,11 +1643,20 @@ static irqreturn_t qcom_pcie_global_irq_thread(int = irq, void *data) struct qcom_pcie *pcie =3D data; struct dw_pcie_rp *pp =3D &pcie->pci->pp; struct device *dev =3D pcie->pci->dev; - u32 status =3D readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); + unsigned long status =3D readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); =20 writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); =20 - if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { + /* + * It is possible that both Link Up and Link Down events might have + * happended. So always handle Link Down first. + */ + if (test_and_clear_bit(INT_ALL_LINK_DOWN, &status)) { + dev_dbg(dev, "Received Link down event\n"); + pci_host_handle_link_down(pp->bridge); + } + + if (test_and_clear_bit(INT_ALL_LINK_UP, &status)) { dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); /* Rescan the bus to enumerate endpoint devices */ pci_lock_rescan_remove(); @@ -1571,11 +1664,12 @@ static irqreturn_t qcom_pcie_global_irq_thread(int = irq, void *data) pci_unlock_rescan_remove(); =20 qcom_pcie_icc_opp_update(pcie); - } else { - dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", - status); } =20 + if (status) + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", + (u32) status); + return IRQ_HANDLED; } =20 @@ -1732,8 +1826,10 @@ static int qcom_pcie_probe(struct platform_device *p= dev) goto err_host_deinit; } =20 - writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_MSI_DEV_0_7, - pcie->parf + PARF_INT_ALL_MASK); + writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_ALL_LINK_DOWN | + PARF_INT_MSI_DEV_0_7, pcie->parf + PARF_INT_ALL_MASK); + + pcie->global_irq =3D irq; } =20 qcom_pcie_icc_opp_update(pcie); --=20 2.43.0