From nobody Sun Dec 14 11:56:17 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16CDB28C2C1; Wed, 7 May 2025 18:07:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746641230; cv=none; b=iaYqg2WW/JjcM5pIr9mSV1TAyd1ZYM1FvSBPR2JaieJ6nYbqk/UF8bDMJ9XCK51uBj/dtGVHGgcrlw+tA7bT02RmxHaSfrLmdy/WfwtvYrynMen36K5MPFHkUFoPHY7pejSXAlUCMXW5v1qh3dNhNOKI37vFP0GEoZbINQOU3JA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746641230; c=relaxed/simple; bh=6/x4vtTqHJbcRGgfij/bKGLlMegIHLsCKSeoEVaNpBA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cmie6c7F0VvlSDa0UIxTkOFqBWigylvjIYA216p3RBmts2ZJVZCs+wl1oIJfk889WgZpE7MSZ0aZkf6zjdW7yq00V0HJTl4NVjMkiSVXoo3vsl+m6Y2gCg7v7J1gNL0qHvhWsz3VlS2ttxynjH6bSUxvJ1kdnMt2HBOJaKs/+Aw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=sDK3yj/X; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="sDK3yj/X" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 547I6cFv878986 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 7 May 2025 13:06:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746641198; bh=dZRmFfn3xP3YswAGBEsjtqQDQ3V5xlqHXr1IAvZak9o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sDK3yj/XYqJYyKsc1eUh5jjs3WwoMEswNm4sSpDFVxYpaVp6hWT0GVXWcnBhrpYHU uwL8MQd1UX4AgIsa8//I09NfQLAzbaFbzeBn+F3xbFybm08rD6FH0ghc9YTw9i+3wI y5jXEZjdCyw01WXzsplNLvvWSblySlGjw3dyKtj8= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 547I6cpP035077 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 7 May 2025 13:06:38 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 7 May 2025 13:06:37 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 7 May 2025 13:06:37 -0500 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 547I6aUo035982; Wed, 7 May 2025 13:06:37 -0500 From: Devarsh Thakkar To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v6 3/3] drm/tidss: Add support for AM62L display subsystem Date: Wed, 7 May 2025 23:36:31 +0530 Message-ID: <20250507180631.874930-4-devarsht@ti.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250507180631.874930-1-devarsht@ti.com> References: <20250507180631.874930-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Enable display for AM62L DSS [1] which supports only a single display pipeline using a single overlay manager, single video port and a single video lite pipeline which does not support scaling. The output of video port is routed to SoC boundary via DPI interface and the DPI signals from the video port are also routed to DSI Tx controller present within the SoC. [1]: Section 11.7 (Display Subsystem and Peripherals) Link : https://www.ti.com/lit/pdf/sprujb4 Signed-off-by: Devarsh Thakkar --- v6: - No change V5: - No change V4: - Rebase on top of previous patch to use vid_info structure V3:=20 - Rebase on top of 0002-drm-tidss-Update-infra-to-support-DSS7-cut-down-vers.patch - Use the generic "tidss_am65x_common_regs" as common reg space instead of creating a new one V2:=20 - Add separate common reg space for AM62L - Add separate irq enable/disable/read/clear helpers for AM62L - Use separate helper function for setting overlay attributes - Drop Reviewed-by: Tomi Valkeinen due to additional changes made in V2. drivers/gpu/drm/tidss/tidss_dispc.c | 41 +++++++++++++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++ drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index f8bd005709d4..eb02c89705b3 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -440,6 +440,42 @@ const struct dispc_features dispc_am62a7_feats =3D { .vid_order =3D {1, 0}, }; =20 +const struct dispc_features dispc_am62l_feats =3D { + .max_pclk_khz =3D { + [DISPC_VP_DPI] =3D 165000, + }, + + .subrev =3D DISPC_AM62L, + + .common =3D "common", + .common_regs =3D tidss_am65x_common_regs, + + .num_vps =3D 1, + .vp_name =3D { "vp1" }, + .ovr_name =3D { "ovr1" }, + .vpclk_name =3D { "vp1" }, + .vp_bus_type =3D { DISPC_VP_DPI }, + + .vp_feat =3D { .color =3D { + .has_ctm =3D true, + .gamma_size =3D 256, + .gamma_type =3D TIDSS_GAMMA_8BIT, + }, + }, + + .num_vids =3D 1, + + .vid_info =3D { + { + .name =3D "vidl1", + .is_lite =3D true, + .hw_id =3D 1, + } + }, + + .vid_order =3D {0}, +}; + static const u16 *dispc_common_regmap; =20 struct dss_vp_data { @@ -951,6 +987,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc= _device *dispc) return dispc_k2g_read_and_clear_irqstatus(dispc); case DISPC_AM625: case DISPC_AM62A7: + case DISPC_AM62L: case DISPC_AM65X: case DISPC_J721E: return dispc_k3_read_and_clear_irqstatus(dispc); @@ -968,6 +1005,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, d= ispc_irq_t mask) break; case DISPC_AM625: case DISPC_AM62A7: + case DISPC_AM62L: case DISPC_AM65X: case DISPC_J721E: dispc_k3_set_irqenable(dispc, mask); @@ -1464,6 +1502,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, = u32 hw_plane, break; case DISPC_AM625: case DISPC_AM62A7: + case DISPC_AM62L: case DISPC_AM65X: dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, x, y, layer); @@ -2384,6 +2423,7 @@ static void dispc_plane_init(struct dispc_device *dis= pc) break; case DISPC_AM625: case DISPC_AM62A7: + case DISPC_AM62L: case DISPC_AM65X: case DISPC_J721E: dispc_k3_plane_init(dispc); @@ -2492,6 +2532,7 @@ static void dispc_vp_write_gamma_table(struct dispc_d= evice *dispc, break; case DISPC_AM625: case DISPC_AM62A7: + case DISPC_AM62L: case DISPC_AM65X: dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); break; diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/ti= dss_dispc.h index 72a0146e57d5..28958514b8f5 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -67,6 +67,7 @@ enum dispc_vp_bus_type { enum dispc_dss_subrevision { DISPC_K2G, DISPC_AM625, + DISPC_AM62L, DISPC_AM62A7, DISPC_AM65X, DISPC_J721E, @@ -96,6 +97,7 @@ struct dispc_features { extern const struct dispc_features dispc_k2g_feats; extern const struct dispc_features dispc_am625_feats; extern const struct dispc_features dispc_am62a7_feats; +extern const struct dispc_features dispc_am62l_feats; extern const struct dispc_features dispc_am65x_feats; extern const struct dispc_features dispc_j721e_feats; =20 diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tids= s_drv.c index d4652e8cc28c..f2a4f659f574 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -242,6 +242,7 @@ static const struct of_device_id tidss_of_table[] =3D { { .compatible =3D "ti,k2g-dss", .data =3D &dispc_k2g_feats, }, { .compatible =3D "ti,am625-dss", .data =3D &dispc_am625_feats, }, { .compatible =3D "ti,am62a7-dss", .data =3D &dispc_am62a7_feats, }, + { .compatible =3D "ti,am62l-dss", .data =3D &dispc_am62l_feats, }, { .compatible =3D "ti,am65x-dss", .data =3D &dispc_am65x_feats, }, { .compatible =3D "ti,j721e-dss", .data =3D &dispc_j721e_feats, }, { } --=20 2.39.1