From nobody Sun Dec 14 11:56:17 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D11EE2571D7; Wed, 7 May 2025 18:07:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746641223; cv=none; b=lojsQuVVDgvga0Xm5wZKz0kOf4SRYhZ7ww79GPc5E3CbS6TsxRzuWCpXkz+bAfIYYLoE6sqhlqdCUzI3sTmMHsIaxr92ZOuGg938yB3qp3qftpSEYLvLiqCKuLZzasJsVu70ZohX8Wy0ihjI8bXy6NfgmJ0FiDUghhcFnpEejV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746641223; c=relaxed/simple; bh=UvpazV8xQU9HRRLul36TI7uDwHlchqfCivv8W6F7Pp8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V4xsk4yuRLdQoL/kMPl7X6IcyA+CaZIqytuK5h0u1zoB4gHOnoJpqTkSnaeJbhHsaGmT1oRksWjBvvmgfa/F2Db6pfhEOLun9KleVNlfOxtiwf1CUjxL1tc84dM9lKoZYfgtrapuKLEC225wSnQZiIdUpjbTbb+aPQzVV58dHSE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=L3CNQJ3y; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="L3CNQJ3y" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 547I6ZZR1594640 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 7 May 2025 13:06:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746641195; bh=0+UCHzmZyl1chqLqX2QUWcfk6t5klutwQR47DtTuYJM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=L3CNQJ3y927oYg9doFlxj/w4vMt39TQj07e8CQqdpjfSGUd+tu14j4I81HF1XqwkJ LQVFPfPmq1uYqUO3mMPueWW8wKSAT8QXGtggSWM+nzhnMp+UyNM9JSg8eEQqcE7Z+c kD9IPNWVkJe7dhgJ6bd3pbgXZ7d32evcBEk8LP70= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 547I6Zb1012470 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 7 May 2025 13:06:35 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 7 May 2025 13:06:34 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 7 May 2025 13:06:34 -0500 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 547I6XJA086337; Wed, 7 May 2025 13:06:34 -0500 From: Devarsh Thakkar To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v6 1/3] dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS Date: Wed, 7 May 2025 23:36:29 +0530 Message-ID: <20250507180631.874930-2-devarsht@ti.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250507180631.874930-1-devarsht@ti.com> References: <20250507180631.874930-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The DSS controller on TI's AM62L SoC is an update from that on TI's AM625/AM65x/AM62A7 SoC. The AM62L DSS [1] only supports a single display pipeline using a single overlay manager, single video port and a single video lite pipeline which does not support scaling. The output of video port is routed to SoC boundary via DPI interface and the DPI signals from the video port are also routed to DSI Tx controller present within the SoC. [1]: Section 11.7 (Display Subsystem and Peripherals) Link : https://www.ti.com/lit/pdf/sprujb4 Reviewed-by: Krzysztof Kozlowski Reviewed-by: Jayesh Choudhary Reviewed-by: Tomi Valkeinen Signed-off-by: Devarsh Thakkar --- V6: No change V5: No change V4: No change V3: - Remove AM62A references as suggested - Add Reviewed-by V2:=20 - Add Reviewed-by - s/ti,am62l,dss/ti,am62l-dss .../bindings/display/ti/ti,am65x-dss.yaml | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 31c4ffcb599c..a5b13cb7bc73 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -12,18 +12,25 @@ maintainers: - Tomi Valkeinen =20 description: | - The AM625 and AM65x TI Keystone Display SubSystem with two output + The AM625 and AM65x TI Keystone Display SubSystem has two output ports and two video planes. In AM65x DSS, the first video port supports 1 OLDI TX and in AM625 DSS, the first video port output is internally routed to 2 OLDI TXes. The second video port supports DPI format. The first plane is full video plane with all features and the second is a "lite plane" without scaling support. + The AM62L display subsystem has a single output port which supports DPI + format but it only supports single video "lite plane" which does not sup= port + scaling. The output port is routed to SoC boundary via DPI interface and= same + DPI signals are also routed internally to DSI Tx controller present with= in the + SoC. Due to clocking limitations only one of the interface i.e. either D= SI or + DPI can be used at once. =20 properties: compatible: enum: - ti,am625-dss - ti,am62a7-dss + - ti,am62l-dss - ti,am65x-dss =20 reg: @@ -91,6 +98,8 @@ properties: For AM625 DSS, the internal DPI output port node from video port 1. For AM62A7 DSS, the port is tied off inside the SoC. + For AM62L DSS, the DSS DPI output port node from video port 1 + or DSI Tx controller node connected to video port 1. =20 port@1: $ref: /schemas/graph.yaml#/properties/port @@ -123,6 +132,16 @@ allOf: ports: properties: port@0: false + - if: + properties: + compatible: + contains: + const: ti,am62l-dss + then: + properties: + ports: + properties: + port@1: false =20 required: - compatible --=20 2.39.1