From nobody Sun Feb 8 19:24:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C3E4928B7CC for ; Wed, 7 May 2025 15:47:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632826; cv=none; b=oCwzMvDiz1TiXio5iSf8bMRradJTBjfZuMUqpaibB8jQ12sm1VM4e0GKGF8I+PLPbIdAXafKkvzZbi9e8ShtUdKsACqpGfb2/dPFHD2+Mzol1A8S4LhPF3eXBF1JtnoWi0A8YTn7x2IMjEYnqyxWxGYJI+2Nsqca0gPnz7/MFT4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632826; c=relaxed/simple; bh=VPh6jhHdJFp/lgb7xKj4rThxAcSWJDnRwVM1TjUPXD0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jGWqyF8HXWc6Bmr+a21y6U5Cjjt/UCGFSxd2o6JNgCZJGS8oiXKq+6hNXjCBoRYpAHxeaZxGVB4vMHrulbKl7HRGqarT9flsFKnz0Lsi/4cCTNa1NYB6oZGabfA6gag67Bnh9rUliSIm1wcmcHYtC7SF27YzhHvzD1fJn1s8SR8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E918D2008; Wed, 7 May 2025 08:46:53 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6AF5A3F58B; Wed, 7 May 2025 08:47:00 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, james.morse@arm.com, hardevsinh.palaniya@siliconsignals.io, huangxiaojia2@huawei.com, mark.rutland@arm.com, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v4 1/7] arm64/cpufeature: add MTE_STORE_ONLY feature Date: Wed, 7 May 2025 16:46:48 +0100 Message-Id: <20250507154654.1937588-2-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507154654.1937588-1-yeoreum.yun@arm.com> References: <20250507154654.1937588-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since ARMv8.9, FEAT_MTE_STORE_ONLY can be used to restrict raise of tag check fault on store operation only. add MTE_STORE_ONLY feature. Signed-off-by: Yeoreum Yun --- arch/arm64/kernel/cpufeature.c | 8 ++++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 9 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 183b4b7e3074..de42f890bcd7 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -313,6 +313,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = =3D { static const struct arm64_ftr_bits ftr_id_aa64pfr2[] =3D { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_F= PMR_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL= 1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL= 1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), ARM64_FTR_END, }; =20 @@ -2869,6 +2870,13 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .matches =3D has_cpuid_feature, ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) }, + { + .desc =3D "Store Only MTE Tag Check", + .capability =3D ARM64_MTE_STORE_ONLY, + .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) + }, #endif /* CONFIG_ARM64_MTE */ { .desc =3D "RCpc load-acquire (LDAPR)", diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index ef62ea04ba37..282a1dbb8bc9 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -68,6 +68,7 @@ MPAM_HCR MTE MTE_ASYMM MTE_FAR +MTE_STORE_ONLY SME SME_FA64 SME2 --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sun Feb 8 19:24:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B3FD028B7CC for ; Wed, 7 May 2025 15:47:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632830; cv=none; b=svTM2f/Fc+NcklvVq6/Bk/Ms77T1GsBztTC+Z2IYXzKCoK2py5Zw0HMlHmRvBbten82cRxcEOH8XoRCqS4EOwy8HwRoL6NDOtH/05dx7FzrLdsPWoatyFSbI1JJ8/LMJaDr74Ad6StUFL3RasXibk2Ze01W4mZS6/IXhRrEDfUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632830; c=relaxed/simple; bh=369bwvtiVylIIOkV/f/3osAZWZV4pzU5X5ry2ZDYtJs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kGle4VX/vXxSp5fxXEaettjjQAhwFuQVb2uggb/ftI05JOMDeg8iIYYHhUmkd7WACZajTTvok6o3d7MS58cL1ArZ0HmFHkgHuIe62KUdAypWHQV+BDldFG0OpKWKFeNgw04BNuO9ceEKruxSR+VOPBcFsZJ2WkZl1sPanAPIprQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E24DB202C; Wed, 7 May 2025 08:46:57 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5C9653F58B; Wed, 7 May 2025 08:47:04 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, james.morse@arm.com, hardevsinh.palaniya@siliconsignals.io, huangxiaojia2@huawei.com, mark.rutland@arm.com, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v4 2/7] prtcl: introduce PR_MTE_STORE_ONLY Date: Wed, 7 May 2025 16:46:49 +0100 Message-Id: <20250507154654.1937588-3-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507154654.1937588-1-yeoreum.yun@arm.com> References: <20250507154654.1937588-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" PR_MTE_STORE_ONLY is used to restrict the MTE tag check for store opeartion only. Signed-off-by: Yeoreum Yun --- include/uapi/linux/prctl.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 15c18ef4eb11..83ac566251d8 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -244,6 +244,8 @@ struct prctl_mm_map { # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) /* Unused; kept only for source compatibility */ # define PR_MTE_TCF_SHIFT 1 +/* MTE tag check store only */ +# define PR_MTE_STORE_ONLY (1UL << 19) /* RISC-V pointer masking tag length */ # define PR_PMLEN_SHIFT 24 # define PR_PMLEN_MASK (0x7fUL << PR_PMLEN_SHIFT) --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sun Feb 8 19:24:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A6EAE28BAB9 for ; Wed, 7 May 2025 15:47:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632834; cv=none; b=M4RjCn+iGGDf5crzxM+THFB3bdFmAdIbxJ68m/LmNajfLT6NCATR5fggDusefAHDalJF+qr+gWJTHnk39bBwbr2JVsH/9w2MmN1Uq2lO0ghPi9r3SuCcHyU3Sdu3Z4Szu3tUVgsK1PpNi+b4HT4cTG8QfY9ldP+b5K2HJNlVvgQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632834; c=relaxed/simple; bh=Y79p7rne7cXX1nFC+SWC96eCL2o2wsDDvsZXSb0YyAc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ime+NmJ/qGNNoMCp3ZbpdpA96wUIlmTPmTeF+LpxaxKTzrz91GYk15mxsrSngKjfT2EIuY2D9vF/eo7fEA6IAjne+R641L0NVQ6QeZJ8Oln6gXfuwX/B5lBRa2C9NBiOUAFv2d6dcVw9y/CJ5ltlms6tTBPxepsXqToSRj8HWqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D3BC5339; Wed, 7 May 2025 08:47:01 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 56E1B3F58B; Wed, 7 May 2025 08:47:08 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, james.morse@arm.com, hardevsinh.palaniya@siliconsignals.io, huangxiaojia2@huawei.com, mark.rutland@arm.com, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v4 3/7] arm64/kernel: support store-only mte tag check Date: Wed, 7 May 2025 16:46:50 +0100 Message-Id: <20250507154654.1937588-4-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507154654.1937588-1-yeoreum.yun@arm.com> References: <20250507154654.1937588-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce new flag -- MTE_CTRL_STORE_ONLY used to set store-only tag check. This flag isn't overridden by prefered tcf flag setting but set together with prefered setting of way to report tag check fault. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/processor.h | 2 ++ arch/arm64/kernel/mte.c | 11 ++++++++++- arch/arm64/kernel/process.c | 6 +++++- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/pr= ocessor.h index 1bf1a3b16e88..61d62bfd5a7b 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -23,6 +23,8 @@ #define MTE_CTRL_TCF_ASYNC (1UL << 17) #define MTE_CTRL_TCF_ASYMM (1UL << 18) =20 +#define MTE_CTRL_STORE_ONLY (1UL << 19) + #ifndef __ASSEMBLY__ =20 #include diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 2fbfd27ff5f2..e5e773844889 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -200,7 +200,7 @@ static void mte_update_sctlr_user(struct task_struct *t= ask) * program requested values go with what was requested. */ resolved_mte_tcf =3D (mte_ctrl & pref) ? pref : mte_ctrl; - sctlr &=3D ~SCTLR_EL1_TCF0_MASK; + sctlr &=3D ~(SCTLR_EL1_TCF0_MASK | SCTLR_EL1_TCSO0_MASK); /* * Pick an actual setting. The order in which we check for * set bits and map into register values determines our @@ -212,6 +212,10 @@ static void mte_update_sctlr_user(struct task_struct *= task) sctlr |=3D SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, ASYNC); else if (resolved_mte_tcf & MTE_CTRL_TCF_SYNC) sctlr |=3D SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, SYNC); + + if (mte_ctrl & MTE_CTRL_STORE_ONLY) + sctlr |=3D SYS_FIELD_PREP(SCTLR_EL1, TCSO0, 1); + task->thread.sctlr_user =3D sctlr; } =20 @@ -371,6 +375,9 @@ long set_mte_ctrl(struct task_struct *task, unsigned lo= ng arg) (arg & PR_MTE_TCF_SYNC)) mte_ctrl |=3D MTE_CTRL_TCF_ASYMM; =20 + if (arg & PR_MTE_STORE_ONLY) + mte_ctrl |=3D MTE_CTRL_STORE_ONLY; + task->thread.mte_ctrl =3D mte_ctrl; if (task =3D=3D current) { preempt_disable(); @@ -398,6 +405,8 @@ long get_mte_ctrl(struct task_struct *task) ret |=3D PR_MTE_TCF_ASYNC; if (mte_ctrl & MTE_CTRL_TCF_SYNC) ret |=3D PR_MTE_TCF_SYNC; + if (mte_ctrl & MTE_CTRL_STORE_ONLY) + ret |=3D PR_MTE_STORE_ONLY; =20 return ret; } diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 42faebb7b712..cea4a23a15de 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -815,10 +815,14 @@ long set_tagged_addr_ctrl(struct task_struct *task, u= nsigned long arg) if (is_compat_thread(ti)) return -EINVAL; =20 - if (system_supports_mte()) + if (system_supports_mte()) { valid_mask |=3D PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC \ | PR_MTE_TAG_MASK; =20 + if (cpus_have_cap(ARM64_MTE_STORE_ONLY)) + valid_mask |=3D PR_MTE_STORE_ONLY; + } + if (arg & ~valid_mask) return -EINVAL; =20 --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sun Feb 8 19:24:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5981D28B7CE for ; Wed, 7 May 2025 15:47:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632837; cv=none; b=o2zDIm9+UHP0eELhCwkjpmDRk6LA0y2cabYr48KJV9g4KICAA9dsfTU3xbR4pDW7rq6BZYE9Q02df7ltu4i747Vq05SLRkxAGzenwJTU/zVPibuTytLI7jjOXZPMrSCJyI8c1C13JjsH3e/BWPUu1SI10efXJUifZPE5vy5ED5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632837; c=relaxed/simple; bh=HHW/VRW/mGVkdrpdo99wEo16Fvla27rU2A19JxzcK3M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=s/FTIvEkC0cNSyesUVVV7U26lHtSNUiStLT574DLZG1cz/7+Cvpw6AYjSti3U4+2Fd+yoDcSIGYaMsdztBx2Y+ly23z3IfAUwxE3iuS7162fP9OEzvzteAx7Kdb/CQ9Xyt9fyKnE2qc58PLirm5fv9Wu0Ggv1pU2PG+6seTQ/ws= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C7901204C; Wed, 7 May 2025 08:47:05 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4802C3F58B; Wed, 7 May 2025 08:47:12 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, james.morse@arm.com, hardevsinh.palaniya@siliconsignals.io, huangxiaojia2@huawei.com, mark.rutland@arm.com, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v4 4/7] arm64/hwcaps: add MTE_STORE_ONLY hwcaps Date: Wed, 7 May 2025 16:46:51 +0100 Message-Id: <20250507154654.1937588-5-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507154654.1937588-1-yeoreum.yun@arm.com> References: <20250507154654.1937588-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since ARMv8.9, FEAT_MTE_STORE_ONLY can be used to restrict raise of tag check fault on store operation only. add MTE_STORE_ONLY hwcaps so that user can use this feature. Signed-off-by: Yeoreum Yun --- Documentation/arch/arm64/elf_hwcaps.rst | 3 +++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 1 + arch/arm64/kernel/cpuinfo.c | 1 + 5 files changed, 7 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/a= rm64/elf_hwcaps.rst index 358f5af035ff..f58ada4d6cb2 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -438,6 +438,9 @@ HWCAP2_POE HWCAP3_MTE_FAR Functionality implied by ID_AA64PFR2_EL1.MTEFAR =3D=3D 0b0001. =20 +HWCAP3_MTE_STORE_ONLY + Functionality implied by ID_AA64PFR2_EL1.MTESTOREONLY =3D=3D 0b0001. + 4. Unused AT_HWCAP bits ----------------------- =20 diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 28dd1ac29ecc..13f94c8ddfc0 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -177,6 +177,7 @@ =20 #define __khwcap3_feature(x) (const_ilog2(HWCAP3_ ## x) + 128) #define KERNEL_HWCAP_MTE_FAR __khwcap3_feature(MTE_FAR) +#define KERNEL_HWCAP_MTE_STORE_ONLY __khwcap3_feature(MTE_STORE_ONLY) =20 /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/= asm/hwcap.h index 7d22527a7975..72c78468b806 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -144,5 +144,6 @@ * HWCAP3 flags - for AT_HWCAP3 */ #define HWCAP3_MTE_FAR (1UL << 0) +#define HWCAP3_MTE_STORE_ONLY (1UL << 1) =20 #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index de42f890bcd7..a2f25a8bed96 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3208,6 +3208,7 @@ static const struct arm64_cpu_capabilities arm64_elf_= hwcaps[] =3D { HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), + HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MT= E_STORE_ONLY), #endif /* CONFIG_ARM64_MTE */ HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 058e21295003..37fd9a56b0ce 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -161,6 +161,7 @@ static const char *const hwcap_str[] =3D { [KERNEL_HWCAP_SME_STMOP] =3D "smestmop", [KERNEL_HWCAP_SME_SMOP4] =3D "smesmop4", [KERNEL_HWCAP_MTE_FAR] =3D "mtefar", + [KERNEL_HWCAP_MTE_STORE_ONLY] =3D "mtestoreonly", }; =20 #ifdef CONFIG_COMPAT --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sun Feb 8 19:24:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4CA3B28B7CE for ; Wed, 7 May 2025 15:47:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632841; cv=none; b=MLj8EtfmVtF45pgeQQrofzQs+km7u6NyGyzQbzimEVGuwxojMDNKxfPLQOF6iImxucDDSDhACg2Dl9TGucIgVNZfhnv0D1Tbcq82Yc1tVlCAvbqsVlE1hOb7e5zrD131MQsjwgpwvOTay9z075Xy+hVIZmOZBqTRvCBzqZHvTzU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632841; c=relaxed/simple; bh=CoZp1yZHryd6ipnxDKA4HcLlBAN2fzhmCIrdYyhrT9k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=krfZwfFIBfMrAgFsrMIwQDWuI1M/OTHnIlWohLonJMCRDbVy3QkGoTOC+NbWXAmkom/O3qx/KqphAeIUy068yGTqeVXHA1OWksf/JoB0L1w7vM2YrSEeAWr9cYkV1/DXQZLlXvV0t9Boa2ByLZSKdg6v++7bxIBnL4ppTgf+YnQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C16A12008; Wed, 7 May 2025 08:47:09 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3C0603F58B; Wed, 7 May 2025 08:47:16 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, james.morse@arm.com, hardevsinh.palaniya@siliconsignals.io, huangxiaojia2@huawei.com, mark.rutland@arm.com, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v4 5/7] tools/kselftest: add MTE_STORE_ONLY feature hwcap test Date: Wed, 7 May 2025 16:46:52 +0100 Message-Id: <20250507154654.1937588-6-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507154654.1937588-1-yeoreum.yun@arm.com> References: <20250507154654.1937588-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" add MTE_STORE_ONLY feature hwcap test. Signed-off-by: Yeoreum Yun Reviewed-by: Mark Brown --- tools/testing/selftests/arm64/abi/hwcap.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/self= tests/arm64/abi/hwcap.c index e60bfb798ba2..42b59a994bd0 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -1104,6 +1104,12 @@ static const struct hwcap_data { .hwcap_bit =3D HWCAP3_MTE_FAR, .cpuinfo =3D "mtefar", }, + { + .name =3D "MTE_STOREONLY", + .at_hwcap =3D AT_HWCAP3, + .hwcap_bit =3D HWCAP3_MTE_STORE_ONLY, + .cpuinfo =3D "mtestoreonly", + }, }; typedef void (*sighandler_fn)(int, siginfo_t *, void *); -- LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sun Feb 8 19:24:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9F82C28B7CE for ; Wed, 7 May 2025 15:47:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632846; cv=none; b=ms/cYbeqYvLBE8PhI2zbZ0I6s9w5dBH2j6oBGltpzUplXlblhl7PVrlwY9NKOVCrHovioI1KnlE76CB9RbVuZ9xPhpNAp9hkrzc8FAK9QeH9DnvPdAeXuJ066vtOCsv4D5+NTHrZB5REQy1BggpNI/SZqDMjkxYdReBXm0j96AE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632846; c=relaxed/simple; bh=1eZolM8PXZ1glHIOupuL1UKzBcmbDfnVjXHZPkpkycE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=myAWbIGdviPN+8oKPTZHBnA8K8+hylA9d+TvKbiJ4gqiB3oRTZzVxD6gasEH5+7LMSam1Br7FVsuN5nWuff/FodoXaiWUazaLmlWMTYba+L2CpRTIEbkPV9t2raVB3MfGY5eTiwbZgrHfQmE9HwOgVwScBxiIzuj21/RVhoJkuo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B45D1204C; Wed, 7 May 2025 08:47:13 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 371823F58B; Wed, 7 May 2025 08:47:20 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, james.morse@arm.com, hardevsinh.palaniya@siliconsignals.io, huangxiaojia2@huawei.com, mark.rutland@arm.com, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v4 6/7] kselftest/arm64/mte: preparation for mte store only test Date: Wed, 7 May 2025 16:46:53 +0100 Message-Id: <20250507154654.1937588-7-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507154654.1937588-1-yeoreum.yun@arm.com> References: <20250507154654.1937588-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since ARMv8.9, FEAT_MTE_STORE_ONLY can be used to restrict raise of tag check fault on store operation only. This patch is preparation for testing FEAT_MTE_STORE_ONLY It shouldn't change test result. Signed-off-by: Yeoreum Yun --- .../selftests/arm64/mte/check_buffer_fill.c | 10 +++++----- .../selftests/arm64/mte/check_child_memory.c | 4 ++-- .../selftests/arm64/mte/check_hugetlb_options.c | 6 +++--- .../selftests/arm64/mte/check_ksm_options.c | 2 +- .../selftests/arm64/mte/check_mmap_options.c | 6 +++--- .../selftests/arm64/mte/check_tags_inclusion.c | 8 ++++---- tools/testing/selftests/arm64/mte/check_user_mem.c | 2 +- .../testing/selftests/arm64/mte/mte_common_util.c | 14 ++++++++++++-- .../testing/selftests/arm64/mte/mte_common_util.h | 3 ++- 9 files changed, 33 insertions(+), 22 deletions(-) diff --git a/tools/testing/selftests/arm64/mte/check_buffer_fill.c b/tools/= testing/selftests/arm64/mte/check_buffer_fill.c index 5248b5265aa4..ff4e07503349 100644 --- a/tools/testing/selftests/arm64/mte/check_buffer_fill.c +++ b/tools/testing/selftests/arm64/mte/check_buffer_fill.c @@ -31,7 +31,7 @@ static int check_buffer_by_byte(int mem_type, int mode) int i, j, item; bool err; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); item =3D ARRAY_SIZE(sizes); =20 for (i =3D 0; i < item; i++) { @@ -68,7 +68,7 @@ static int check_buffer_underflow_by_byte(int mem_type, i= nt mode, bool err; char *und_ptr =3D NULL; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); item =3D ARRAY_SIZE(sizes); for (i =3D 0; i < item; i++) { ptr =3D (char *)mte_allocate_memory_tag_range(sizes[i], mem_type, 0, @@ -164,7 +164,7 @@ static int check_buffer_overflow_by_byte(int mem_type, = int mode, size_t tagged_size, overflow_size; char *over_ptr =3D NULL; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); item =3D ARRAY_SIZE(sizes); for (i =3D 0; i < item; i++) { ptr =3D (char *)mte_allocate_memory_tag_range(sizes[i], mem_type, 0, @@ -337,7 +337,7 @@ static int check_buffer_by_block(int mem_type, int mode) { int i, item, result =3D KSFT_PASS; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); item =3D ARRAY_SIZE(sizes); cur_mte_cxt.fault_valid =3D false; for (i =3D 0; i < item; i++) { @@ -368,7 +368,7 @@ static int check_memory_initial_tags(int mem_type, int = mode, int mapping) int run, fd; int total =3D ARRAY_SIZE(sizes); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < total; run++) { /* check initial tags for anonymous mmap */ ptr =3D (char *)mte_allocate_memory(sizes[run], mem_type, mapping, false= ); diff --git a/tools/testing/selftests/arm64/mte/check_child_memory.c b/tools= /testing/selftests/arm64/mte/check_child_memory.c index b97ea3981c21..5e97ee792e4d 100644 --- a/tools/testing/selftests/arm64/mte/check_child_memory.c +++ b/tools/testing/selftests/arm64/mte/check_child_memory.c @@ -88,7 +88,7 @@ static int check_child_memory_mapping(int mem_type, int m= ode, int mapping) int item =3D ARRAY_SIZE(sizes); =20 item =3D ARRAY_SIZE(sizes); - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < item; run++) { ptr =3D (char *)mte_allocate_memory_tag_range(sizes[run], mem_type, mapp= ing, UNDERFLOW, OVERFLOW); @@ -109,7 +109,7 @@ static int check_child_file_mapping(int mem_type, int m= ode, int mapping) int run, fd, map_size, result =3D KSFT_PASS; int total =3D ARRAY_SIZE(sizes); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < total; run++) { fd =3D create_temp_file(); if (fd =3D=3D -1) diff --git a/tools/testing/selftests/arm64/mte/check_hugetlb_options.c b/to= ols/testing/selftests/arm64/mte/check_hugetlb_options.c index 4e644a606394..aad1234c7e0f 100644 --- a/tools/testing/selftests/arm64/mte/check_hugetlb_options.c +++ b/tools/testing/selftests/arm64/mte/check_hugetlb_options.c @@ -151,7 +151,7 @@ static int check_hugetlb_memory_mapping(int mem_type, i= nt mode, int mapping, int =20 map_size =3D default_huge_page_size(); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); map_ptr =3D (char *)mte_allocate_memory(map_size, mem_type, mapping, fals= e); if (check_allocated_memory(map_ptr, map_size, mem_type, false) !=3D KSFT_= PASS) return KSFT_FAIL; @@ -180,7 +180,7 @@ static int check_clear_prot_mte_flag(int mem_type, int = mode, int mapping) unsigned long map_size; =20 prot_flag =3D PROT_READ | PROT_WRITE; - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); map_size =3D default_huge_page_size(); map_ptr =3D (char *)mte_allocate_memory_tag_range(map_size, mem_type, map= ping, 0, 0); @@ -210,7 +210,7 @@ static int check_child_hugetlb_memory_mapping(int mem_t= ype, int mode, int mappin =20 map_size =3D default_huge_page_size(); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); ptr =3D (char *)mte_allocate_memory_tag_range(map_size, mem_type, mapping, 0, 0); if (check_allocated_memory_range(ptr, map_size, mem_type, diff --git a/tools/testing/selftests/arm64/mte/check_ksm_options.c b/tools/= testing/selftests/arm64/mte/check_ksm_options.c index afea4e381862..0cf5faef1724 100644 --- a/tools/testing/selftests/arm64/mte/check_ksm_options.c +++ b/tools/testing/selftests/arm64/mte/check_ksm_options.c @@ -106,7 +106,7 @@ static int check_madvise_options(int mem_type, int mode= , int mapping) return err; } =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); ptr =3D mte_allocate_memory(TEST_UNIT * page_sz, mem_type, mapping, true); if (check_allocated_memory(ptr, TEST_UNIT * page_sz, mem_type, false) != =3D KSFT_PASS) return KSFT_FAIL; diff --git a/tools/testing/selftests/arm64/mte/check_mmap_options.c b/tools= /testing/selftests/arm64/mte/check_mmap_options.c index 4f26617c8e69..d4193377b406 100644 --- a/tools/testing/selftests/arm64/mte/check_mmap_options.c +++ b/tools/testing/selftests/arm64/mte/check_mmap_options.c @@ -81,7 +81,7 @@ static int check_anonymous_memory_mapping(int mem_type, i= nt mode, int mapping, i int run, result, map_size; int item =3D ARRAY_SIZE(sizes); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < item; run++) { map_size =3D sizes[run] + OVERFLOW + UNDERFLOW; map_ptr =3D (char *)mte_allocate_memory(map_size, mem_type, mapping, fal= se); @@ -113,7 +113,7 @@ static int check_file_memory_mapping(int mem_type, int = mode, int mapping, int ta int total =3D ARRAY_SIZE(sizes); int result =3D KSFT_PASS; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < total; run++) { fd =3D create_temp_file(); if (fd =3D=3D -1) @@ -152,7 +152,7 @@ static int check_clear_prot_mte_flag(int mem_type, int = mode, int mapping, int at int total =3D ARRAY_SIZE(sizes); =20 prot_flag =3D PROT_READ | PROT_WRITE; - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); for (run =3D 0; run < total; run++) { map_size =3D sizes[run] + OVERFLOW + UNDERFLOW; ptr =3D (char *)mte_allocate_memory_tag_range(sizes[run], mem_type, mapp= ing, diff --git a/tools/testing/selftests/arm64/mte/check_tags_inclusion.c b/too= ls/testing/selftests/arm64/mte/check_tags_inclusion.c index b96296ab9870..4b764f2a8185 100644 --- a/tools/testing/selftests/arm64/mte/check_tags_inclusion.c +++ b/tools/testing/selftests/arm64/mte/check_tags_inclusion.c @@ -57,7 +57,7 @@ static int check_single_included_tags(int mem_type, int m= ode) return KSFT_FAIL; =20 for (tag =3D 0; (tag < MT_TAG_COUNT) && (result =3D=3D KSFT_PASS); tag++)= { - ret =3D mte_switch_mode(mode, MT_INCLUDE_VALID_TAG(tag)); + ret =3D mte_switch_mode(mode, MT_INCLUDE_VALID_TAG(tag), false); if (ret !=3D 0) result =3D KSFT_FAIL; /* Try to catch a excluded tag by a number of tries. */ @@ -91,7 +91,7 @@ static int check_multiple_included_tags(int mem_type, int= mode) =20 for (tag =3D 0; (tag < MT_TAG_COUNT - 1) && (result =3D=3D KSFT_PASS); ta= g++) { excl_mask |=3D 1 << tag; - mte_switch_mode(mode, MT_INCLUDE_VALID_TAGS(excl_mask)); + mte_switch_mode(mode, MT_INCLUDE_VALID_TAGS(excl_mask), false); /* Try to catch a excluded tag by a number of tries. */ for (run =3D 0; (run < RUNS) && (result =3D=3D KSFT_PASS); run++) { ptr =3D mte_insert_tags(ptr, BUFFER_SIZE); @@ -120,7 +120,7 @@ static int check_all_included_tags(int mem_type, int mo= de) mem_type, false) !=3D KSFT_PASS) return KSFT_FAIL; =20 - ret =3D mte_switch_mode(mode, MT_INCLUDE_TAG_MASK); + ret =3D mte_switch_mode(mode, MT_INCLUDE_TAG_MASK, false); if (ret !=3D 0) return KSFT_FAIL; /* Try to catch a excluded tag by a number of tries. */ @@ -145,7 +145,7 @@ static int check_none_included_tags(int mem_type, int m= ode) if (check_allocated_memory(ptr, BUFFER_SIZE, mem_type, false) !=3D KSFT_P= ASS) return KSFT_FAIL; =20 - ret =3D mte_switch_mode(mode, MT_EXCLUDE_TAG_MASK); + ret =3D mte_switch_mode(mode, MT_EXCLUDE_TAG_MASK, false); if (ret !=3D 0) return KSFT_FAIL; /* Try to catch a excluded tag by a number of tries. */ diff --git a/tools/testing/selftests/arm64/mte/check_user_mem.c b/tools/tes= ting/selftests/arm64/mte/check_user_mem.c index d1d14aaaba16..fb7936c4e097 100644 --- a/tools/testing/selftests/arm64/mte/check_user_mem.c +++ b/tools/testing/selftests/arm64/mte/check_user_mem.c @@ -44,7 +44,7 @@ static int check_usermem_access_fault(int mem_type, int m= ode, int mapping, =20 err =3D KSFT_PASS; len =3D 2 * page_sz; - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); fd =3D create_temp_file(); if (fd =3D=3D -1) return KSFT_FAIL; diff --git a/tools/testing/selftests/arm64/mte/mte_common_util.c b/tools/te= sting/selftests/arm64/mte/mte_common_util.c index 47e5f940b804..d0da7ee82696 100644 --- a/tools/testing/selftests/arm64/mte/mte_common_util.c +++ b/tools/testing/selftests/arm64/mte/mte_common_util.c @@ -28,8 +28,10 @@ =20 struct mte_fault_cxt cur_mte_cxt; bool mtefar_support; +bool mtestonly_support; static unsigned int mte_cur_mode; static unsigned int mte_cur_pstate_tco; +static bool mte_cur_stonly; =20 void mte_default_handler(int signum, siginfo_t *si, void *uc) { @@ -316,7 +318,7 @@ void mte_initialize_current_context(int mode, uintptr_t= ptr, ssize_t range) cur_mte_cxt.trig_si_code =3D 0; } =20 -int mte_switch_mode(int mte_option, unsigned long incl_mask) +int mte_switch_mode(int mte_option, unsigned long incl_mask, bool stonly) { unsigned long en =3D 0; =20 @@ -348,6 +350,9 @@ int mte_switch_mode(int mte_option, unsigned long incl_= mask) break; } =20 + if (mtestonly_support && stonly) + en |=3D PR_MTE_STORE_ONLY; + en |=3D (incl_mask << PR_MTE_TAG_SHIFT); /* Enable address tagging ABI, mte error reporting mode and tag inclusion= mask. */ if (prctl(PR_SET_TAGGED_ADDR_CTRL, en, 0, 0, 0) !=3D 0) { @@ -370,6 +375,9 @@ int mte_default_setup(void) if (hwcaps3 & HWCAP3_MTE_FAR) mtefar_support =3D true; =20 + if (hwcaps3 & HWCAP3_MTE_STORE_ONLY) + mtestonly_support =3D true; + /* Get current mte mode */ ret =3D prctl(PR_GET_TAGGED_ADDR_CTRL, en, 0, 0, 0); if (ret < 0) { @@ -383,6 +391,8 @@ int mte_default_setup(void) else if (ret & PR_MTE_TCF_NONE) mte_cur_mode =3D MTE_NONE_ERR; =20 + mte_cur_stonly =3D (ret & PR_MTE_STORE_ONLY) ? true : false; + mte_cur_pstate_tco =3D mte_get_pstate_tco(); /* Disable PSTATE.TCO */ mte_disable_pstate_tco(); @@ -391,7 +401,7 @@ int mte_default_setup(void) =20 void mte_restore_setup(void) { - mte_switch_mode(mte_cur_mode, MTE_ALLOW_NON_ZERO_TAG); + mte_switch_mode(mte_cur_mode, MTE_ALLOW_NON_ZERO_TAG, mte_cur_stonly); if (mte_cur_pstate_tco =3D=3D MT_PSTATE_TCO_EN) mte_enable_pstate_tco(); else if (mte_cur_pstate_tco =3D=3D MT_PSTATE_TCO_DIS) diff --git a/tools/testing/selftests/arm64/mte/mte_common_util.h b/tools/te= sting/selftests/arm64/mte/mte_common_util.h index 7dbb5e1046ae..567d299b393c 100644 --- a/tools/testing/selftests/arm64/mte/mte_common_util.h +++ b/tools/testing/selftests/arm64/mte/mte_common_util.h @@ -40,6 +40,7 @@ struct mte_fault_cxt { =20 extern struct mte_fault_cxt cur_mte_cxt; extern bool mtefar_support; +extern bool mtestonly_support; =20 /* MTE utility functions */ void mte_default_handler(int signum, siginfo_t *si, void *uc); @@ -62,7 +63,7 @@ void *mte_insert_atag(void *ptr); void *mte_clear_atag(void *ptr); int mte_default_setup(void); void mte_restore_setup(void); -int mte_switch_mode(int mte_option, unsigned long incl_mask); +int mte_switch_mode(int mte_option, unsigned long incl_mask, bool stonly); void mte_initialize_current_context(int mode, uintptr_t ptr, ssize_t range= ); =20 /* Common utility functions */ --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sun Feb 8 19:24:49 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 73CCA28BA80 for ; Wed, 7 May 2025 15:47:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632850; cv=none; b=prdrqFNkJ6+aoUmGpstdjjs8CsWQ30ly3gamqGVe0CVGACRg72bD3fYxGhu0bFk8XZkrkhYYrs3gedkjxjSmC5tyyEmVA7xQb5tmUizNVFOdGSUuE14EJzN8n1sim8A9d9B8AElEDlDyHa+iC12lTjXDfvwaepwwnRUDwT07Lmo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746632850; c=relaxed/simple; bh=/+1U4shG5AoMx127wEMz8Df1UZJH4I+6oRT2ihxCr0M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZQql0G9em6U6k5S3NS8e9sRh39h5gcgCdqDvH3M8vE5awj56101hBTEprVe5MHLLMyS3rARdTMc4YC9zEr6FhH5CMDGoI9wSUtv/6U8v8rx9CFdTZfl0KWjdGpeiW01G3imL3/TIE26roMmeYQ+T50Hs4shwJqQj5LJoP3KAf4g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A723F339; Wed, 7 May 2025 08:47:17 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 297773F58B; Wed, 7 May 2025 08:47:24 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, pcc@google.com, will@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, frederic@kernel.org, james.morse@arm.com, hardevsinh.palaniya@siliconsignals.io, huangxiaojia2@huawei.com, mark.rutland@arm.com, samuel.holland@sifive.com, palmer@rivosinc.com, charlie@rivosinc.com, thiago.bauermann@linaro.org, bgray@linux.ibm.com, tglx@linutronix.de, puranjay@kernel.org, david@redhat.com, yang@os.amperecomputing.com, mbenes@suse.cz, joel.granados@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH v4 7/7] kselftest/arm64/mte: add MTE_STORE_ONLY testcases Date: Wed, 7 May 2025 16:46:54 +0100 Message-Id: <20250507154654.1937588-8-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507154654.1937588-1-yeoreum.yun@arm.com> References: <20250507154654.1937588-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since ARMv8.9, FEAT_MTE_STORE_ONLY can be used to restrict raise of tag check fault on store operation only. Adds new test cases using MTE_STORE_ONLY feature. Signed-off-by: Yeoreum Yun --- .../selftests/arm64/mte/check_mmap_options.c | 114 ++++++++++++------ .../testing/selftests/arm64/mte/check_prctl.c | 25 ++-- 2 files changed, 95 insertions(+), 44 deletions(-) diff --git a/tools/testing/selftests/arm64/mte/check_mmap_options.c b/tools= /testing/selftests/arm64/mte/check_mmap_options.c index d4193377b406..b9db3e05565e 100644 --- a/tools/testing/selftests/arm64/mte/check_mmap_options.c +++ b/tools/testing/selftests/arm64/mte/check_mmap_options.c @@ -34,15 +34,19 @@ #define ATAG_TEST_ON 1 #define ATAG_TEST_OFF 0 =20 +#define TAG_OP_ALL 0 +#define TAG_OP_STONLY 1 + static size_t page_size; static int sizes[] =3D { 1, 537, 989, 1269, MT_GRANULE_SIZE - 1, MT_GRANULE_SIZE, /* page size - 1*/ 0, /* page_size */ 0, /* page size + 1 */ 0 }; =20 -static int check_mte_memory(char *ptr, int size, int mode, int tag_check, = int atag_test) +static int check_mte_memory(char *ptr, int size, int mode, + int tag_check,int atag_test, int tag_op) { - int err; + char buf[MT_GRANULE_SIZE]; =20 if (!mtefar_support && atag_test =3D=3D ATAG_TEST_ON) return KSFT_SKIP; @@ -72,16 +76,34 @@ static int check_mte_memory(char *ptr, int size, int mo= de, int tag_check, int at if (cur_mte_cxt.fault_valid =3D=3D true && tag_check =3D=3D TAG_CHECK_OFF) return KSFT_FAIL; =20 + if (tag_op =3D=3D TAG_OP_STONLY) { + mte_initialize_current_context(mode, (uintptr_t)ptr, -UNDERFLOW); + memcpy(buf, ptr - UNDERFLOW, MT_GRANULE_SIZE); + mte_wait_after_trig(); + if (cur_mte_cxt.fault_valid =3D=3D true) + return KSFT_FAIL; + + mte_initialize_current_context(mode, (uintptr_t)ptr, size + OVERFLOW); + memcpy(buf, ptr + size, MT_GRANULE_SIZE); + mte_wait_after_trig(); + if (cur_mte_cxt.fault_valid =3D=3D true) + return KSFT_FAIL; + } + return KSFT_PASS; } =20 -static int check_anonymous_memory_mapping(int mem_type, int mode, int mapp= ing, int tag_check, int atag_test) +static int check_anonymous_memory_mapping(int mem_type, int mode, int mapp= ing, + int tag_check, int atag_test, int tag_op) { char *ptr, *map_ptr; int run, result, map_size; int item =3D ARRAY_SIZE(sizes); =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); + if (tag_op =3D=3D TAG_OP_STONLY && !mtestonly_support) + return KSFT_SKIP; + + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, tag_op); for (run =3D 0; run < item; run++) { map_size =3D sizes[run] + OVERFLOW + UNDERFLOW; map_ptr =3D (char *)mte_allocate_memory(map_size, mem_type, mapping, fal= se); @@ -97,7 +119,7 @@ static int check_anonymous_memory_mapping(int mem_type, = int mode, int mapping, i munmap((void *)map_ptr, map_size); return KSFT_FAIL; } - result =3D check_mte_memory(ptr, sizes[run], mode, tag_check, atag_test); + result =3D check_mte_memory(ptr, sizes[run], mode, tag_check, atag_test,= tag_op); mte_clear_tags((void *)ptr, sizes[run]); mte_free_memory((void *)map_ptr, map_size, mem_type, false); if (result !=3D KSFT_SKIP) @@ -106,14 +128,18 @@ static int check_anonymous_memory_mapping(int mem_typ= e, int mode, int mapping, i return KSFT_PASS; } =20 -static int check_file_memory_mapping(int mem_type, int mode, int mapping, = int tag_check, int atag_test) +static int check_file_memory_mapping(int mem_type, int mode, int mapping, + int tag_check, int atag_test, int tag_op) { char *ptr, *map_ptr; int run, fd, map_size; int total =3D ARRAY_SIZE(sizes); int result =3D KSFT_PASS; =20 - mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, false); + if (tag_op =3D=3D TAG_OP_STONLY && !mtestonly_support) + return KSFT_SKIP; + + mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG, tag_op); for (run =3D 0; run < total; run++) { fd =3D create_temp_file(); if (fd =3D=3D -1) @@ -135,7 +161,7 @@ static int check_file_memory_mapping(int mem_type, int = mode, int mapping, int ta close(fd); return KSFT_FAIL; } - result =3D check_mte_memory(ptr, sizes[run], mode, tag_check, atag_test); + result =3D check_mte_memory(ptr, sizes[run], mode, tag_check, atag_test,= tag_op); mte_clear_tags((void *)ptr, sizes[run]); munmap((void *)map_ptr, map_size); close(fd); @@ -168,7 +194,7 @@ static int check_clear_prot_mte_flag(int mem_type, int = mode, int mapping, int at ksft_print_msg("FAIL: mprotect not ignoring clear PROT_MTE property\n"); return KSFT_FAIL; } - result =3D check_mte_memory(ptr, sizes[run], mode, TAG_CHECK_ON, atag_te= st); + result =3D check_mte_memory(ptr, sizes[run], mode, TAG_CHECK_ON, atag_te= st, TAG_OP_ALL); mte_free_memory_tag_range((void *)ptr, sizes[run], mem_type, UNDERFLOW, = OVERFLOW); if (result !=3D KSFT_PASS) return result; @@ -192,7 +218,7 @@ static int check_clear_prot_mte_flag(int mem_type, int = mode, int mapping, int at close(fd); return KSFT_FAIL; } - result =3D check_mte_memory(ptr, sizes[run], mode, TAG_CHECK_ON, atag_te= st); + result =3D check_mte_memory(ptr, sizes[run], mode, TAG_CHECK_ON, atag_te= st, TAG_OP_ALL); mte_free_memory_tag_range((void *)ptr, sizes[run], mem_type, UNDERFLOW, = OVERFLOW); close(fd); if (result !=3D KSFT_PASS) @@ -202,7 +228,7 @@ static int check_clear_prot_mte_flag(int mem_type, int = mode, int mapping, int at } =20 const char *format_test_name(int check_type, int mem_type, int sync, - int mapping, int tag_check, int atag_test) + int mapping, int tag_check, int atag_test, int tag_op) { static char test_name[TEST_NAME_MAX]; const char* check_type_str; @@ -211,6 +237,7 @@ const char *format_test_name(int check_type, int mem_ty= pe, int sync, const char* mapping_str; const char* tag_check_str; const char *atag_test_str; + const char *tag_op_str; =20 switch (check_type) { case CHECK_ANON_MEM: @@ -290,10 +317,22 @@ const char *format_test_name(int check_type, int mem_= type, int sync, break; } =20 + switch (tag_op) { + case TAG_OP_ALL: + tag_op_str =3D ""; + break; + case TAG_OP_STONLY: + tag_op_str =3D " / store-only"; + break; + default: + assert(0); + break; + } + snprintf(test_name, TEST_NAME_MAX, - "Check %s with %s mapping, %s mode, %s memory and %s (%s)\n", + "Check %s with %s mapping, %s mode, %s memory and %s (%s%s)\n", check_type_str, mapping_str, sync_str, mem_type_str, - tag_check_str, atag_test_str); + tag_check_str, atag_test_str, tag_op_str); =20 return test_name; } @@ -307,7 +346,8 @@ int main(int argc, char *argv[]) int mte_sync[] =3D { MTE_SYNC_ERR, MTE_ASYNC_ERR }; int mapping[] =3D { MAP_PRIVATE, MAP_SHARED }; int atag_test[] =3D { ATAG_TEST_OFF, ATAG_TEST_ON }; - int c, mt, s, m, a; + int tag_ops[] =3D { TAG_OP_ALL, TAG_OP_STONLY }; + int c, mt, s, m, a, o; =20 err =3D mte_default_setup(); if (err) @@ -322,7 +362,7 @@ int main(int argc, char *argv[]) sizes[item - 1] =3D page_size + 1; =20 /* Set test plan */ - ksft_set_plan(44); + ksft_set_plan(76); =20 for (a =3D 0; a < ARRAY_SIZE(atag_test); a++) { /* Register signal handlers */ @@ -331,38 +371,40 @@ int main(int argc, char *argv[]) =20 mte_enable_pstate_tco(); =20 - evaluate_test(check_anonymous_memory_mapping(USE_MMAP, MTE_SYNC_ERR, MAP= _PRIVATE, TAG_CHECK_OFF, atag_test[a]), - format_test_name(CHECK_ANON_MEM, USE_MMAP, MTE_SYNC_ERR, MAP_PRIV= ATE, TAG_CHECK_OFF, atag_test[a])); + evaluate_test(check_anonymous_memory_mapping(USE_MMAP, MTE_SYNC_ERR, MAP= _PRIVATE, TAG_CHECK_OFF, atag_test[a], TAG_OP_ALL), + format_test_name(CHECK_ANON_MEM, USE_MMAP, MTE_SYNC_ERR, MAP_PRIV= ATE, TAG_CHECK_OFF, atag_test[a], TAG_OP_ALL)); =20 - evaluate_test(check_file_memory_mapping(USE_MPROTECT, MTE_SYNC_ERR, MAP_= PRIVATE, TAG_CHECK_OFF, atag_test[a]), - format_test_name(CHECK_FILE_MEM, USE_MPROTECT, MTE_SYNC_ERR, MAP_= PRIVATE, TAG_CHECK_OFF, atag_test[a])); + evaluate_test(check_file_memory_mapping(USE_MPROTECT, MTE_SYNC_ERR, MAP_= PRIVATE, TAG_CHECK_OFF, atag_test[a], TAG_OP_ALL), + format_test_name(CHECK_FILE_MEM, USE_MPROTECT, MTE_SYNC_ERR, MAP_= PRIVATE, TAG_CHECK_OFF, atag_test[a], TAG_OP_ALL)); =20 mte_disable_pstate_tco(); =20 - evaluate_test(check_anonymous_memory_mapping(USE_MMAP, MTE_NONE_ERR, MAP= _PRIVATE, TAG_CHECK_OFF, atag_test[a]), - format_test_name(CHECK_ANON_MEM, USE_MMAP, MTE_NONE_ERR, MAP_PRIV= ATE, TAG_CHECK_OFF, atag_test[a])); - evaluate_test(check_file_memory_mapping(USE_MPROTECT, MTE_NONE_ERR, MAP_= PRIVATE, TAG_CHECK_OFF, atag_test[a]), - format_test_name(CHECK_FILE_MEM, USE_MPROTECT, MTE_NONE_ERR, MAP_= PRIVATE, TAG_CHECK_OFF, atag_test[a])); - - for (c =3D 0 ; c < ARRAY_SIZE(check_type); c++) { - for (s =3D 0; s < ARRAY_SIZE(mte_sync); s++) { - for (m =3D 0; m < ARRAY_SIZE(mapping); m++) { - for (mt =3D 0; mt < ARRAY_SIZE(mem_type); mt++) { - if (check_type[c] =3D=3D CHECK_ANON_MEM) - evaluate_test(check_anonymous_memory_mapping(mem_type[mt], mte_sync= [s], mapping[m], TAG_CHECK_ON, atag_test[a]), - format_test_name(CHECK_ANON_MEM, mem_type[mt], mte_sync[s], mappin= g[m], TAG_CHECK_ON, atag_test[a])); - else - evaluate_test(check_file_memory_mapping(mem_type[mt], mte_sync[s], = mapping[m], TAG_CHECK_ON, atag_test[a]), - format_test_name(CHECK_FILE_MEM, mem_type[mt], mte_sync[s], mappin= g[m], TAG_CHECK_ON, atag_test[a])); + evaluate_test(check_anonymous_memory_mapping(USE_MMAP, MTE_NONE_ERR, MAP= _PRIVATE, TAG_CHECK_OFF, atag_test[a], TAG_OP_ALL), + format_test_name(CHECK_ANON_MEM, USE_MMAP, MTE_NONE_ERR, MAP_PRIV= ATE, TAG_CHECK_OFF, atag_test[a], TAG_OP_ALL)); + evaluate_test(check_file_memory_mapping(USE_MPROTECT, MTE_NONE_ERR, MAP_= PRIVATE, TAG_CHECK_OFF, atag_test[a], TAG_OP_ALL), + format_test_name(CHECK_FILE_MEM, USE_MPROTECT, MTE_NONE_ERR, MAP_= PRIVATE, TAG_CHECK_OFF, atag_test[a], TAG_OP_ALL)); + + for (o =3D 0; o < ARRAY_SIZE(tag_ops); o++) { + for (c =3D 0 ; c < ARRAY_SIZE(check_type); c++) { + for (s =3D 0; s < ARRAY_SIZE(mte_sync); s++) { + for (m =3D 0; m < ARRAY_SIZE(mapping); m++) { + for (mt =3D 0; mt < ARRAY_SIZE(mem_type); mt++) { + if (check_type[c] =3D=3D CHECK_ANON_MEM) + evaluate_test(check_anonymous_memory_mapping(mem_type[mt], mte_syn= c[s], mapping[m], TAG_CHECK_ON, atag_test[a], tag_ops[o]), + format_test_name(CHECK_ANON_MEM, mem_type[mt], mte_sync[s], mappi= ng[m], TAG_CHECK_ON, atag_test[a], tag_ops[o])); + else + evaluate_test(check_file_memory_mapping(mem_type[mt], mte_sync[s],= mapping[m], TAG_CHECK_ON, atag_test[a], tag_ops[o]), + format_test_name(CHECK_FILE_MEM, mem_type[mt], mte_sync[s], mappi= ng[m], TAG_CHECK_ON, atag_test[a], tag_ops[o])); + } } } } } =20 evaluate_test(check_clear_prot_mte_flag(USE_MMAP, MTE_SYNC_ERR, MAP_PRIV= ATE, atag_test[a]), - format_test_name(CHECK_CLEAR_PROT_MTE, USE_MMAP, MTE_SYNC_ERR, MA= P_PRIVATE, TAG_CHECK_ON, atag_test[a])); + format_test_name(CHECK_CLEAR_PROT_MTE, USE_MMAP, MTE_SYNC_ERR, MA= P_PRIVATE, TAG_CHECK_ON, atag_test[a], TAG_OP_ALL)); evaluate_test(check_clear_prot_mte_flag(USE_MPROTECT, MTE_SYNC_ERR, MAP_= PRIVATE, atag_test[a]), - format_test_name(CHECK_CLEAR_PROT_MTE, USE_MPROTECT, MTE_SYNC_ERR= , MAP_PRIVATE, TAG_CHECK_ON, atag_test[a])); + format_test_name(CHECK_CLEAR_PROT_MTE, USE_MPROTECT, MTE_SYNC_ERR= , MAP_PRIVATE, TAG_CHECK_ON, atag_test[a], TAG_OP_ALL)); } =20 mte_restore_setup(); diff --git a/tools/testing/selftests/arm64/mte/check_prctl.c b/tools/testin= g/selftests/arm64/mte/check_prctl.c index 4c89e9538ca0..83fa20cc6072 100644 --- a/tools/testing/selftests/arm64/mte/check_prctl.c +++ b/tools/testing/selftests/arm64/mte/check_prctl.c @@ -60,7 +60,7 @@ void check_basic_read(void) /* * Attempt to set a specified combination of modes. */ -void set_mode_test(const char *name, int hwcap2, int mask) +void set_mode_test(const char *name, int hwcap2, int hwcap3, int mask) { int ret; =20 @@ -69,6 +69,11 @@ void set_mode_test(const char *name, int hwcap2, int mas= k) return; } =20 + if ((getauxval(AT_HWCAP3) & hwcap3) !=3D hwcap3) { + ksft_test_result_skip("%s\n", name); + return; + } + ret =3D set_tagged_addr_ctrl(mask); if (ret < 0) { ksft_test_result_fail("%s\n", name); @@ -81,7 +86,7 @@ void set_mode_test(const char *name, int hwcap2, int mask) return; } =20 - if ((ret & PR_MTE_TCF_MASK) =3D=3D mask) { + if ((ret & (PR_MTE_TCF_MASK | PR_MTE_STORE_ONLY)) =3D=3D mask) { ksft_test_result_pass("%s\n", name); } else { ksft_print_msg("Got %x, expected %x\n", @@ -93,12 +98,16 @@ void set_mode_test(const char *name, int hwcap2, int ma= sk) struct mte_mode { int mask; int hwcap2; + int hwcap3; const char *name; } mte_modes[] =3D { - { PR_MTE_TCF_NONE, 0, "NONE" }, - { PR_MTE_TCF_SYNC, HWCAP2_MTE, "SYNC" }, - { PR_MTE_TCF_ASYNC, HWCAP2_MTE, "ASYNC" }, - { PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC, HWCAP2_MTE, "SYNC+ASYNC" }, + { PR_MTE_TCF_NONE, 0, 0, = "NONE" }, + { PR_MTE_TCF_SYNC, HWCAP2_MTE, 0, = "SYNC" }, + { PR_MTE_TCF_ASYNC, HWCAP2_MTE, 0, = "ASYNC" }, + { PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC, HWCAP2_MTE, 0, = "SYNC+ASYNC" }, + { PR_MTE_TCF_SYNC | PR_MTE_STORE_ONLY, HWCAP2_MTE, HWC= AP3_MTE_STORE_ONLY, "SYNC+STONLY" }, + { PR_MTE_TCF_ASYNC | PR_MTE_STORE_ONLY, HWCAP2_MTE, HWC= AP3_MTE_STORE_ONLY, "ASYNC+STONLY" }, + { PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC | PR_MTE_STORE_ONLY, HWCAP2_MTE, HWC= AP3_MTE_STORE_ONLY, "SYNC+ASYNC+STONLY" }, }; =20 int main(void) @@ -106,11 +115,11 @@ int main(void) int i; =20 ksft_print_header(); - ksft_set_plan(5); + ksft_set_plan(8); =20 check_basic_read(); for (i =3D 0; i < ARRAY_SIZE(mte_modes); i++) - set_mode_test(mte_modes[i].name, mte_modes[i].hwcap2, + set_mode_test(mte_modes[i].name, mte_modes[i].hwcap2, mte_modes[i].hwcap= 3, mte_modes[i].mask); =20 ksft_print_cnts(); --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}