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On larger systems this causes massive lock contention when the configuration space has to be accessed frequently. One such access pattern is the Intel Uncore performance counter unit. All x86 PCI configuration space accessors have either their own serialization or can operate completely lockless, So Disable the global lock in the generic PCI configuration space accessors Signed-off-by: Zijiang Huang Reviewed-by: Hao Peng --- drivers/pci/access.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/pci/access.c b/drivers/pci/access.c index 3c230ca3d..5200f7bbc 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -216,20 +216,21 @@ static noinline void pci_wait_cfg(struct pci_dev *dev) } =20 /* Returns 0 on success, negative values indicate error. */ -#define PCI_USER_READ_CONFIG(size, type) \ +#define PCI_USER_READ_CONFIG(size, type) \ int pci_user_read_config_##size \ (struct pci_dev *dev, int pos, type *val) \ { \ int ret =3D PCIBIOS_SUCCESSFUL; \ u32 data =3D -1; \ + unsigned long flags; \ if (PCI_##size##_BAD) \ return -EINVAL; \ - raw_spin_lock_irq(&pci_lock); \ + pci_lock_config(flags); \ if (unlikely(dev->block_cfg_access)) \ pci_wait_cfg(dev); \ ret =3D dev->bus->ops->read(dev->bus, dev->devfn, \ pos, sizeof(type), &data); \ - raw_spin_unlock_irq(&pci_lock); \ + pci_unlock_config(flags); \ if (ret) \ PCI_SET_ERROR_RESPONSE(val); \ else \ @@ -244,14 +245,15 @@ int pci_user_write_config_##size \ (struct pci_dev *dev, int pos, type val) \ { \ int ret =3D PCIBIOS_SUCCESSFUL; \ + unsigned long flags; \ if (PCI_##size##_BAD) \ return -EINVAL; \ - raw_spin_lock_irq(&pci_lock); \ + pci_lock_config(flags); \ if (unlikely(dev->block_cfg_access)) \ pci_wait_cfg(dev); \ ret =3D dev->bus->ops->write(dev->bus, dev->devfn, \ pos, sizeof(type), val); \ - raw_spin_unlock_irq(&pci_lock); \ + pci_unlock_config(flags); \ return pcibios_err_to_errno(ret); \ } \ EXPORT_SYMBOL_GPL(pci_user_write_config_##size); --=20 2.43.5