From nobody Wed Dec 17 04:16:57 2025 Received: from mx.treblig.org (mx.treblig.org [46.235.229.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38DAB8C1E for ; Wed, 7 May 2025 00:24:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.229.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746577475; cv=none; b=tlRJbJN5Rzlx/YEa1ULPtzXAoD37gOUf75BzVjAe0RfpmoDEFX50n79U7Mik/zNYLr/IdFY9YhzvSUVYmBTun3GD6nqPAbOh5h3I6FaiRSlY6VVDabtGiVtsaziJqPlRKwVY+JxcPA3ne1MEQLlnp8YfmsuGvwz2mfjCic2jp3E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746577475; c=relaxed/simple; bh=ItTn6ZUW7IH3rzHIL1nvf1Ic5CHn7dYvyllDewHVc14=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bp7/jkFqdrwktZZEWqBkKB/DpxfkqKgZZ8yHocfyjFmEc567XZXc3+d33UFDoMbOnX1EfqHrbQul1xw1pmBgyLbd+jATYj+7+8TDHen8gVQkg0cfbBonaQZWMvvP6DEojWkhs0DOQW6QONJxlCLZdHTRbPnbE3wrYTXIWeF25ps= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=treblig.org; spf=pass smtp.mailfrom=treblig.org; dkim=pass (2048-bit key) header.d=treblig.org header.i=@treblig.org header.b=GA5hGdzJ; arc=none smtp.client-ip=46.235.229.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=treblig.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=treblig.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=treblig.org header.i=@treblig.org header.b="GA5hGdzJ" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=treblig.org ; s=bytemarkmx; h=MIME-Version:Message-ID:Date:Subject:From:Content-Type:From :Subject; bh=Vt4x2NR9rZy0McKBk09pp7yXo99XRz0SlCyk5eqZpBI=; b=GA5hGdzJ6Oe6wu2y 6GLarlrWVoLlNdhVlOT7/uWxOdVD0cUcX5YsCyD6ImRdYiAPgiXKwj/FIz6aQB2nFHubh4NnpLrAm t5f68xtgKIYW4JKyE8Hbnuzq2J8gUwRAg5f1SNCW24koqGt1hgUdYFJDPcvP/B0MN3rBSKvlZsBjU J49I9bP81lG6KttgJFaRfcXOT7ZU59O6nOmZaGg8dGQUU9v8F52GSb5i1jd0AOAqvt1nznnkQ9vnN ARoX1u4mdevxOiANkraKgtqmdu1NGd7bNwrUp+6V8E6AdMDbF3XTJu4TvO9xmgiiGtM6nS2r6ct9k /TwjAF3T9LPEPn910w==; Received: from localhost ([127.0.0.1] helo=dalek.home.treblig.org) by mx.treblig.org with esmtp (Exim 4.96) (envelope-from ) id 1uCSaI-0021Kc-0h; Wed, 07 May 2025 00:24:26 +0000 From: linux@treblig.org To: alexander.deucher@amd.com, kenneth.feng@amd.com, christian.koenig@amd.com Cc: airlied@gmail.com, simona@ffwll.ch, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, "Dr. David Alan Gilbert" Subject: [PATCH 1/3] drm/amd/pm/smu7: Remove unused smu7_copy_bytes_from_smc Date: Wed, 7 May 2025 01:24:23 +0100 Message-ID: <20250507002425.93421-2-linux@treblig.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250507002425.93421-1-linux@treblig.org> References: <20250507002425.93421-1-linux@treblig.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Dr. David Alan Gilbert" smu7_copy_bytes_from_smc() was added in 2016 by commit 1ff55f465103 ("drm/amd/powerplay: implement smu7_smumgr for asics with smu ip version 7.") but never used. Remove it. Signed-off-by: Dr. David Alan Gilbert --- .../drm/amd/pm/powerplay/smumgr/smu7_smumgr.c | 36 ------------------- .../drm/amd/pm/powerplay/smumgr/smu7_smumgr.h | 2 -- 2 files changed, 38 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c b/driver= s/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c index 5a010cd38303..baf51cd82a35 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c @@ -46,42 +46,6 @@ static int smu7_set_smc_sram_address(struct pp_hwmgr *hw= mgr, uint32_t smc_addr, } =20 =20 -int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_ad= dress, uint32_t *dest, uint32_t byte_count, uint32_t limit) -{ - uint32_t data; - uint32_t addr; - uint8_t *dest_byte; - uint8_t i, data_byte[4] =3D {0}; - uint32_t *pdata =3D (uint32_t *)&data_byte; - - PP_ASSERT_WITH_CODE((0 =3D=3D (3 & smc_start_address)), "SMC address must= be 4 byte aligned.", return -EINVAL); - PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC addr= ess is beyond the SMC RAM area.", return -EINVAL); - - addr =3D smc_start_address; - - while (byte_count >=3D 4) { - smu7_read_smc_sram_dword(hwmgr, addr, &data, limit); - - *dest =3D PP_SMC_TO_HOST_UL(data); - - dest +=3D 1; - byte_count -=3D 4; - addr +=3D 4; - } - - if (byte_count) { - smu7_read_smc_sram_dword(hwmgr, addr, &data, limit); - *pdata =3D PP_SMC_TO_HOST_UL(data); - /* Cast dest into byte type in dest_byte. This way, we don't overflow if= the allocated memory is not 4-byte aligned. */ - dest_byte =3D (uint8_t *)dest; - for (i =3D 0; i < byte_count; i++) - dest_byte[i] =3D data_byte[i]; - } - - return 0; -} - - int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_addr= ess, const uint8_t *src, uint32_t byte_count, uint32_t limit) { diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h b/driver= s/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h index e7303dc8c260..63e428ceaee4 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h @@ -53,8 +53,6 @@ struct smu7_smumgr { }; =20 =20 -int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_ad= dress, - uint32_t *dest, uint32_t byte_count, uint32_t limit); int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_addr= ess, const uint8_t *src, uint32_t byte_count, uint32_t limit); int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr); --=20 2.49.0 From nobody Wed Dec 17 04:16:57 2025 Received: from mx.treblig.org (mx.treblig.org [46.235.229.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38DDAF4E2 for ; Wed, 7 May 2025 00:24:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.229.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746577474; cv=none; b=YOJxBBjSLnFu4oFxbCgyWiHlA2MLsAGk6SsVNcET+0AIHiDqbn6CoRqeY6pmwXhd12ub6zn/7EnghsIvaGC/CFkic+Q35gWQaTkCxbXC1w9g5BRFawQCueoELKxmrsXh0NOLknyKchnoyBR6OSKexEhaATAeU3xJNQl29bVSSGw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746577474; c=relaxed/simple; bh=mgRHUO5kly8vgVg2eQnOQsu6uX+8Zl1l2MUALqAAMnY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=abwYMngJ57PFzbrbDUg//DhW3G7alb+P/arVU/I5By1Q6erVXZIDCung56RTDU2zXZEz29BFtvOggaJnyid64HXeYDcJGSR0R2JFIC0cZCk5robB+8mfLHKKxQVU6JIk76j/QkkJDSDB7xqnLlx+R2O4vytfhB/OObky5Ow0V1o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=treblig.org; spf=pass smtp.mailfrom=treblig.org; dkim=pass (2048-bit key) header.d=treblig.org header.i=@treblig.org header.b=HF+/InVA; arc=none smtp.client-ip=46.235.229.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=treblig.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=treblig.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=treblig.org header.i=@treblig.org header.b="HF+/InVA" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=treblig.org ; s=bytemarkmx; h=MIME-Version:Message-ID:Date:Subject:From:Content-Type:From :Subject; bh=409FBbvDS2Us+ovAjAHcsc9xHm8JBy90GPNyffM0qoU=; b=HF+/InVAf8DFiG1p Xcz9dHF2r4H4tNXgV6XwSdKDucX1f/Ja/RjPdahEDpJaiS1UAkqK4nUrkSRJOvwtZhCvIil4o4tA3 tnLO61iOm2iX+7DAtrHD2J2a7jZVvhbjq/kLwLuIdegBEJfHtQD/7cx1HE7/13Z0F7pidxbSRBupn kY286Ll7J7blspcexphXgTYdW+xcAmL+dIM6Q0RIs4CAyYM/vQIbg57NeWjVq4+OD68tsc2g8OJgO RjnxdtXEA5a9e7OXIPJQ1zXWDwDgk3e3QSlnbpU32ymhpO3JWcZgmKlcit377WJcvXXb9/qoyb4jX X6ab79rpey9mq7HGRA==; Received: from localhost ([127.0.0.1] helo=dalek.home.treblig.org) by mx.treblig.org with esmtp (Exim 4.96) (envelope-from ) id 1uCSaI-0021Kc-2M; Wed, 07 May 2025 00:24:26 +0000 From: linux@treblig.org To: alexander.deucher@amd.com, kenneth.feng@amd.com, christian.koenig@amd.com Cc: airlied@gmail.com, simona@ffwll.ch, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, "Dr. David Alan Gilbert" Subject: [PATCH 2/3] drm/amd/pm/smu11: Remove unused smu_v11_0_get_dpm_level_range Date: Wed, 7 May 2025 01:24:24 +0100 Message-ID: <20250507002425.93421-3-linux@treblig.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250507002425.93421-1-linux@treblig.org> References: <20250507002425.93421-1-linux@treblig.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Dr. David Alan Gilbert" The last use of smu_v11_0_get_dpm_level_range() was removed in 2020 by commit 46a301e14e8a ("drm/amd/powerplay: drop unnecessary Navi1x specific APIs") Remove it. Signed-off-by: Dr. David Alan Gilbert --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h | 5 --- .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 39 ------------------- 2 files changed, 44 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h b/drivers/gpu/drm= /amd/pm/swsmu/inc/smu_v11_0.h index ed8304d82831..56ae555bb52a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h @@ -281,11 +281,6 @@ int smu_v11_0_set_single_dpm_table(struct smu_context = *smu, enum smu_clk_type clk_type, struct smu_11_0_dpm_table *single_dpm_table); =20 -int smu_v11_0_get_dpm_level_range(struct smu_context *smu, - enum smu_clk_type clk_type, - uint32_t *min_value, - uint32_t *max_value); - int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu); =20 uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/d= rm/amd/pm/swsmu/smu11/smu_v11_0.c index 25fabf336a64..78e4186d06cc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -2059,45 +2059,6 @@ int smu_v11_0_set_single_dpm_table(struct smu_contex= t *smu, return 0; } =20 -int smu_v11_0_get_dpm_level_range(struct smu_context *smu, - enum smu_clk_type clk_type, - uint32_t *min_value, - uint32_t *max_value) -{ - uint32_t level_count =3D 0; - int ret =3D 0; - - if (!min_value && !max_value) - return -EINVAL; - - if (min_value) { - /* by default, level 0 clock value as min value */ - ret =3D smu_v11_0_get_dpm_freq_by_index(smu, - clk_type, - 0, - min_value); - if (ret) - return ret; - } - - if (max_value) { - ret =3D smu_v11_0_get_dpm_level_count(smu, - clk_type, - &level_count); - if (ret) - return ret; - - ret =3D smu_v11_0_get_dpm_freq_by_index(smu, - clk_type, - level_count - 1, - max_value); - if (ret) - return ret; - } - - return ret; -} - int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu) { struct amdgpu_device *adev =3D smu->adev; --=20 2.49.0 From nobody Wed Dec 17 04:16:57 2025 Received: from mx.treblig.org (mx.treblig.org [46.235.229.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38D7E3211 for ; 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Wed, 07 May 2025 00:24:27 +0000 From: linux@treblig.org To: alexander.deucher@amd.com, kenneth.feng@amd.com, christian.koenig@amd.com Cc: airlied@gmail.com, simona@ffwll.ch, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, "Dr. David Alan Gilbert" Subject: [PATCH 3/3] drm/amd/pm/smu13: Remove unused smu_v3 functions Date: Wed, 7 May 2025 01:24:25 +0100 Message-ID: <20250507002425.93421-4-linux@treblig.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250507002425.93421-1-linux@treblig.org> References: <20250507002425.93421-1-linux@treblig.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Dr. David Alan Gilbert" smu_v13_0_display_clock_voltage_request() and smu_v13_0_set_min_deep_sleep_dcefclk() were added in 2020 by commit c05d1c401572 ("drm/amd/swsmu: add aldebaran smu13 ip support (v3)") but have remained unused. Remove them. smu_v13_0_display_clock_voltage_request() was the only user of smu_v13_0_set_hard_freq_limited_range(). Remove it. Signed-off-by: Dr. David Alan Gilbert --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 12 --- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 101 ------------------ 2 files changed, 113 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm= /amd/pm/swsmu/inc/smu_v13_0.h index cd03caffe317..6f74783472e5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -183,13 +183,6 @@ int smu_v13_0_disable_thermal_alert(struct smu_context= *smu); =20 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value); =20 -int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t= clk); - -int -smu_v13_0_display_clock_voltage_request(struct smu_context *smu, - struct pp_display_clock_request - *clock_req); - uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu); =20 @@ -226,11 +219,6 @@ int smu_v13_0_get_dpm_ultimate_freq(struct smu_context= *smu, enum smu_clk_type c int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum sm= u_clk_type clk_type, uint32_t min, uint32_t max, bool automatic); =20 -int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, - enum smu_clk_type clk_type, - uint32_t min, - uint32_t max); - int smu_v13_0_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level); =20 diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/d= rm/amd/pm/swsmu/smu13/smu_v13_0.c index ba5a9012dbd5..03242f65e262 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -709,18 +709,6 @@ int smu_v13_0_notify_memory_pool_location(struct smu_c= ontext *smu) return ret; } =20 -int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t= clk) -{ - int ret; - - ret =3D smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); - if (ret) - dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed= !"); - - return ret; -} - int smu_v13_0_set_driver_table_location(struct smu_context *smu) { struct smu_table *driver_table =3D &smu->smu_table.driver_table; @@ -1073,56 +1061,6 @@ int smu_v13_0_get_gfx_vdd(struct smu_context *smu, u= int32_t *value) =20 } =20 -int -smu_v13_0_display_clock_voltage_request(struct smu_context *smu, - struct pp_display_clock_request - *clock_req) -{ - enum amd_pp_clock_type clk_type =3D clock_req->clock_type; - int ret =3D 0; - enum smu_clk_type clk_select =3D 0; - uint32_t clk_freq =3D clock_req->clock_freq_in_khz / 1000; - - if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || - smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { - switch (clk_type) { - case amd_pp_dcef_clock: - clk_select =3D SMU_DCEFCLK; - break; - case amd_pp_disp_clock: - clk_select =3D SMU_DISPCLK; - break; - case amd_pp_pixel_clock: - clk_select =3D SMU_PIXCLK; - break; - case amd_pp_phy_clock: - clk_select =3D SMU_PHYCLK; - break; - case amd_pp_mem_clock: - clk_select =3D SMU_UCLK; - break; - default: - dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__); - ret =3D -EINVAL; - break; - } - - if (ret) - goto failed; - - if (clk_select =3D=3D SMU_UCLK && smu->disable_uclk_switch) - return 0; - - ret =3D smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq,= 0); - - if (clk_select =3D=3D SMU_UCLK) - smu->hard_min_uclk_req_from_dal =3D clk_freq; - } - -failed: - return ret; -} - uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu) { if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) @@ -1647,45 +1585,6 @@ int smu_v13_0_set_soft_freq_limited_range(struct smu= _context *smu, return ret; } =20 -int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, - enum smu_clk_type clk_type, - uint32_t min, - uint32_t max) -{ - int ret =3D 0, clk_id =3D 0; - uint32_t param; - - if (min <=3D 0 && max <=3D 0) - return -EINVAL; - - if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) - return 0; - - clk_id =3D smu_cmn_to_asic_specific_index(smu, - CMN2ASIC_MAPPING_CLK, - clk_type); - if (clk_id < 0) - return clk_id; - - if (max > 0) { - param =3D (uint32_t)((clk_id << 16) | (max & 0xffff)); - ret =3D smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, - param, NULL); - if (ret) - return ret; - } - - if (min > 0) { - param =3D (uint32_t)((clk_id << 16) | (min & 0xffff)); - ret =3D smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, - param, NULL); - if (ret) - return ret; - } - - return ret; -} - int smu_v13_0_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) { --=20 2.49.0