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Tue, 06 May 2025 23:58:51 -0700 (PDT) From: Alexey Charkov Date: Wed, 07 May 2025 10:58:31 +0400 Subject: [PATCH v2 2/4] clocksource/drivers/timer-vt8500: Add defines for magic constants Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250507-vt8500-timer-updates-v2-2-65e5d1b0855e@gmail.com> References: <20250507-vt8500-timer-updates-v2-0-65e5d1b0855e@gmail.com> In-Reply-To: <20250507-vt8500-timer-updates-v2-0-65e5d1b0855e@gmail.com> To: Krzysztof Kozlowski , Daniel Lezcano , Thomas Gleixner , Rob Herring , Conor Dooley , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746601114; l=4723; i=alchark@gmail.com; s=20250416; h=from:subject:message-id; bh=4CyYsnhnKma2xppJbhsHsOk6fmvNYSaorpOr7AaIMyg=; b=2hmYsIIl3JTTzoNlkemuEqYWoJwtX02w1BOyvcRaRz0UXM/UX9q+mlX+UPe6goxwY67GNIrnI C5lJS7thZ5yCGiPc1qogRSL1ukycQShkcrEdQjnvsiEyLYVQV/ILE0y X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=ltKbQzKLTJPiDgPtcHxdo+dzFthCCMtC3V9qf7+0rkc= Add defines for all known registers and their bits to make the code more self-explanatory. While at that, replace _VAL suffixes with more intuitive _REG suffixes on register offsets. No functional changes. Signed-off-by: Alexey Charkov --- drivers/clocksource/timer-vt8500.c | 65 ++++++++++++++++++++++++----------= ---- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/drivers/clocksource/timer-vt8500.c b/drivers/clocksource/timer= -vt8500.c index a469b1b5f97233202bf01298b9f612e07026c20c..9f28f30dcaf83ab4e9c89952175= b0d4c75bd6b40 100644 --- a/drivers/clocksource/timer-vt8500.c +++ b/drivers/clocksource/timer-vt8500.c @@ -24,15 +24,31 @@ =20 #define VT8500_TIMER_OFFSET 0x0100 #define VT8500_TIMER_HZ 3000000 -#define TIMER_MATCH_VAL 0x0000 -#define TIMER_COUNT_VAL 0x0010 -#define TIMER_STATUS_VAL 0x0014 -#define TIMER_IER_VAL 0x001c /* interrupt enable */ -#define TIMER_CTRL_VAL 0x0020 -#define TIMER_AS_VAL 0x0024 /* access status */ -#define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */ -#define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */ -#define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */ + +#define TIMER_MATCH_REG(x) (4 * (x)) +#define TIMER_COUNT_REG 0x0010 /* clocksource counter */ + +#define TIMER_STATUS_REG 0x0014 +#define TIMER_STATUS_MATCH(x) BIT((x)) +#define TIMER_STATUS_CLEARALL (TIMER_STATUS_MATCH(0) | \ + TIMER_STATUS_MATCH(1) | \ + TIMER_STATUS_MATCH(2) | \ + TIMER_STATUS_MATCH(3)) + +#define TIMER_WATCHDOG_EN_REG 0x0018 +#define TIMER_WD_EN BIT(0) + +#define TIMER_INT_EN_REG 0x001c /* interrupt enable */ +#define TIMER_INT_EN_MATCH(x) BIT((x)) + +#define TIMER_CTRL_REG 0x0020 +#define TIMER_CTRL_ENABLE BIT(0) /* enable clocksource counter */ +#define TIMER_CTRL_RD_REQ BIT(1) /* request counter read */ + +#define TIMER_ACC_STS_REG 0x0024 /* access status */ +#define TIMER_ACC_WR_MATCH(x) BIT((x)) /* writing Match (x) value */ +#define TIMER_ACC_WR_COUNTER BIT(4) /* writing clocksource counter */ +#define TIMER_ACC_RD_COUNTER BIT(5) /* reading clocksource counter */ =20 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) =20 @@ -43,11 +59,12 @@ static void __iomem *regbase; static u64 vt8500_timer_read(struct clocksource *cs) { int loops =3D msecs_to_loops(10); - writel(3, regbase + TIMER_CTRL_VAL); - while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE) - && --loops) + + writel(TIMER_CTRL_ENABLE | TIMER_CTRL_RD_REQ, regbase + TIMER_CTRL_REG); + while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_RD_COUNTER + && --loops) cpu_relax(); - return readl(regbase + TIMER_COUNT_VAL); + return readl(regbase + TIMER_COUNT_REG); } =20 static struct clocksource clocksource =3D { @@ -63,23 +80,25 @@ static int vt8500_timer_set_next_event(unsigned long cy= cles, { int loops =3D msecs_to_loops(10); u64 alarm =3D clocksource.read(&clocksource) + cycles; - while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE) - && --loops) + + while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_WR_MATCH(0) + && --loops) cpu_relax(); - writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); + writel((unsigned long)alarm, regbase + TIMER_MATCH_REG(0)); =20 if ((signed)(alarm - clocksource.read(&clocksource)) <=3D MIN_OSCR_DELTA) return -ETIME; =20 - writel(1, regbase + TIMER_IER_VAL); + writel(TIMER_INT_EN_MATCH(0), regbase + TIMER_INT_EN_REG); =20 return 0; } =20 static int vt8500_shutdown(struct clock_event_device *evt) { - writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL); - writel(0, regbase + TIMER_IER_VAL); + writel(readl(regbase + TIMER_CTRL_REG) | TIMER_CTRL_ENABLE, + regbase + TIMER_CTRL_REG); + writel(0, regbase + TIMER_INT_EN_REG); return 0; } =20 @@ -95,7 +114,7 @@ static struct clock_event_device clockevent =3D { static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt =3D dev_id; - writel(0xf, regbase + TIMER_STATUS_VAL); + writel(TIMER_STATUS_CLEARALL, regbase + TIMER_STATUS_REG); evt->event_handler(evt); =20 return IRQ_HANDLED; @@ -119,9 +138,9 @@ static int __init vt8500_timer_init(struct device_node = *np) return -EINVAL; } =20 - writel(1, regbase + TIMER_CTRL_VAL); - writel(0xf, regbase + TIMER_STATUS_VAL); - writel(~0, regbase + TIMER_MATCH_VAL); + writel(TIMER_CTRL_ENABLE, regbase + TIMER_CTRL_REG); + writel(TIMER_STATUS_CLEARALL, regbase + TIMER_STATUS_REG); + writel(~0, regbase + TIMER_MATCH_REG(0)); =20 ret =3D clocksource_register_hz(&clocksource, VT8500_TIMER_HZ); if (ret) { --=20 2.49.0