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Tue, 06 May 2025 23:58:45 -0700 (PDT) From: Alexey Charkov Date: Wed, 07 May 2025 10:58:30 +0400 Subject: [PATCH v2 1/4] dt-bindings: timer: via,vt8500-timer: Convert to YAML Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250507-vt8500-timer-updates-v2-1-65e5d1b0855e@gmail.com> References: <20250507-vt8500-timer-updates-v2-0-65e5d1b0855e@gmail.com> In-Reply-To: <20250507-vt8500-timer-updates-v2-0-65e5d1b0855e@gmail.com> To: Krzysztof Kozlowski , Daniel Lezcano , Thomas Gleixner , Rob Herring , Conor Dooley , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746601114; l=3856; i=alchark@gmail.com; s=20250416; h=from:subject:message-id; bh=8ur7PF+h+OoYNnx+CEH0MbXd0jVGhfPuCWw2eRDq/R0=; b=lhE5lWPmUzXCbmWvbeOwQgJMVk1YQ1w5MFmgMOhRfho594LWwPSCvWhcrNB/QZCJF9Me0JwNa o7U4TEIhxNqBkkKvgiCqek98wq8QKMYQ0bgDGp4TiocThkarTIKEs7D X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=ltKbQzKLTJPiDgPtcHxdo+dzFthCCMtC3V9qf7+0rkc= Rewrite the textual description for the VIA/WonderMedia timer as YAML schema. The IP can generate up to four interrupts from four respective match registers, so reflect that in the schema. Reviewed-by: Rob Herring (Arm) Signed-off-by: Alexey Charkov --- .../devicetree/bindings/timer/via,vt8500-timer.txt | 15 ------- .../bindings/timer/via,vt8500-timer.yaml | 51 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 3 files changed, 52 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/via,vt8500-timer.txt b= /Documentation/devicetree/bindings/timer/via,vt8500-timer.txt deleted file mode 100644 index 901c73f0d8ef05fb54d517b807d04f80eef2e736..000000000000000000000000000= 0000000000000 --- a/Documentation/devicetree/bindings/timer/via,vt8500-timer.txt +++ /dev/null @@ -1,15 +0,0 @@ -VIA/Wondermedia VT8500 Timer ------------------------------------------------------ - -Required properties: -- compatible : "via,vt8500-timer" -- reg : Should contain 1 register ranges(address and length) -- interrupts : interrupt for the timer - -Example: - - timer@d8130100 { - compatible =3D "via,vt8500-timer"; - reg =3D <0xd8130100 0x28>; - interrupts =3D <36>; - }; diff --git a/Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml = b/Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e748149948f3140d4a158f800b9= 1e70bf9c4f042 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/via,vt8500-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/Wondermedia VT8500 Timer + +description: + This is the timer block that is a standalone part of the system power + management controller on VIA/WonderMedia SoCs (VIA VT8500 and alike). + The hardware has a single 32-bit counter running at 3 MHz and four match + registers, each of which is associated with a dedicated match interrupt, + and the first of which can also serve as the system watchdog (if the + watchdog function is enabled, it will reset the system upon match instead + of triggering its respective interrupt) + +maintainers: + - Alexey Charkov + +properties: + compatible: + const: via,vt8500-timer + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + items: + - description: Channel 0 match. Note that if the watchdog function + is enabled, this interrupt will not fire and the system will + reboot instead once the counter reaches match register 0 value + - description: Channel 1 match + - description: Channel 2 match + - description: Channel 3 match + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@d8130100 { + compatible =3D "via,vt8500-timer"; + reg =3D <0xd8130100 0x28>; + interrupts =3D <36>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 16037aaa770fc35efb45fc26555afaa5102e2640..5c38a60eb3bddc47106509d6cc6= 450ae93e50191 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3467,6 +3467,7 @@ F: Documentation/devicetree/bindings/hwinfo/via,vt850= 0-scc-id.yaml F: Documentation/devicetree/bindings/i2c/i2c-wmt.txt F: Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.= yaml F: Documentation/devicetree/bindings/pwm/via,vt8500-pwm.yaml +F: Documentation/devicetree/bindings/timer/via,vt8500-timer.yaml F: arch/arm/boot/dts/vt8500/ F: arch/arm/mach-vt8500/ F: drivers/clocksource/timer-vt8500.c --=20 2.49.0 From nobody Tue Dec 16 07:25:24 2025 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 418511DF980; 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Tue, 06 May 2025 23:58:52 -0700 (PDT) Received: from NB-GIGA003.letovo.school ([5.194.95.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30aae525db4sm1315529a91.22.2025.05.06.23.58.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 May 2025 23:58:51 -0700 (PDT) From: Alexey Charkov Date: Wed, 07 May 2025 10:58:31 +0400 Subject: [PATCH v2 2/4] clocksource/drivers/timer-vt8500: Add defines for magic constants Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250507-vt8500-timer-updates-v2-2-65e5d1b0855e@gmail.com> References: <20250507-vt8500-timer-updates-v2-0-65e5d1b0855e@gmail.com> In-Reply-To: <20250507-vt8500-timer-updates-v2-0-65e5d1b0855e@gmail.com> To: Krzysztof Kozlowski , Daniel Lezcano , Thomas Gleixner , Rob Herring , Conor Dooley , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746601114; l=4723; i=alchark@gmail.com; s=20250416; h=from:subject:message-id; bh=4CyYsnhnKma2xppJbhsHsOk6fmvNYSaorpOr7AaIMyg=; b=2hmYsIIl3JTTzoNlkemuEqYWoJwtX02w1BOyvcRaRz0UXM/UX9q+mlX+UPe6goxwY67GNIrnI C5lJS7thZ5yCGiPc1qogRSL1ukycQShkcrEdQjnvsiEyLYVQV/ILE0y X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=ltKbQzKLTJPiDgPtcHxdo+dzFthCCMtC3V9qf7+0rkc= Add defines for all known registers and their bits to make the code more self-explanatory. While at that, replace _VAL suffixes with more intuitive _REG suffixes on register offsets. No functional changes. Signed-off-by: Alexey Charkov --- drivers/clocksource/timer-vt8500.c | 65 ++++++++++++++++++++++++----------= ---- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/drivers/clocksource/timer-vt8500.c b/drivers/clocksource/timer= -vt8500.c index a469b1b5f97233202bf01298b9f612e07026c20c..9f28f30dcaf83ab4e9c89952175= b0d4c75bd6b40 100644 --- a/drivers/clocksource/timer-vt8500.c +++ b/drivers/clocksource/timer-vt8500.c @@ -24,15 +24,31 @@ =20 #define VT8500_TIMER_OFFSET 0x0100 #define VT8500_TIMER_HZ 3000000 -#define TIMER_MATCH_VAL 0x0000 -#define TIMER_COUNT_VAL 0x0010 -#define TIMER_STATUS_VAL 0x0014 -#define TIMER_IER_VAL 0x001c /* interrupt enable */ -#define TIMER_CTRL_VAL 0x0020 -#define TIMER_AS_VAL 0x0024 /* access status */ -#define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */ -#define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */ -#define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */ + +#define TIMER_MATCH_REG(x) (4 * (x)) +#define TIMER_COUNT_REG 0x0010 /* clocksource counter */ + +#define TIMER_STATUS_REG 0x0014 +#define TIMER_STATUS_MATCH(x) BIT((x)) +#define TIMER_STATUS_CLEARALL (TIMER_STATUS_MATCH(0) | \ + TIMER_STATUS_MATCH(1) | \ + TIMER_STATUS_MATCH(2) | \ + TIMER_STATUS_MATCH(3)) + +#define TIMER_WATCHDOG_EN_REG 0x0018 +#define TIMER_WD_EN BIT(0) + +#define TIMER_INT_EN_REG 0x001c /* interrupt enable */ +#define TIMER_INT_EN_MATCH(x) BIT((x)) + +#define TIMER_CTRL_REG 0x0020 +#define TIMER_CTRL_ENABLE BIT(0) /* enable clocksource counter */ +#define TIMER_CTRL_RD_REQ BIT(1) /* request counter read */ + +#define TIMER_ACC_STS_REG 0x0024 /* access status */ +#define TIMER_ACC_WR_MATCH(x) BIT((x)) /* writing Match (x) value */ +#define TIMER_ACC_WR_COUNTER BIT(4) /* writing clocksource counter */ +#define TIMER_ACC_RD_COUNTER BIT(5) /* reading clocksource counter */ =20 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) =20 @@ -43,11 +59,12 @@ static void __iomem *regbase; static u64 vt8500_timer_read(struct clocksource *cs) { int loops =3D msecs_to_loops(10); - writel(3, regbase + TIMER_CTRL_VAL); - while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE) - && --loops) + + writel(TIMER_CTRL_ENABLE | TIMER_CTRL_RD_REQ, regbase + TIMER_CTRL_REG); + while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_RD_COUNTER + && --loops) cpu_relax(); - return readl(regbase + TIMER_COUNT_VAL); + return readl(regbase + TIMER_COUNT_REG); } =20 static struct clocksource clocksource =3D { @@ -63,23 +80,25 @@ static int vt8500_timer_set_next_event(unsigned long cy= cles, { int loops =3D msecs_to_loops(10); u64 alarm =3D clocksource.read(&clocksource) + cycles; - while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE) - && --loops) + + while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_WR_MATCH(0) + && --loops) cpu_relax(); - writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); + writel((unsigned long)alarm, regbase + TIMER_MATCH_REG(0)); =20 if ((signed)(alarm - clocksource.read(&clocksource)) <=3D MIN_OSCR_DELTA) return -ETIME; =20 - writel(1, regbase + TIMER_IER_VAL); + writel(TIMER_INT_EN_MATCH(0), regbase + TIMER_INT_EN_REG); =20 return 0; } =20 static int vt8500_shutdown(struct clock_event_device *evt) { - writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL); - writel(0, regbase + TIMER_IER_VAL); + writel(readl(regbase + TIMER_CTRL_REG) | TIMER_CTRL_ENABLE, + regbase + TIMER_CTRL_REG); + writel(0, regbase + TIMER_INT_EN_REG); return 0; } =20 @@ -95,7 +114,7 @@ static struct clock_event_device clockevent =3D { static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt =3D dev_id; - writel(0xf, regbase + TIMER_STATUS_VAL); + writel(TIMER_STATUS_CLEARALL, regbase + TIMER_STATUS_REG); evt->event_handler(evt); =20 return IRQ_HANDLED; @@ -119,9 +138,9 @@ static int __init vt8500_timer_init(struct device_node = *np) return -EINVAL; } =20 - writel(1, regbase + TIMER_CTRL_VAL); - writel(0xf, regbase + TIMER_STATUS_VAL); - writel(~0, regbase + TIMER_MATCH_VAL); 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Tue, 06 May 2025 23:58:58 -0700 (PDT) Received: from NB-GIGA003.letovo.school ([5.194.95.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30aae525db4sm1315529a91.22.2025.05.06.23.58.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 May 2025 23:58:57 -0700 (PDT) From: Alexey Charkov Date: Wed, 07 May 2025 10:58:32 +0400 Subject: [PATCH v2 3/4] clocksource/drivers/timer-vt8500: Add watchdog functionality Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250507-vt8500-timer-updates-v2-3-65e5d1b0855e@gmail.com> References: <20250507-vt8500-timer-updates-v2-0-65e5d1b0855e@gmail.com> In-Reply-To: <20250507-vt8500-timer-updates-v2-0-65e5d1b0855e@gmail.com> To: Krzysztof Kozlowski , Daniel Lezcano , Thomas Gleixner , Rob Herring , Conor Dooley , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746601114; l=5490; i=alchark@gmail.com; s=20250416; h=from:subject:message-id; bh=M8A28/FCgOo+Deh18WtLaw69mM3yhAAB9vBej8CvPmM=; b=DTwPvujc+dzWl1IVbzguAeSoM1aBFWO/ppre0b9GS9cnvyG6K+kcbZYTdwUB/upwnCr7nKc0/ oFc/Z7V/5n6DkVxk9TTqEF8yGx30u2xWnIfr5K4U5/7iwkB1NgkRYiQ X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=ltKbQzKLTJPiDgPtcHxdo+dzFthCCMtC3V9qf7+0rkc= VIA/WonderMedia system timer IP can generate a watchdog reset when its clocksource counter matches the value in the match register 0 and watchdog function is enabled. For this to work, obvously the clock event device must use a different match register (1~3) and respective interrupt. Check if at least two interrupts are provided by the device tree, then use match register 1 for system clock events and match register 0 for watchdog respectively. Signed-off-by: Alexey Charkov --- drivers/clocksource/Kconfig | 11 +++++++ drivers/clocksource/timer-vt8500.c | 61 ++++++++++++++++++++++++++++++++++= ---- 2 files changed, 67 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 487c8525996724fbf9c6e9726dabb478d86513b9..8f5e41ff23386d9ecb46b38603d= ae485db71cfc7 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -181,6 +181,17 @@ config VT8500_TIMER help Enables support for the VT8500 driver. =20 +config VT8500_TIMER_WATCHDOG + bool "Enable VT8500 watchdog functionality" + depends on VT8500_TIMER + depends on WATCHDOG && WATCHDOG_CORE=3Dy + help + VIA/WonderMedia SoCs can use their system timer as a hardware + watchdog, as long as the first timer channel is free from other + uses and respective function is enabled in its registers. To + make use of it, say Y here and ensure that the device tree + lists at least two interrupts for the VT8500 timer device + config NPCM7XX_TIMER bool "NPCM7xx timer driver" if COMPILE_TEST depends on HAS_IOMEM diff --git a/drivers/clocksource/timer-vt8500.c b/drivers/clocksource/timer= -vt8500.c index 9f28f30dcaf83ab4e9c89952175b0d4c75bd6b40..4128c4f19adc2e02b6df2d0aa2d= ca4659f62fba7 100644 --- a/drivers/clocksource/timer-vt8500.c +++ b/drivers/clocksource/timer-vt8500.c @@ -22,6 +22,8 @@ #include #include =20 +#include + #define VT8500_TIMER_OFFSET 0x0100 #define VT8500_TIMER_HZ 3000000 =20 @@ -55,6 +57,9 @@ #define MIN_OSCR_DELTA 16 =20 static void __iomem *regbase; +static unsigned int sys_timer_ch; /* which match register to use + * for the system timer + */ =20 static u64 vt8500_timer_read(struct clocksource *cs) { @@ -81,15 +86,15 @@ static int vt8500_timer_set_next_event(unsigned long cy= cles, int loops =3D msecs_to_loops(10); u64 alarm =3D clocksource.read(&clocksource) + cycles; =20 - while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_WR_MATCH(0) + while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_WR_MATCH(sys_timer_= ch) && --loops) cpu_relax(); - writel((unsigned long)alarm, regbase + TIMER_MATCH_REG(0)); + writel((unsigned long)alarm, regbase + TIMER_MATCH_REG(sys_timer_ch)); =20 if ((signed)(alarm - clocksource.read(&clocksource)) <=3D MIN_OSCR_DELTA) return -ETIME; =20 - writel(TIMER_INT_EN_MATCH(0), regbase + TIMER_INT_EN_REG); + writel(TIMER_INT_EN_MATCH(sys_timer_ch), regbase + TIMER_INT_EN_REG); =20 return 0; } @@ -120,6 +125,40 @@ static irqreturn_t vt8500_timer_interrupt(int irq, voi= d *dev_id) return IRQ_HANDLED; } =20 +static int vt8500_watchdog_start(struct watchdog_device *wdd) +{ + u64 cycles =3D wdd->timeout * VT8500_TIMER_HZ; + u64 deadline =3D clocksource.read(&clocksource) + cycles; + + writel((u32)deadline, regbase + TIMER_MATCH_REG(0)); + writel(TIMER_WD_EN, regbase + TIMER_WATCHDOG_EN_REG); + return 0; +} + +static int vt8500_watchdog_stop(struct watchdog_device *wdd) +{ + writel(0, regbase + TIMER_WATCHDOG_EN_REG); + return 0; +} + +static const struct watchdog_ops vt8500_watchdog_ops =3D { + .start =3D vt8500_watchdog_start, + .stop =3D vt8500_watchdog_stop, +}; + +static const struct watchdog_info vt8500_watchdog_info =3D { + .identity =3D "VIA VT8500 watchdog", + .options =3D WDIOF_MAGICCLOSE | + WDIOF_KEEPALIVEPING | + WDIOF_SETTIMEOUT, +}; + +static struct watchdog_device vt8500_watchdog_device =3D { + .ops =3D &vt8500_watchdog_ops, + .info =3D &vt8500_watchdog_info, + .max_hw_heartbeat_ms =3D -1UL / (VT8500_TIMER_HZ / 1000), +}; + static int __init vt8500_timer_init(struct device_node *np) { int timer_irq, ret; @@ -131,7 +170,9 @@ static int __init vt8500_timer_init(struct device_node = *np) return -ENXIO; } =20 - timer_irq =3D irq_of_parse_and_map(np, 0); + sys_timer_ch =3D of_irq_count(np) > 1 ? 1 : 0; + + timer_irq =3D irq_of_parse_and_map(np, sys_timer_ch); if (!timer_irq) { pr_err("%s: Missing irq description in Device Tree\n", __func__); @@ -140,7 +181,7 @@ static int __init vt8500_timer_init(struct device_node = *np) =20 writel(TIMER_CTRL_ENABLE, regbase + TIMER_CTRL_REG); writel(TIMER_STATUS_CLEARALL, regbase + TIMER_STATUS_REG); - writel(~0, regbase + TIMER_MATCH_REG(0)); + writel(~0, regbase + TIMER_MATCH_REG(sys_timer_ch)); =20 ret =3D clocksource_register_hz(&clocksource, VT8500_TIMER_HZ); if (ret) { @@ -163,6 +204,16 @@ static int __init vt8500_timer_init(struct device_node= *np) clockevents_config_and_register(&clockevent, VT8500_TIMER_HZ, MIN_OSCR_DELTA * 2, 0xf0000000); =20 + if (!IS_ENABLED(CONFIG_VT8500_TIMER_WATCHDOG)) + return 0; + + if (!sys_timer_ch) { + pr_info("%s: Not enabling watchdog: only one irq was given\n", + __func__); + } else { + watchdog_register_device(&vt8500_watchdog_device); + } + return 0; } =20 --=20 2.49.0 From nobody Tue Dec 16 07:25:24 2025 Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6DF9213E9E; Wed, 7 May 2025 06:59:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 06 May 2025 23:59:03 -0700 (PDT) Received: from NB-GIGA003.letovo.school ([5.194.95.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30aae525db4sm1315529a91.22.2025.05.06.23.58.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 May 2025 23:59:03 -0700 (PDT) From: Alexey Charkov Date: Wed, 07 May 2025 10:58:33 +0400 Subject: [PATCH v2 4/4] ARM: dts: vt8500: list all four timer interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250507-vt8500-timer-updates-v2-4-65e5d1b0855e@gmail.com> References: <20250507-vt8500-timer-updates-v2-0-65e5d1b0855e@gmail.com> In-Reply-To: <20250507-vt8500-timer-updates-v2-0-65e5d1b0855e@gmail.com> To: Krzysztof Kozlowski , Daniel Lezcano , Thomas Gleixner , Rob Herring , Conor Dooley , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746601114; l=3301; i=alchark@gmail.com; s=20250416; h=from:subject:message-id; bh=np1yhCpp/qpjWGPuT2g9hwqJ7HuHqaWY+xGRBXC7yJw=; b=FFRTMlEYxUjfk04F5tcy6Fu8t48a/oBMv1JKyKZORF6YvISOkxhzZ46nWOvKjhQlm3S+G5IK4 3dTVT2mgNcyDZhB9T7QOJuQOdzVCuj62wFbHfp0HeZC4noLZjEbkFui X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=ltKbQzKLTJPiDgPtcHxdo+dzFthCCMtC3V9qf7+0rkc= VIA/WonderMedia SoC timer can generate up to four interrupts corresponding to four timer match registers (firing when the 32-bit freerunning clock source counter matches either of the match registers, respectively). List all four interrupts in device trees. This also enables the system event timer to use a match register other than 0, which can then in turn be used as a system watchdog (watchdog function is not available on other channels) Signed-off-by: Alexey Charkov --- arch/arm/boot/dts/vt8500/vt8500.dtsi | 2 +- arch/arm/boot/dts/vt8500/wm8505.dtsi | 2 +- arch/arm/boot/dts/vt8500/wm8650.dtsi | 2 +- arch/arm/boot/dts/vt8500/wm8750.dtsi | 2 +- arch/arm/boot/dts/vt8500/wm8850.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/vt8500/vt8500.dtsi b/arch/arm/boot/dts/vt850= 0/vt8500.dtsi index 2ba021585d4889f29777a12473964c29f999f3a0..d1dd37220d41becece5d24fbb19= aa71b01723e35 100644 --- a/arch/arm/boot/dts/vt8500/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500/vt8500.dtsi @@ -111,7 +111,7 @@ clkuart3: uart3 { timer@d8130100 { compatible =3D "via,vt8500-timer"; reg =3D <0xd8130100 0x28>; - interrupts =3D <36>; + interrupts =3D <36>, <37>, <38>, <39>; }; =20 usb@d8007900 { diff --git a/arch/arm/boot/dts/vt8500/wm8505.dtsi b/arch/arm/boot/dts/vt850= 0/wm8505.dtsi index 99c064c916b2279797f71261ca9306e9dcd4bbd8..2b1819f0c5412648a83cd3eeb49= 5f68d2e4100ef 100644 --- a/arch/arm/boot/dts/vt8500/wm8505.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8505.dtsi @@ -209,7 +209,7 @@ clksdhc: sdhc { timer@d8130100 { compatible =3D "via,vt8500-timer"; reg =3D <0xd8130100 0x28>; - interrupts =3D <36>; + interrupts =3D <36>, <37>, <38>, <39>; }; =20 usb@d8007100 { diff --git a/arch/arm/boot/dts/vt8500/wm8650.dtsi b/arch/arm/boot/dts/vt850= 0/wm8650.dtsi index 0d6c7bd87f7dcce0eef056d04c38ab1de5d52639..042eec78c085d19fc97d7f0f972= 1399c0716ff74 100644 --- a/arch/arm/boot/dts/vt8500/wm8650.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8650.dtsi @@ -181,7 +181,7 @@ clksdhc: sdhc { timer@d8130100 { compatible =3D "via,vt8500-timer"; reg =3D <0xd8130100 0x28>; - interrupts =3D <36>; + interrupts =3D <36>, <37>, <38>, <39>; }; =20 usb@d8007900 { diff --git a/arch/arm/boot/dts/vt8500/wm8750.dtsi b/arch/arm/boot/dts/vt850= 0/wm8750.dtsi index 0158c0ba5dd110957eac38775d3bf3ebd2ab4154..56342aa1d993a43e7ee766f9315= 1c6d456496262 100644 --- a/arch/arm/boot/dts/vt8500/wm8750.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8750.dtsi @@ -253,7 +253,7 @@ pwm: pwm@d8220000 { timer@d8130100 { compatible =3D "via,vt8500-timer"; reg =3D <0xd8130100 0x28>; - interrupts =3D <36>; + interrupts =3D <36>, <37>, <38>, <39>; }; =20 usb@d8007900 { diff --git a/arch/arm/boot/dts/vt8500/wm8850.dtsi b/arch/arm/boot/dts/vt850= 0/wm8850.dtsi index c4bfb4d30aad0358b39cbf30edf0c63e32167bbd..03e72f28d31b1cfdcfa71ede93b= 8943971bae4e3 100644 --- a/arch/arm/boot/dts/vt8500/wm8850.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8850.dtsi @@ -240,7 +240,7 @@ pwm: pwm@d8220000 { timer@d8130100 { compatible =3D "via,vt8500-timer"; reg =3D <0xd8130100 0x28>; - interrupts =3D <36>; + interrupts =3D <36>, <37>, <38>, <39>; }; =20 usb@d8007900 { --=20 2.49.0