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Tue, 06 May 2025 13:07:00 -0700 (PDT) From: Alexey Charkov Date: Wed, 07 May 2025 00:06:13 +0400 Subject: [PATCH 2/3] clocksource/drivers/timer-vt8500: Add watchdog functionality Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250507-vt8500-timer-updates-v1-2-6b76f7f340a6@gmail.com> References: <20250507-vt8500-timer-updates-v1-0-6b76f7f340a6@gmail.com> In-Reply-To: <20250507-vt8500-timer-updates-v1-0-6b76f7f340a6@gmail.com> To: Krzysztof Kozlowski , Daniel Lezcano , Thomas Gleixner , Rob Herring , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746562005; l=5194; i=alchark@gmail.com; s=20250416; h=from:subject:message-id; bh=rs25g11CJBXBRYyaXrvG97XFkeNvmD+nVlB+j3jsEDY=; b=oDKDtMHT3iU0PdwOZVXCTa/pmq+GInkIZmIaCIFJ6y84zT/N+41IEs31oxfVlhRznAxwXT2o5 zpe4U9hDZ0LAi3tK+tw8nvKR/WP7BkBy5fhiRer08v0t8jU0VBOK/5K X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=ltKbQzKLTJPiDgPtcHxdo+dzFthCCMtC3V9qf7+0rkc= VIA/WonderMedia system timer IP can generate a watchdog reset when its clocksource counter matches the value in the match register 0 and watchdog function is enabled. For this to work, obvously the clock event device must use a different match register (1~3) and respective interrupt. Check if at least two interrupts are provided by the device tree, then use match register 1 for system clock events and match register 0 for watchdog respectively. Signed-off-by: Alexey Charkov --- drivers/clocksource/Kconfig | 6 +++- drivers/clocksource/timer-vt8500.c | 58 ++++++++++++++++++++++++++++++++++= ---- 2 files changed, 58 insertions(+), 6 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 487c8525996724fbf9c6e9726dabb478d86513b9..e4f9aade058af1adc279274c6c7= 11658f9f4cd0a 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -177,9 +177,13 @@ config TEGRA186_TIMER =20 config VT8500_TIMER bool "VT8500 timer driver" if COMPILE_TEST + depends on ARCH_VT8500 || COMPILE_TEST depends on HAS_IOMEM + select WATCHDOG + select WATCHDOG_CORE help - Enables support for the VT8500 driver. + Enables support for the timer and watchdog found on + VIA/WonderMedia VT8500 and related SoCs. =20 config NPCM7XX_TIMER bool "NPCM7xx timer driver" if COMPILE_TEST diff --git a/drivers/clocksource/timer-vt8500.c b/drivers/clocksource/timer= -vt8500.c index 9f28f30dcaf83ab4e9c89952175b0d4c75bd6b40..4e44133d455e1e9e016ddb6dfdd= ca422295ab15c 100644 --- a/drivers/clocksource/timer-vt8500.c +++ b/drivers/clocksource/timer-vt8500.c @@ -22,6 +22,8 @@ #include #include =20 +#include + #define VT8500_TIMER_OFFSET 0x0100 #define VT8500_TIMER_HZ 3000000 =20 @@ -55,6 +57,9 @@ #define MIN_OSCR_DELTA 16 =20 static void __iomem *regbase; +static unsigned int sys_timer_ch; /* which match register to use + * for the system timer + */ =20 static u64 vt8500_timer_read(struct clocksource *cs) { @@ -81,15 +86,15 @@ static int vt8500_timer_set_next_event(unsigned long cy= cles, int loops =3D msecs_to_loops(10); u64 alarm =3D clocksource.read(&clocksource) + cycles; =20 - while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_WR_MATCH(0) + while (readl(regbase + TIMER_ACC_STS_REG) & TIMER_ACC_WR_MATCH(sys_timer_= ch) && --loops) cpu_relax(); - writel((unsigned long)alarm, regbase + TIMER_MATCH_REG(0)); + writel((unsigned long)alarm, regbase + TIMER_MATCH_REG(sys_timer_ch)); =20 if ((signed)(alarm - clocksource.read(&clocksource)) <=3D MIN_OSCR_DELTA) return -ETIME; =20 - writel(TIMER_INT_EN_MATCH(0), regbase + TIMER_INT_EN_REG); + writel(TIMER_INT_EN_MATCH(sys_timer_ch), regbase + TIMER_INT_EN_REG); =20 return 0; } @@ -120,6 +125,40 @@ static irqreturn_t vt8500_timer_interrupt(int irq, voi= d *dev_id) return IRQ_HANDLED; } =20 +static int vt8500_watchdog_start(struct watchdog_device *wdd) +{ + u64 cycles =3D wdd->timeout * VT8500_TIMER_HZ; + u64 deadline =3D clocksource.read(&clocksource) + cycles; + + writel((u32)deadline, regbase + TIMER_MATCH_REG(0)); + writel(TIMER_WD_EN, regbase + TIMER_WATCHDOG_EN_REG); + return 0; +} + +static int vt8500_watchdog_stop(struct watchdog_device *wdd) +{ + writel(0, regbase + TIMER_WATCHDOG_EN_REG); + return 0; +} + +static const struct watchdog_ops vt8500_watchdog_ops =3D { + .start =3D vt8500_watchdog_start, + .stop =3D vt8500_watchdog_stop, +}; + +static const struct watchdog_info vt8500_watchdog_info =3D { + .identity =3D "VIA VT8500 watchdog", + .options =3D WDIOF_MAGICCLOSE | + WDIOF_KEEPALIVEPING | + WDIOF_SETTIMEOUT, +}; + +static struct watchdog_device vt8500_watchdog_device =3D { + .ops =3D &vt8500_watchdog_ops, + .info =3D &vt8500_watchdog_info, + .max_hw_heartbeat_ms =3D -1UL / (VT8500_TIMER_HZ / 1000), +}; + static int __init vt8500_timer_init(struct device_node *np) { int timer_irq, ret; @@ -131,7 +170,9 @@ static int __init vt8500_timer_init(struct device_node = *np) return -ENXIO; } =20 - timer_irq =3D irq_of_parse_and_map(np, 0); + sys_timer_ch =3D of_irq_count(np) > 1 ? 1 : 0; + + timer_irq =3D irq_of_parse_and_map(np, sys_timer_ch); if (!timer_irq) { pr_err("%s: Missing irq description in Device Tree\n", __func__); @@ -140,7 +181,7 @@ static int __init vt8500_timer_init(struct device_node = *np) =20 writel(TIMER_CTRL_ENABLE, regbase + TIMER_CTRL_REG); writel(TIMER_STATUS_CLEARALL, regbase + TIMER_STATUS_REG); - writel(~0, regbase + TIMER_MATCH_REG(0)); + writel(~0, regbase + TIMER_MATCH_REG(sys_timer_ch)); =20 ret =3D clocksource_register_hz(&clocksource, VT8500_TIMER_HZ); if (ret) { @@ -163,6 +204,13 @@ static int __init vt8500_timer_init(struct device_node= *np) clockevents_config_and_register(&clockevent, VT8500_TIMER_HZ, MIN_OSCR_DELTA * 2, 0xf0000000); =20 + if (!sys_timer_ch) { + pr_info("%s: Not enabling watchdog: only one irq was given\n", + __func__); + } else { + watchdog_register_device(&vt8500_watchdog_device); + } + return 0; } =20 --=20 2.49.0