From nobody Thu Dec 18 03:21:13 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FBD228A731; Wed, 7 May 2025 13:08:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746623283; cv=pass; b=j/Z1/iOUZDB9RwKJDjNakyDxn17AxdX5DV2ILS3nyNMFnERAKXoXxy1Iy7zJ8kq1OGKUJSbnSQAQPijKT0G3ZPhRvlVzUjF7Ejo89qsCNryyC0Le7O1E+3B6rA06WCOk5nOXZj49sXdgz0bRgQgSNR8drXYGLUttWcT3V4W6L1Y= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746623283; c=relaxed/simple; bh=suBvb1buuYMhohUMIqerKRu8jOXJRpZNklfTSfXFeV8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FLyzofUmbTB2gBP9xv/hd+VRHU7bgFoPS/4+QHa7MMfdpjoiC65cefanPb3taaQ4xtavyBHKmM68MEElkM4to/m80Q6uRg603AVd+2UO5Jh7hf5u/epIcel5kRwyOT2Ot/n3bL/vHpp8+QSqhSsz/ydp5TjRke3iske9FPHWuE0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=bjM9yUuP; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="bjM9yUuP" ARC-Seal: i=1; a=rsa-sha256; t=1746623260; cv=none; d=zohomail.com; s=zohoarc; b=hYUU4CebSq40Ch8/PqoHaY83sVzrTlYc3+MHTFtKA0dw+9zPFpJXWPgKpqiLBZYR86Tv7DQEQAcNxYWUdn/BVg23ZMxpFoCDN1dbMN1xAN1Y3/uQ2tXwsHA3Qms4wKBobMs9zE8RNDAs7CRsW+7T9OWH8bbWOVg0/A1y363Jios= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746623260; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=MaDkGjhQDSPYsuzM9uRxkmARdK9P5jYEAGbm91UNP7U=; b=U7oIgnC1p6hgnYw0XBS3biqATiK5t2fYlRbnJ05rPQYnarbjg5lEq4s1f2XyamBAbDj9gBwN4VpGGgb0ox6A9AcwFHg0OlRaIyF3gDS38quTLvg1I1JX+tIgeWv6un182gp9aPNQ0UTLnEwEjy9FI8UK439Xz6Zq5na9jrWo84I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1746623260; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=MaDkGjhQDSPYsuzM9uRxkmARdK9P5jYEAGbm91UNP7U=; b=bjM9yUuPJUBMZsYfIIpTfHegVTB/MlDJ9TvPaSes6fGwVa7jGdydKl6l31aoouDC 58AxVBRbF0rX3F6PgLpMbPuOxjxaTg+2fDz6ggpiaP8FVZsZpZ9dK4pTNo6EocuXUl6 uZT2I/d4AreSq3ECgTsXWALjlP+O6z/9JaFPYzPg= Received: by mx.zohomail.com with SMTPS id 1746623258186946.658266425853; Wed, 7 May 2025 06:07:38 -0700 (PDT) From: Nicolas Frattaroli Date: Wed, 07 May 2025 15:07:21 +0200 Subject: [PATCH v3 1/4] phy: rockchip: inno-usb2: add soft vbusvalid control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250507-rk3576-sige5-usb-v3-1-89bf5a614ccf@collabora.com> References: <20250507-rk3576-sige5-usb-v3-0-89bf5a614ccf@collabora.com> In-Reply-To: <20250507-rk3576-sige5-usb-v3-0-89bf5a614ccf@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Frank Wang Cc: Sebastian Reichel , kernel@collabora.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 With USB type C connectors, the vbus detect pin of the OTG controller attached to it is pulled high by a USB Type C controller chip such as the fusb302. This means USB enumeration on Type-C ports never works, as the vbus is always seen as high. Rockchip added some GRF register flags to deal with this situation. The RK3576 TRM calls these "soft_vbusvalid_bvalid" (con0 bit index 15) and "soft_vbusvalid_bvalid_sel" (con0 bit index 14). Downstream introduces a new vendor property which tells the USB 2 PHY that it's connected to a type C port, but we can do better. Since in such an arrangement, we'll have an OF graph connection from the USB controller to the USB connector anyway, we can walk said OF graph and check the connector's compatible to determine this without adding any further vendor properties. Do keep in mind that the usbdp PHY driver seemingly fiddles with these register fields as well, but what it does doesn't appear to be enough for us to get working USB enumeration, presumably because the whole vbus_attach logic needs to be adjusted as well either way. Signed-off-by: Nicolas Frattaroli --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 113 ++++++++++++++++++++++= +++- 1 file changed, 109 insertions(+), 4 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/ro= ckchip/phy-rockchip-inno-usb2.c index b5e6a864deebbcb33375001fc6ed67b2dfee6954..07be9c033c772d4157c7bf438fc= a9b9219a68c9d 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -114,6 +115,8 @@ struct rockchip_chg_det_reg { /** * struct rockchip_usb2phy_port_cfg - usb-phy port configuration. * @phy_sus: phy suspend register. + * @svbus_en: soft vbus bvalid enable register. + * @svbus_sel: soft vbus bvalid selection register. * @bvalid_det_en: vbus valid rise detection enable register. * @bvalid_det_st: vbus valid rise detection status register. * @bvalid_det_clr: vbus valid rise detection clear register. @@ -140,6 +143,8 @@ struct rockchip_chg_det_reg { */ struct rockchip_usb2phy_port_cfg { struct usb2phy_reg phy_sus; + struct usb2phy_reg svbus_en; + struct usb2phy_reg svbus_sel; struct usb2phy_reg bvalid_det_en; struct usb2phy_reg bvalid_det_st; struct usb2phy_reg bvalid_det_clr; @@ -203,6 +208,7 @@ struct rockchip_usb2phy_cfg { * @event_nb: hold event notification callback. * @state: define OTG enumeration states before device reset. * @mode: the dr_mode of the controller. + * @typec_vbus_det: whether to apply Type C logic to OTG vbus detection. */ struct rockchip_usb2phy_port { struct phy *phy; @@ -222,6 +228,7 @@ struct rockchip_usb2phy_port { struct notifier_block event_nb; enum usb_otg_state state; enum usb_dr_mode mode; + bool typec_vbus_det; }; =20 /** @@ -495,6 +502,13 @@ static int rockchip_usb2phy_init(struct phy *phy) mutex_lock(&rport->mutex); =20 if (rport->port_id =3D=3D USB2PHY_PORT_OTG) { + if (rport->typec_vbus_det) { + if (rport->port_cfg->svbus_en.enable && + rport->port_cfg->svbus_sel.enable) { + property_enable(rphy->grf, &rport->port_cfg->svbus_en, true); + property_enable(rphy->grf, &rport->port_cfg->svbus_sel, true); + } + } if (rport->mode !=3D USB_DR_MODE_HOST && rport->mode !=3D USB_DR_MODE_UNKNOWN) { /* clear bvalid status and enable bvalid detect irq */ @@ -535,8 +549,7 @@ static int rockchip_usb2phy_init(struct phy *phy) if (ret) goto out; =20 - schedule_delayed_work(&rport->otg_sm_work, - OTG_SCHEDULE_DELAY * 3); + schedule_delayed_work(&rport->otg_sm_work, 0); } else { /* If OTG works in host only mode, do nothing. */ dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode); @@ -666,8 +679,17 @@ static void rockchip_usb2phy_otg_sm_work(struct work_s= truct *work) unsigned long delay; bool vbus_attach, sch_work, notify_charger; =20 - vbus_attach =3D property_enabled(rphy->grf, - &rport->port_cfg->utmi_bvalid); + if (rport->port_cfg->svbus_en.enable && rport->typec_vbus_det) { + if (property_enabled(rphy->grf, &rport->port_cfg->svbus_en) && + property_enabled(rphy->grf, &rport->port_cfg->svbus_sel)) { + vbus_attach =3D true; + } else { + vbus_attach =3D false; + } + } else { + vbus_attach =3D property_enabled(rphy->grf, + &rport->port_cfg->utmi_bvalid); + } =20 sch_work =3D false; notify_charger =3D false; @@ -1276,6 +1298,83 @@ static int rockchip_otg_event(struct notifier_block = *nb, return NOTIFY_DONE; } =20 +static const char *const rockchip_usb2phy_typec_cons[] =3D { + "usb-c-connector", + NULL, +}; + +static struct device_node *rockchip_usb2phy_to_controller(struct rockchip_= usb2phy *rphy) +{ + struct device_node *np; + struct device_node *parent; + + for_each_node_with_property(np, "phys") { + struct of_phandle_iterator it; + int ret; + + of_for_each_phandle(&it, ret, np, "phys", NULL, 0) { + parent =3D of_get_parent(it.node); + if (it.node !=3D rphy->dev->of_node && rphy->dev->of_node !=3D parent) { + if (parent) + of_node_put(parent); + continue; + } + + /* + * Either the PHY phandle we're iterating or its parent + * matched, we don't care about which out of the two in + * particular as we just need to know it's the right + * USB controller for this PHY. + */ + of_node_put(it.node); + of_node_put(parent); + return np; + } + } + + return NULL; +} + +static bool rockchip_usb2phy_otg_is_type_c(struct rockchip_usb2phy *rphy) +{ + struct device_node *controller =3D rockchip_usb2phy_to_controller(rphy); + struct device_node *ports; + struct device_node *ep =3D NULL; + struct device_node *parent; + + if (!controller) + return false; + + ports =3D of_get_child_by_name(controller, "ports"); + if (ports) { + of_node_put(controller); + controller =3D ports; + } + + for_each_of_graph_port(controller, port) { + ep =3D of_get_child_by_name(port, "endpoint"); + if (!ep) + continue; + + parent =3D of_graph_get_remote_port_parent(ep); + of_node_put(ep); + if (!parent) + continue; + + if (of_device_compatible_match(parent, rockchip_usb2phy_typec_cons)) { + of_node_put(parent); + of_node_put(controller); + return true; + } + + of_node_put(parent); + } + + of_node_put(controller); + + return false; +} + static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, struct rockchip_usb2phy_port *rport, struct device_node *child_np) @@ -1297,6 +1396,8 @@ static int rockchip_usb2phy_otg_port_init(struct rock= chip_usb2phy *rphy, =20 mutex_init(&rport->mutex); =20 + rport->typec_vbus_det =3D rockchip_usb2phy_otg_is_type_c(rphy); + rport->mode =3D of_usb_get_dr_mode_by_phy(child_np, -1); if (rport->mode =3D=3D USB_DR_MODE_HOST || rport->mode =3D=3D USB_DR_MODE_UNKNOWN) { @@ -1971,6 +2072,8 @@ static const struct rockchip_usb2phy_cfg rk3576_phy_c= fgs[] =3D { .port_cfgs =3D { [USB2PHY_PORT_OTG] =3D { .phy_sus =3D { 0x0000, 8, 0, 0, 0x1d1 }, + .svbus_en =3D { 0x0000, 15, 15, 0, 1 }, + .svbus_sel =3D { 0x0000, 14, 14, 0, 1 }, .bvalid_det_en =3D { 0x00c0, 1, 1, 0, 1 }, .bvalid_det_st =3D { 0x00c4, 1, 1, 0, 1 }, .bvalid_det_clr =3D { 0x00c8, 1, 1, 0, 1 }, @@ -2008,6 +2111,8 @@ static const struct rockchip_usb2phy_cfg rk3576_phy_c= fgs[] =3D { .port_cfgs =3D { [USB2PHY_PORT_OTG] =3D { .phy_sus =3D { 0x2000, 8, 0, 0, 0x1d1 }, + .svbus_en =3D { 0x2000, 15, 15, 0, 1 }, + .svbus_sel =3D { 0x2000, 14, 14, 0, 1 }, .bvalid_det_en =3D { 0x20c0, 1, 1, 0, 1 }, .bvalid_det_st =3D { 0x20c4, 1, 1, 0, 1 }, .bvalid_det_clr =3D { 0x20c8, 1, 1, 0, 1 }, --=20 2.49.0 From nobody Thu Dec 18 03:21:13 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 528DD28AAE6; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250507-rk3576-sige5-usb-v3-2-89bf5a614ccf@collabora.com> References: <20250507-rk3576-sige5-usb-v3-0-89bf5a614ccf@collabora.com> In-Reply-To: <20250507-rk3576-sige5-usb-v3-0-89bf5a614ccf@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Frank Wang Cc: Sebastian Reichel , kernel@collabora.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The orientation handling code isn't referenced until very far down the driver code. Move it down some ways so it can later reference other driver functions without needing forward declarations. Signed-off-by: Nicolas Frattaroli --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 100 +++++++++++++++-----------= ---- 1 file changed, 50 insertions(+), 50 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockch= ip/phy-rockchip-usbdp.c index c066cc0a7b4f10fc3cd8779323c369360893520d..fff54900feea601c8fe6bf4c712= 3dfebc5661a15 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -651,56 +651,6 @@ static void rk_udphy_set_typec_default_mapping(struct = rk_udphy *udphy) udphy->mode =3D UDPHY_MODE_DP_USB; } =20 -static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw, - enum typec_orientation orien) -{ - struct rk_udphy *udphy =3D typec_switch_get_drvdata(sw); - - mutex_lock(&udphy->mutex); - - if (orien =3D=3D TYPEC_ORIENTATION_NONE) { - gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); - gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); - /* unattached */ - rk_udphy_usb_bvalid_enable(udphy, false); - goto unlock_ret; - } - - udphy->flip =3D (orien =3D=3D TYPEC_ORIENTATION_REVERSE) ? true : false; - rk_udphy_set_typec_default_mapping(udphy); - rk_udphy_usb_bvalid_enable(udphy, true); - -unlock_ret: - mutex_unlock(&udphy->mutex); - return 0; -} - -static void rk_udphy_orien_switch_unregister(void *data) -{ - struct rk_udphy *udphy =3D data; - - typec_switch_unregister(udphy->sw); -} - -static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy) -{ - struct typec_switch_desc sw_desc =3D { }; - - sw_desc.drvdata =3D udphy; - sw_desc.fwnode =3D dev_fwnode(udphy->dev); - sw_desc.set =3D rk_udphy_orien_sw_set; - - udphy->sw =3D typec_switch_register(udphy->dev, &sw_desc); - if (IS_ERR(udphy->sw)) { - dev_err(udphy->dev, "Error register typec orientation switch: %ld\n", - PTR_ERR(udphy->sw)); - return PTR_ERR(udphy->sw); - } - - return devm_add_action_or_reset(udphy->dev, - rk_udphy_orien_switch_unregister, udphy); -} - static int rk_udphy_refclk_set(struct rk_udphy *udphy) { unsigned long rate; @@ -1451,6 +1401,56 @@ static struct phy *rk_udphy_phy_xlate(struct device = *dev, const struct of_phandl return ERR_PTR(-EINVAL); } =20 +static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw, + enum typec_orientation orien) +{ + struct rk_udphy *udphy =3D typec_switch_get_drvdata(sw); + + mutex_lock(&udphy->mutex); + + if (orien =3D=3D TYPEC_ORIENTATION_NONE) { + gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); + gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); + /* unattached */ + rk_udphy_usb_bvalid_enable(udphy, false); + goto unlock_ret; + } + + udphy->flip =3D (orien =3D=3D TYPEC_ORIENTATION_REVERSE) ? true : false; + rk_udphy_set_typec_default_mapping(udphy); + rk_udphy_usb_bvalid_enable(udphy, true); + +unlock_ret: + mutex_unlock(&udphy->mutex); + return 0; +} + +static void rk_udphy_orien_switch_unregister(void *data) +{ + struct rk_udphy *udphy =3D data; + + typec_switch_unregister(udphy->sw); +} + +static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy) +{ + struct typec_switch_desc sw_desc =3D { }; + + sw_desc.drvdata =3D udphy; + sw_desc.fwnode =3D dev_fwnode(udphy->dev); + sw_desc.set =3D rk_udphy_orien_sw_set; + + udphy->sw =3D typec_switch_register(udphy->dev, &sw_desc); + if (IS_ERR(udphy->sw)) { + dev_err(udphy->dev, "Error register typec orientation switch: %ld\n", + PTR_ERR(udphy->sw)); + return PTR_ERR(udphy->sw); + } + + return devm_add_action_or_reset(udphy->dev, + rk_udphy_orien_switch_unregister, udphy); +} + static int rk_udphy_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; --=20 2.49.0 From nobody Thu Dec 18 03:21:13 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74D3528AB0C; Wed, 7 May 2025 13:08:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250507-rk3576-sige5-usb-v3-3-89bf5a614ccf@collabora.com> References: <20250507-rk3576-sige5-usb-v3-0-89bf5a614ccf@collabora.com> In-Reply-To: <20250507-rk3576-sige5-usb-v3-0-89bf5a614ccf@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Frank Wang Cc: Sebastian Reichel , kernel@collabora.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 Until now, super speed on Type-C only worked in one orientation. This is because on an orientation switch, the UDPHY was never reinitialised. Heiko presented a patch to do this[1], but there were concerns over the correctness of it[2]. Experimentally using Heiko's patch on RK3576 did make me run into issues, though they seemed to be related to the orientation switch actually happening while a clock driving a GRF register was disabled. The key issue is that the hardware wants the USB 3 controller to be held in reset while the PHY is being reconfigured, otherwise we may run into hard-to-catch race conditions. Either way, this patch implements the required ordering in a somewhat unpleasant way: we get the USB 3 controller from the DT, and use runtime power management to forcibly suspend it while the UDPHY is being reconfigured, and then forcibly resume it later. As an added pain in the rear, the suspend/resume of the USB 3 controller also tries fiddling with the USB 3 PHY part of the UDPHY, which means we introduce an atomic flag to skip suspending/resuming the UDPHY if we're resetting the USB 3 controller. We may just need to skip trying to acquire the mutex again, but both ways work for me in practice. This solution may in fact be complete rubbish, but it works to get USB 3 Super Speed working in both cable orientations on my board. Link: https://lore.kernel.org/all/20250226103810.3746018-3-heiko@sntech.de/= [1] Link: https://lore.kernel.org/linux-rockchip/h57ok2hw6os7bcafqkrqknfvm7hnu2= 5m2oe54qmrsuzdwqlos3@m4och2fcdm7s/ [2] Signed-off-by: Nicolas Frattaroli --- drivers/phy/rockchip/phy-rockchip-usbdp.c | 54 +++++++++++++++++++++++++++= ++++ 1 file changed, 54 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockch= ip/phy-rockchip-usbdp.c index fff54900feea601c8fe6bf4c7123dfebc5661a15..5cd6bbc367f69bca15c2a94a07e= 72f850b381ae3 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -200,6 +200,10 @@ struct rk_udphy { /* PHY devices */ struct phy *phy_dp; struct phy *phy_u3; + + /* USB 3 controller device */ + struct device *ctrl_u3; + atomic_t ctrl_resetting; }; =20 static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[= 4][4] =3D { @@ -1255,6 +1259,9 @@ static int rk_udphy_usb3_phy_init(struct phy *phy) struct rk_udphy *udphy =3D phy_get_drvdata(phy); int ret =3D 0; =20 + if (atomic_read(&udphy->ctrl_resetting)) + return 0; + mutex_lock(&udphy->mutex); /* DP only or high-speed, disable U3 port */ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { @@ -1273,6 +1280,9 @@ static int rk_udphy_usb3_phy_exit(struct phy *phy) { struct rk_udphy *udphy =3D phy_get_drvdata(phy); =20 + if (atomic_read(&udphy->ctrl_resetting)) + return 0; + mutex_lock(&udphy->mutex); /* DP only or high-speed */ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) @@ -1401,10 +1411,31 @@ static struct phy *rk_udphy_phy_xlate(struct device= *dev, const struct of_phandl return ERR_PTR(-EINVAL); } =20 +static struct device_node *rk_udphy_to_controller(struct rk_udphy *udphy) +{ + struct device_node *np; + + for_each_node_with_property(np, "phys") { + struct of_phandle_iterator it; + int ret; + + of_for_each_phandle(&it, ret, np, "phys", NULL, 0) { + if (it.node !=3D udphy->dev->of_node) + continue; + + of_node_put(it.node); + return np; + } + } + + return NULL; +} + static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw, enum typec_orientation orien) { struct rk_udphy *udphy =3D typec_switch_get_drvdata(sw); + int ret; =20 mutex_lock(&udphy->mutex); =20 @@ -1420,6 +1451,18 @@ static int rk_udphy_orien_sw_set(struct typec_switch= _dev *sw, rk_udphy_set_typec_default_mapping(udphy); rk_udphy_usb_bvalid_enable(udphy, true); =20 + if (udphy->status !=3D UDPHY_MODE_NONE && udphy->ctrl_u3) { + atomic_set(&udphy->ctrl_resetting, 1); + pm_runtime_force_suspend(udphy->ctrl_u3); + + ret =3D rk_udphy_setup(udphy); + if (!ret) + clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); + + pm_runtime_force_resume(udphy->ctrl_u3); + atomic_set(&udphy->ctrl_resetting, 0); + } + unlock_ret: mutex_unlock(&udphy->mutex); return 0; @@ -1430,12 +1473,22 @@ static void rk_udphy_orien_switch_unregister(void *= data) struct rk_udphy *udphy =3D data; =20 typec_switch_unregister(udphy->sw); + put_device(udphy->ctrl_u3); } =20 static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy) { + struct device_node *ctrl =3D rk_udphy_to_controller(udphy); struct typec_switch_desc sw_desc =3D { }; =20 + if (ctrl) { + udphy->ctrl_u3 =3D bus_find_device_by_of_node(udphy->dev->bus, ctrl); + of_node_put(ctrl); + } + + if (!udphy->ctrl_u3) + dev_info(udphy->dev, "couldn't find this PHY's USB3 controller\n"); + sw_desc.drvdata =3D udphy; sw_desc.fwnode =3D dev_fwnode(udphy->dev); sw_desc.set =3D rk_udphy_orien_sw_set; @@ -1499,6 +1552,7 @@ static int rk_udphy_probe(struct platform_device *pde= v) return ret; =20 mutex_init(&udphy->mutex); + atomic_set(&udphy->ctrl_resetting, 0); platform_set_drvdata(pdev, udphy); =20 if (device_property_present(dev, "orientation-switch")) { --=20 2.49.0 From nobody Thu Dec 18 03:21:13 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02CB6289802; Wed, 7 May 2025 13:08:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746623292; 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spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1746623270; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=n/b63KH5NJPUOPZ1g1cKRKHd1zEwEqpry3HADn6QvTM=; b=UgSIQJXpt40JoQWQx9NJh3nI/TmbfDvztlOBqxNfBs9vkcxjaESiACyVYMYtZFRo BhXMI1s3LDC+ZZX7qsKyOYMy2T62FK+kGmqIrv5LD2a+jG2sImjma9kDVzfqZA7q40I gCvHjWbEbkFHYtzGCfd9YzkZBldYeJbvEXwqSnJ8= Received: by mx.zohomail.com with SMTPS id 1746623268314716.9665012016193; Wed, 7 May 2025 06:07:48 -0700 (PDT) From: Nicolas Frattaroli Date: Wed, 07 May 2025 15:07:24 +0200 Subject: [PATCH v3 4/4] arm64: dts: rockchip: enable USB on Sige5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250507-rk3576-sige5-usb-v3-4-89bf5a614ccf@collabora.com> References: <20250507-rk3576-sige5-usb-v3-0-89bf5a614ccf@collabora.com> In-Reply-To: <20250507-rk3576-sige5-usb-v3-0-89bf5a614ccf@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Frank Wang Cc: Sebastian Reichel , kernel@collabora.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The ArmSoM Sige5 has several USB ports: a Type-A USB 3 port (USB2 lines going through a hub), a Type-A USB 2.0 port (also going through a hub), a Type-C DC input port that has absolutely no USB data connection and a Type-C port with USB3.2 Gen1x1 that's also the maskrom programming port. Enable these ports, and set the device role to be host for the host ports. The data capable Type-C USB port uses a fusb302 for data role switching. Signed-off-by: Nicolas Frattaroli --- .../boot/dts/rockchip/rk3576-armsom-sige5.dts | 160 +++++++++++++++++= ++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/ar= m64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 570252c4c0bfe56a3c269e47d81fca7676e61787..74de0fc77fefeffb8a90dd6dd93= 27ddb0083a146 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -177,6 +177,33 @@ vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { regulator-max-microvolt =3D <3300000>; vin-supply =3D <&vcc_5v0_sys>; }; + + vcc_5v0_typec0: regulator-vcc-5v0-typec0 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_otg0_pwren>; + regulator-name =3D "vcc_5v0_typec0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc_5v0_device>; + }; + vcc_5v0_usbhost: regulator-vcc-5v0-usbhost { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_host_pwren>; + regulator-name =3D "vcc_5v0_usbhost"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc_5v0_device>; + }; +}; + +&combphy1_psu { + status =3D "okay"; }; =20 &combphy0_ps { @@ -611,6 +638,58 @@ regulator-state-mem { &i2c2 { status =3D "okay"; =20 + usbc0: typec-portc@22 { + compatible =3D "fcs,fusb302"; + reg =3D <0x22>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usbc0_interrupt>; + vbus-supply =3D <&vcc_5v0_typec0>; + + connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + data-role =3D "dual"; + /* fusb302 supports PD Rev 2.0 Ver 1.2 */ + pd-revision =3D /bits/ 8 <0x2 0x0 0x1 0x2>; + power-role =3D "source"; + source-pdos =3D ; + + altmodes { + displayport { + svid =3D /bits/ 16 <0xff01>; + vdo =3D <0xffffffff>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + usbc0_hs_ep: endpoint { + remote-endpoint =3D <&usb_drd0_hs_ep>; + }; + }; + port@1 { + reg =3D <1>; + usbc0_ss_ep: endpoint { + remote-endpoint =3D <&usb_drd0_ss_ep>; + }; + }; + port@2 { + reg =3D <2>; + usbc0_dp_ep: endpoint { + remote-endpoint =3D <&usbdp_phy_ep>; + }; + }; + }; + }; + }; + hym8563: rtc@51 { compatible =3D "haoyu,hym8563"; reg =3D <0x51>; @@ -678,6 +757,24 @@ pcie_reset: pcie-reset { rockchip,pins =3D <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins =3D <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + usb_otg0_pwren: usb-otg0-pwren { + rockchip,pins =3D <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + usbc0_interrupt: usbc0-interrupt { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + usbc0_sbu1: usbc0-sbu1 { + rockchip,pins =3D <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + usbc0_sbu2: usbc0-sbu2 { + rockchip,pins =3D <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; }; =20 &sdhci { @@ -706,11 +803,74 @@ &sdmmc { status =3D "okay"; }; =20 +&u2phy0 { + status =3D "okay"; +}; + +&u2phy0_otg { + status =3D "okay"; +}; + +&u2phy1 { + status =3D "okay"; +}; + +&u2phy1_otg { + phy-supply =3D <&vcc_5v0_usbhost>; + status =3D "okay"; +}; + &uart0 { pinctrl-0 =3D <&uart0m0_xfer>; status =3D "okay"; }; =20 +&usb_drd0_dwc3 { + usb-role-switch; + dr_mode =3D "otg"; + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + usb_drd0_hs_ep: endpoint { + remote-endpoint =3D <&usbc0_hs_ep>; + }; + }; + + port@1 { + reg =3D <1>; + usb_drd0_ss_ep: endpoint { + remote-endpoint =3D <&usbc0_ss_ep>; + }; + }; + }; +}; + +&usb_drd1_dwc3 { + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usbdp_phy { + mode-switch; + orientation-switch; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usbc0_sbu1 &usbc0_sbu2>; + sbu1-dc-gpios =3D <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios =3D <&gpio2 RK_PA7 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + port { + usbdp_phy_ep: endpoint { + remote-endpoint =3D <&usbc0_dp_ep>; + }; + }; +}; + &vop { status =3D "okay"; }; --=20 2.49.0