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Redefine the register layout to match its actual definition as provided by OpenRM and expose the fully-constructed "architecture" field through our own "Architecture" type. The "chipset" pseudo-field is also useful to have, so keep providing it. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gpu.rs | 19 ++++++++++++++++--- drivers/gpu/nova-core/regs.rs | 26 ++++++++++++++++++++++++-- 2 files changed, 40 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 43139b527fac35f5f33facbc0be50b9715044245..29db6726a1f5196bd2d17781173= 13c987ccf343b 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -101,9 +101,22 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Resu= lt { /// Enum representation of the GPU generation. #[derive(fmt::Debug)] pub(crate) enum Architecture { - Turing, - Ampere, - Ada, + Turing =3D 0x16, + Ampere =3D 0x17, + Ada =3D 0x19, +} + +impl TryFrom for Architecture { + type Error =3D Error; + + fn try_from(value: u8) -> core::result::Result { + match value { + 0x16 =3D> Ok(Self::Turing), + 0x17 =3D> Ok(Self::Ampere), + 0x19 =3D> Ok(Self::Ada), + _ =3D> Err(ENODEV), + } + } } =20 pub(crate) struct Revision { diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 498fefb52f33bf01518f19d32287962f1fdc3224..bfb9555b203ff880c0fc373bb22= e5ce6048015d4 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -4,15 +4,37 @@ // but are mapped to types. #![allow(non_camel_case_types)] =20 +use kernel::error::Error; + #[macro_use] mod macros; =20 -use crate::gpu::Chipset; +use crate::gpu::{Architecture, Chipset}; =20 /* PMC */ =20 register!(NV_PMC_BOOT_0 @ 0x00000000, "Basic revision information about th= e GPU" { 3:0 minor_revision as u8, "Minor revision of the chip"; 7:4 major_revision as u8, "Major revision of the chip"; - 28:20 chipset as u32 ?=3D> Chipset, "Chipset model"; + 8:8 architecture_1 as u8, "MSB of the architecture"; + 23:20 implementation as u8, "Implementation version of the architect= ure"; + 28:24 architecture_0 as u8, "Lower bits of the architecture"; }); + +impl NV_PMC_BOOT_0 { + /// Combines `architecture_0` and `architecture_1` to obtain the archi= tecture of the chip. + pub(crate) fn architecture(self) -> Result { + Architecture::try_from( + self.architecture_0() | (self.architecture_1() << Self::ARCHIT= ECTURE_0.len()), + ) + } + + /// Combines `architecture` and `implementation` to obtain a code uniq= ue to the chipset. + pub(crate) fn chipset(self) -> Result { + self.architecture() + .map(|arch| { + ((arch as u32) << Self::IMPLEMENTATION.len()) | self.imple= mentation() as u32 + }) + .and_then(Chipset::try_from) + } +} --=20 2.49.0