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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250507-nova-frts-v3-17-fcb02749754d@nvidia.com> References: <20250507-nova-frts-v3-0-fcb02749754d@nvidia.com> In-Reply-To: <20250507-nova-frts-v3-0-fcb02749754d@nvidia.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: John Hubbard , Ben Skeggs , Joel Fernandes , Timur Tabi , Alistair Popple , linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Alexandre Courbot X-Mailer: b4 0.14.2 X-ClientProxiedBy: TYAPR04CA0023.apcprd04.prod.outlook.com (2603:1096:404:15::35) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|SJ0PR12MB8115:EE_ X-MS-Office365-Filtering-Correlation-Id: 99b2ca02-25f4-4492-2617-08dd8d6e95c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|366016|10070799003|921020; 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Do this in a `FbLayout` structure, that will be later extended to describe more memory regions used to boot the GSP. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gpu.rs | 4 ++ drivers/gpu/nova-core/gsp.rs | 3 ++ drivers/gpu/nova-core/gsp/fb.rs | 108 +++++++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 27 ++++++++++ 5 files changed, 143 insertions(+) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 4bf7f72247e5320935a517270b5a0e1ec2becfec..a3d96639706e808305cce664167= 78d2bf6e7e683 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -7,6 +7,7 @@ use crate::driver::Bar0; use crate::falcon::{gsp::Gsp, sec2::Sec2, Falcon}; use crate::firmware::Firmware; +use crate::gsp::fb::FbLayout; use crate::regs; use crate::util; use crate::vbios::Vbios; @@ -239,6 +240,9 @@ pub(crate) fn new( =20 let _sec2_falcon =3D Falcon::::new(pdev.as_ref(), spec.chips= et, bar, true)?; =20 + let fb_layout =3D FbLayout::new(spec.chipset, bar)?; + dev_dbg!(pdev.as_ref(), "{:#x?}\n", fb_layout); + let _bios =3D Vbios::new(pdev, bar)?; =20 Ok(pin_init!(Self { diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs new file mode 100644 index 0000000000000000000000000000000000000000..27616a9d2b7069b18661fc97811= fa1cac285b8f8 --- /dev/null +++ b/drivers/gpu/nova-core/gsp.rs @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0 + +pub(crate) mod fb; diff --git a/drivers/gpu/nova-core/gsp/fb.rs b/drivers/gpu/nova-core/gsp/fb= .rs new file mode 100644 index 0000000000000000000000000000000000000000..f28ded59469d52daf39e5d19c09= efd7bf08fee92 --- /dev/null +++ b/drivers/gpu/nova-core/gsp/fb.rs @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 + +use core::ops::Range; + +use kernel::prelude::*; + +use crate::driver::Bar0; +use crate::gpu::Chipset; +use crate::regs; + +fn align_down(value: u64, align: u64) -> u64 { + value & !(align - 1) +} + +/// Layout of the GPU framebuffer memory. +/// +/// Contains ranges of GPU memory reserved for a given purpose during the = GSP bootup process. +#[derive(Debug)] +#[expect(dead_code)] +pub(crate) struct FbLayout { + pub fb: Range, + + pub vga_workspace: Range, + pub bios: Range, + + pub frts: Range, +} + +impl FbLayout { + pub(crate) fn new(chipset: Chipset, bar: &Bar0) -> Result { + let fb =3D { + let fb_size =3D vidmem_size(bar, chipset); + + 0..fb_size + }; + let fb_len =3D fb.end - fb.start; + + let vga_workspace =3D { + let vga_base =3D vga_workspace_addr(bar, fb_len, chipset); + + vga_base..fb.end + }; + + let bios =3D vga_workspace.clone(); + + let frts =3D { + const FRTS_DOWN_ALIGN: u64 =3D 0x20000; + const FRTS_SIZE: u64 =3D 0x100000; + let frts_base =3D align_down(vga_workspace.start, FRTS_DOWN_AL= IGN) - FRTS_SIZE; + + frts_base..frts_base + FRTS_SIZE + }; + + Ok(Self { + fb, + vga_workspace, + bios, + frts, + }) + } +} + +/// Returns `true` if the display is disabled. +fn display_disabled(bar: &Bar0, chipset: Chipset) -> bool { + if chipset >=3D Chipset::GA100 { + regs::NV_FUSE_STATUS_OPT_DISPLAY_MAXWELL::read(bar).display_disabl= ed() + } else { + regs::NV_FUSE_STATUS_OPT_DISPLAY_AMPERE::read(bar).display_disable= d() + } +} + +/// Returns the video memory size in bytes. +fn vidmem_size(bar: &Bar0, chipset: Chipset) -> u64 { + if chipset >=3D Chipset::GA102 { + (regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_42::read(bar).value() as u= 64) << 20 + } else { + let local_mem_range =3D regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE::r= ead(bar); + let size =3D + (local_mem_range.lower_mag() as u64) << ((local_mem_range.lowe= r_scale() as u64) + 20); + + if local_mem_range.ecc_mode_enabled() { + size / 16 * 15 + } else { + size + } + } +} + +/// Returns the vga workspace address. +fn vga_workspace_addr(bar: &Bar0, fb_size: u64, chipset: Chipset) -> u64 { + let base =3D fb_size - 0x100000; + let vga_workspace_base =3D if display_disabled(bar, chipset) { + regs::NV_PDISP_VGA_WORKSPACE_BASE::read(bar) + } else { + return base; + }; + + if !vga_workspace_base.status_valid() { + return base; + } + + let addr =3D (vga_workspace_base.addr() as u64) << 16; + if addr < base { + fb_size - 0x20000 + } else { + addr + } +} diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index ff6d0b40c18f36af4c7e2d5c839fdf77dba23321..202e978e56f024de3ae8b178e65= b63c2cea244e1 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -8,6 +8,7 @@ mod falcon; mod firmware; mod gpu; +mod gsp; mod regs; mod util; mod vbios; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index b5c6eeb6ed873a06b4aefcb375f4944eb0b20597..15ec9b7e69694ff198b5353d562= fc1aff5eefd3f 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -53,6 +53,12 @@ pub(crate) fn chipset(self) -> Result { 23:0 adr_63_40 as u32; }); =20 +register!(NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE @ 0x00100ce0 { + 3:0 lower_scale as u8; + 9:4 lower_mag as u8; + 30:30 ecc_mode_enabled as bool; +}); + /* PGC6 */ =20 register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128= { @@ -64,6 +70,27 @@ pub(crate) fn chipset(self) -> Result { 31:0 value as u32; }); =20 +register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 @ 0x001183a4 { + 31:0 value as u32; +}); + +/* PDISP */ + +register!(NV_PDISP_VGA_WORKSPACE_BASE @ 0x00625f04 { + 3:3 status_valid as bool; + 31:8 addr as u32; +}); + +/* FUSE */ + +register!(NV_FUSE_STATUS_OPT_DISPLAY_MAXWELL @ 0x00021c04 { + 0:0 display_disabled as bool; +}); + +register!(NV_FUSE_STATUS_OPT_DISPLAY_AMPERE @ 0x00820c04 { + 0:0 display_disabled as bool; +}); + /* PFALCON */ =20 register!(NV_PFALCON_FALCON_IRQSCLR @ +0x00000004 { --=20 2.49.0