From nobody Mon Feb 9 05:22:19 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E319D4B1E5E; Thu, 8 May 2025 03:09:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746673771; cv=none; b=K6FyWZaX7Z+RJqpnr1+ldGaYiOdEyb6t/S8hIGP6C6izYUQQYFd6hRVFJuBW8NFl1zv/XTKMfMEz4R4rXbx6u9jpMArwKorTcVgGm0OoIA3VnfppuiAdHmdZOoPIxeP7eHzAs71xDrXimw6Ldp8dV5ruImVy+j8CwxT6m1SiIQk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746673771; c=relaxed/simple; bh=9VPUkAAqKJdFWpDRqamHtFrmx85GBqkgnKOSnrDI9vA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=oObtfgSJHmAly0o7V/znJpR/e1oZAiykL53sgTFg3cnw9s+sk9JRBdWGIhKUDoYCrVa8WhUy1S1sSQ/OQ1uEvvCqn2R6qL1uM5ialUK3zPIQK+WEZzmwzXg/jJojTB/XA3llAZTu4CfsMgCGEdbaIzw99+/gGsg3u5TVEqdy84M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=EFd6c7Kw; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="EFd6c7Kw" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 54839KTa982443 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 7 May 2025 22:09:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746673760; bh=i8RU0fbhH6U3yXyRxm0j+S6qxPOhhNP5iZUZq5SHWkU=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=EFd6c7Kw8CRgFAsa70xcFmpdhdP7ddY9ZNBmSSVTKdb/U395KNpqvgG+QUY3aCYd+ EMKgzYazfEv4Zq/u6a8jR5fc0qBLN2MkXFCGVgD1nicNv9dJwsPi2kBUABF07Qb9/q ms1xj4hwzWEV9JODyrYinI0pnRogL3TxYd1e/ivg= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 54839K8I008939 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 7 May 2025 22:09:20 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 7 May 2025 22:09:19 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 7 May 2025 22:09:19 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 54839JRi020147; Wed, 7 May 2025 22:09:19 -0500 From: Bryan Brattlof Date: Wed, 7 May 2025 22:09:19 -0500 Subject: [PATCH v5 1/3] dt-bindings: arm: ti: Add binding for AM62L SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250507-am62lx-v5-1-4b57ea878e62@ti.com> References: <20250507-am62lx-v5-0-4b57ea878e62@ti.com> In-Reply-To: <20250507-am62lx-v5-0-4b57ea878e62@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Add the binding for TI's AM62L family of devices. Signed-off-by: Bryan Brattlof Acked-by: Krzysztof Kozlowski --- Changes in v1: - separated out devicetree bindings --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index bf6003d8fb764..6f448433d3b2e 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -31,6 +31,12 @@ properties: - const: phytec,am62a-phycore-som - const: ti,am62a7 =20 + - description: K3 AM62L3 SoC and Boards + items: + - enum: + - ti,am62l3-evm + - const: ti,am62l3 + - description: K3 AM62P5 SoC and Boards items: - enum: --=20 2.49.0 From nobody Mon Feb 9 05:22:19 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 730AD1E32BE; Thu, 8 May 2025 03:09:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746673774; cv=none; b=UJs/ePg/4IGWAGhgDGPnLRQVQanwSvZzzQNX3lPrsk1iLLJEqjy1tH8JeOGj2k5TjqQ/Cn71Of+xq8W2Ykwy67joqeYFkgG46+nrun+1niElAam+x07/c8E4xvo+PdX/EL4wUgTv6Il3KDChIBd3uuWioFlbxAcVcQ3c+O+HdV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746673774; c=relaxed/simple; bh=ob2IMiP3W01pT5EoUPoYAwR7d1e4kq2jw0tfE0PMbyY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=KptKYpJxd5SkaTGRZ2XNoTZFALcmUDf98rbqviUHmYDITW7eVfvWH98Sv3RZmHr1omAFseyED0lBE5NtfkYlfmF75zx3ssHxkyXZenFn7tbi/Hipjk+7DaVAEoshTUN2r1FY9xOC5BhVlEsS6LtaSgxSHY0RqynB+tEnL1hxZCs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=hJoQS4vt; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hJoQS4vt" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 54839K661716640 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 7 May 2025 22:09:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746673760; bh=+MyIwbO3e8lDIdK2uX/3mIDIc4SuviZCq/V/ADu+kEs=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=hJoQS4vtqX+yrg6JcfMPXz8M1FKgltCG913dpJqwgbWsc6QOu3pGzmXmzmX4KykEO 566a0FkU0MTGD6y46thhFngz5F3SjWA76eZgz+mQ8TX+dgTCsSCFSy3lh/XPk7hnua iS6qFZGzOW3sjbjHvHYm9kq62+xjJPLcMdOOF38s= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 54839KkU102459 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 7 May 2025 22:09:20 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 7 May 2025 22:09:19 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 7 May 2025 22:09:19 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 54839J92066230; Wed, 7 May 2025 22:09:19 -0500 From: Bryan Brattlof Date: Wed, 7 May 2025 22:09:20 -0500 Subject: [PATCH v5 2/3] arm64: dts: ti: k3-am62l: add initial infrastructure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250507-am62lx-v5-2-4b57ea878e62@ti.com> References: <20250507-am62lx-v5-0-4b57ea878e62@ti.com> In-Reply-To: <20250507-am62lx-v5-0-4b57ea878e62@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea From: Vignesh Raghavendra Add the initial infrastructure needed for the AM62L. ALl of which can be found in the Technical Reference Manual (TRM) located here: https://www.ti.com/lit/pdf/sprujb4 Signed-off-by: Vignesh Raghavendra Signed-off-by: Bryan Brattlof --- Changes in v4: - Corrected Copyright year - Used 'ranges' property in the fss{} node Changes in v3: - Added more nodes now that the SCMI interface is ready Changes in v1: - switched to non-direct links to TRM updates are automatic - fixed white space indent issues with a few nodes - separated out device tree bindings --- arch/arm64/boot/dts/ti/Makefile | 3 + arch/arm64/boot/dts/ti/k3-am62l-main.dtsi | 673 +++++++++++++++++++++++= ++++ arch/arm64/boot/dts/ti/k3-am62l-thermal.dtsi | 25 + arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 133 ++++++ arch/arm64/boot/dts/ti/k3-am62l.dtsi | 121 +++++ arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 67 +++ arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 + 7 files changed, 1024 insertions(+) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 3c3aa09a94b64..6c0e27c1042f9 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -33,6 +33,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am62-pocketbeagle2.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-phyboard-lyra-rdk.dtb =20 +# Boards with AM62Lx SoCs +dtb-$(CONFIG_ARCH_K3) +=3D k3-am62l3-evm.dtb + # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-verdin-nonwifi-dahlia.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62l-main.dtsi new file mode 100644 index 0000000000000..f6fbaaede8c36 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi @@ -0,0 +1,673 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L main domain peripherals + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01840000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <3>; + interrupt-controller; + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts =3D ; + + gic_its: msi-controller@1820000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its =3D <0x1000000 0x400000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + gpio0: gpio@600000 { + compatible =3D "ti,am64-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + power-domains =3D <&scmi_pds 34>; + clocks =3D <&scmi_clk 140>; + clock-names =3D "gpio"; + ti,ngpio =3D <126>; + ti,davinci-gpio-unbanked =3D <0>; + status =3D "disabled"; + }; + + gpio2: gpio@610000 { + compatible =3D "ti,am64-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + power-domains =3D <&scmi_pds 35>; + clocks =3D <&scmi_clk 141>; + clock-names =3D "gpio"; + ti,ngpio =3D <79>; + ti,davinci-gpio-unbanked =3D <0>; + status =3D "disabled"; + }; + + timer0: timer@2400000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2400000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 47>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 15>; + ti,timer-pwm; + }; + + timer1: timer@2410000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2410000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 61>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 16>; + ti,timer-pwm; + }; + + timer2: timer@2420000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2420000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 66>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 17>; + ti,timer-pwm; + }; + + timer3: timer@2430000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2430000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 80>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 18>; + ti,timer-pwm; + }; + + uart0: serial@2800000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02800000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 89>; + clocks =3D <&scmi_clk 358>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart1: serial@2810000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02810000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 77>; + clocks =3D <&scmi_clk 312>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart2: serial@2820000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02820000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 78>; + clocks =3D <&scmi_clk 314>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart3: serial@2830000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02830000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 79>; + clocks =3D <&scmi_clk 316>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart4: serial@2840000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02840000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 80>; + clocks =3D <&scmi_clk 318>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart5: serial@2850000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02850000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 81>; + clocks =3D <&scmi_clk 320>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart6: serial@2860000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02860000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 82>; + clocks =3D <&scmi_clk 322>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + conf: syscon@9000000 { + compatible =3D "syscon", "simple-mfd"; + ranges =3D <0x0 0x00 0x09000000 0x400000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + phy_gmii_sel: phy@1be000 { + compatible =3D "ti,am654-phy-gmii-sel"; + reg =3D <0x1be000 0x8>; + #phy-cells =3D <1>; + }; + + epwm_tbclk: clock-controller@1e9100 { + compatible =3D "ti,am62-epwm-tbclk"; + reg =3D <0x1e9100 0x4>; + #clock-cells =3D <1>; + }; + }; + + rti0: watchdog@e000000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x0e000000 0x00 0x100>; + clocks =3D <&scmi_clk 273>; + power-domains =3D <&scmi_pds 60>; + assigned-clocks =3D <&scmi_clk 273>; + assigned-clock-parents =3D <&scmi_clk 1>; + }; + + rti1: watchdog@e010000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x0e010000 0x00 0x100>; + clocks =3D <&scmi_clk 279>; + power-domains =3D <&scmi_pds 61>; + assigned-clocks =3D <&scmi_clk 279>; + assigned-clock-parents =3D <&scmi_clk 1>; + }; + + fss: bus@fc00000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x0fc00000 0x00 0x100>, // FSS Control + <0x00 0x0fc40000 0x00 0x100>, // OSPI0 Control + <0x05 0x00000000 0x01 0x00000000>; // OSPI0 Memory + + ospi0: spi@fc40000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts =3D ; + clocks =3D <&scmi_clk 134>; + assigned-clocks =3D <&scmi_clk 134>; + assigned-clock-rates =3D <166666666>; + power-domains =3D <&scmi_pds 32>; + #size-cells =3D <0>; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + cdns,phase-detect-selector =3D <2>; + status =3D "disabled"; + }; + }; + + usbss0: dwc3-usb@f900000 { + compatible =3D "ti,am62-usb"; + reg =3D <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; + clocks =3D <&scmi_clk 329>; + clock-names =3D "ref"; + power-domains =3D <&scmi_pds 95>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + ti,syscon-phy-pll-refclk =3D <&wkup_conf 0x45000>; + status =3D "disabled"; + + usb0: usb@31000000 { + compatible =3D "snps,dwc3"; + reg =3D <0x00 0x31000000 0x00 0x50000>; + interrupts =3D , /* irq.0 */ + ; /* irq.0 */ + interrupt-names =3D "host", "peripheral"; + maximum-speed =3D "high-speed"; + dr_mode =3D "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + bootph-all; + }; + }; + + usbss1: dwc3-usb@f910000 { + compatible =3D "ti,am62-usb"; + reg =3D <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks =3D <&scmi_clk 336>; + clock-names =3D "ref"; + power-domains =3D <&scmi_pds 96>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ti,syscon-phy-pll-refclk =3D <&wkup_conf 0x45004>; + ranges; + status =3D "disabled"; + + usb1: usb@31100000 { + compatible =3D "snps,dwc3"; + reg =3D <0x00 0x31100000 0x00 0x50000>; + interrupts =3D , /* irq.0 */ + ; /* irq.0 */ + interrupt-names =3D "host", "peripheral"; + maximum-speed =3D "high-speed"; + dr_mode =3D "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + + sdhci0: mmc@fa10000 { + compatible =3D "ti,am62-sdhci"; + reg =3D <0x00 0xfa10000 0x00 0x1000>, + <0x00 0xfa18000 0x00 0x400>; + interrupts =3D ; + power-domains =3D <&scmi_pds 28>; + clocks =3D <&scmi_clk 122>, <&scmi_clk 123>; + clock-names =3D "clk_ahb", "clk_xin"; + assigned-clocks =3D <&scmi_clk 123>; + assigned-clock-parents =3D <&scmi_clk 0>; + bus-width =3D <8>; + ti,clkbuf-sel =3D <0x7>; + ti,otap-del-sel-legacy =3D <0x0>; + ti,itap-del-sel-legacy =3D <0x0>; + status =3D "disabled"; + }; + + sdhci1: mmc@fa00000 { + compatible =3D "ti,am62-sdhci"; + reg =3D <0x00 0x0fa00000 0x00 0x1000>, + <0x00 0x0fa08000 0x00 0x400>; + interrupts =3D ; + power-domains =3D <&scmi_pds 26>; + clocks =3D <&scmi_clk 106>, <&scmi_clk 107>; + clock-names =3D "clk_ahb", "clk_xin"; + assigned-clocks =3D <&scmi_clk 107>; + assigned-clock-parents =3D <&scmi_clk 0>; + bus-width =3D <4>; + ti,clkbuf-sel =3D <0x7>; + ti,otap-del-sel-legacy =3D <0x0>; + ti,itap-del-sel-legacy =3D <0x0>; + status =3D "disabled"; + }; + + sdhci2: mmc@fa20000 { + compatible =3D "ti,am62-sdhci"; + reg =3D <0x00 0x0fa20000 0x00 0x1000>, + <0x00 0x0fa28000 0x00 0x400>; + interrupts =3D ; + power-domains =3D <&scmi_pds 27>; + clocks =3D <&scmi_clk 114>, <&scmi_clk 115>; + clock-names =3D "clk_ahb", "clk_xin"; + assigned-clocks =3D <&scmi_clk 115>; + assigned-clock-parents =3D <&scmi_clk 0>; + bus-width =3D <4>; + ti,clkbuf-sel =3D <0x7>; + ti,otap-del-sel-legacy =3D <0x0>; + ti,itap-del-sel-legacy =3D <0x0>; + status =3D "disabled"; + }; + + i2c0: i2c@20000000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20000000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 53>; + clocks =3D <&scmi_clk 246>; + clock-names =3D "fck"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@20010000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20010000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 54>; + clocks =3D <&scmi_clk 250>; + clock-names =3D "fck"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@20020000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20020000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 55>; + clocks =3D <&scmi_clk 254>; + clock-names =3D "fck"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@20030000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20030000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 56>; + clocks =3D <&scmi_clk 258>; + clock-names =3D "fck"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + mcan0: can@20701000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&scmi_pds 47>; + clocks =3D <&scmi_clk 179>, <&scmi_clk 174>; + clock-names =3D "hclk", "cclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + status =3D "disabled"; + }; + + mcan1: can@20711000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x20711000 0x00 0x200>, + <0x00 0x20718000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&scmi_pds 48>; + clocks =3D <&scmi_clk 185>, <&scmi_clk 180>; + clock-names =3D "hclk", "cclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + status =3D "disabled"; + }; + + mcan2: can@20721000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x20721000 0x00 0x200>, + <0x00 0x20728000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&scmi_pds 49>; + clocks =3D <&scmi_clk 191>, <&scmi_clk 186>; + clock-names =3D "hclk", "cclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + status =3D "disabled"; + }; + + spi0: spi@20100000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x20100000 0x00 0x400>; + interrupts =3D ; + power-domains =3D <&scmi_pds 72>; + clocks =3D <&scmi_clk 299>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@20110000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x20110000 0x00 0x400>; + interrupts =3D ; + power-domains =3D <&scmi_pds 73>; + clocks =3D <&scmi_clk 302>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi2: spi@20120000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x20120000 0x00 0x400>; + interrupts =3D ; + power-domains =3D <&scmi_pds 74>; + clocks =3D <&scmi_clk 305>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@20130000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x20130000 0x00 0x400>; + interrupts =3D ; + power-domains =3D <&scmi_pds 75>; + clocks =3D <&scmi_clk 308>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + epwm0: pwm@23000000 { + compatible =3D "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x23000000 0x00 0x100>; + power-domains =3D <&scmi_pds 40>; + clocks =3D <&epwm_tbclk 0>, <&scmi_clk 164>; + clock-names =3D "tbclk", "fck"; + status =3D "disabled"; + }; + + epwm1: pwm@23010000 { + compatible =3D "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x23010000 0x00 0x100>; + power-domains =3D <&scmi_pds 41>; + clocks =3D <&epwm_tbclk 1>, <&scmi_clk 165>; + clock-names =3D "tbclk", "fck"; + status =3D "disabled"; + }; + + epwm2: pwm@23020000 { + compatible =3D "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x23020000 0x00 0x100>; + power-domains =3D <&scmi_pds 42>; + clocks =3D <&epwm_tbclk 2>, <&scmi_clk 166>; + clock-names =3D "tbclk", "fck"; + status =3D "disabled"; + }; + + ecap0: pwm@23100000 { + compatible =3D "ti,am3352-ecap"; + reg =3D <0x00 0x23100000 0x00 0x100>; + power-domains =3D <&scmi_pds 22>; + clocks =3D <&scmi_clk 99>; + clock-names =3D "fck"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + ecap1: pwm@23110000 { + compatible =3D "ti,am3352-ecap"; + reg =3D <0x00 0x23110000 0x00 0x100>; + power-domains =3D <&scmi_pds 23>; + clocks =3D <&scmi_clk 100>; + clock-names =3D "fck"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + ecap2: pwm@23120000 { + compatible =3D "ti,am3352-ecap"; + reg =3D <0x00 0x23120000 0x00 0x100>; + power-domains =3D <&scmi_pds 24>; + clocks =3D <&scmi_clk 101>; + clock-names =3D "fck"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + eqep0: counter@23200000 { + compatible =3D "ti,am62-eqep"; + reg =3D <0x00 0x23200000 0x00 0x100>; + power-domains =3D <&scmi_pds 29>; + clocks =3D <&scmi_clk 127>; + interrupts =3D ; + status =3D "disabled"; + }; + + eqep1: counter@23210000 { + compatible =3D "ti,am62-eqep"; + reg =3D <0x00 0x23210000 0x00 0x100>; + power-domains =3D <&scmi_pds 30>; + clocks =3D <&scmi_clk 128>; + interrupts =3D ; + status =3D "disabled"; + }; + + eqep2: counter@23220000 { + compatible =3D "ti,am62-eqep"; + reg =3D <0x00 0x23220000 0x00 0x100>; + power-domains =3D <&scmi_pds 31>; + clocks =3D <&scmi_clk 129>; + interrupts =3D ; + status =3D "disabled"; + }; + + elm0: ecc@25010000 { + compatible =3D "ti,am64-elm"; + reg =3D <0x00 0x25010000 0x00 0x2000>; + interrupts =3D ; + power-domains =3D <&scmi_pds 25>; + clocks =3D <&scmi_clk 102>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + + tscadc0: tscadc@28001000 { + compatible =3D "ti,am654-tscadc", "ti,am3359-tscadc"; + reg =3D <0x00 0x28001000 0x00 0x1000>; + interrupts =3D ; + power-domains =3D <&scmi_pds 0>; + clocks =3D <&scmi_clk 0>; + assigned-clocks =3D <&scmi_clk 0>; + assigned-clock-parents =3D <&scmi_clk 2>; + assigned-clock-rates =3D <60000000>; + clock-names =3D "fck"; + status =3D "disabled"; + + adc { + compatible =3D "ti,am654-adc", "ti,am3359-adc"; + #io-channel-cells =3D <1>; + }; + }; + + dphy_tx0: phy@301c0000 { + compatible =3D "ti,j721e-dphy"; + reg =3D <0x0 0x301c0000 0x0 0x1000>; + clocks =3D <&scmi_clk 348>, <&scmi_clk 341>; + clock-names =3D "psm", "pll_ref"; + power-domains =3D <&scmi_pds 86>; + assigned-clocks =3D <&scmi_clk 341>; + assigned-clock-parents =3D <&scmi_clk 0>; + assigned-clock-rates =3D <25000000>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + dsi0: dsi@30500000 { + compatible =3D "ti,j721e-dsi"; + reg =3D <0x0 0x30500000 0x0 0x100000>, + <0x0 0x30270000 0x0 0x100>; + clocks =3D <&scmi_clk 155>, <&scmi_clk 158>; + clock-names =3D "dsi_p_clk", "dsi_sys_clk"; + power-domains =3D <&scmi_pds 38>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + phys =3D <&dphy_tx0>; + phy-names =3D "dphy"; + status =3D "disabled"; + }; + + gpmc0: memory-controller@3b000000 { + compatible =3D "ti,am64-gpmc"; + reg =3D <0x00 0x3b000000 0x00 0x400>, + <0x00 0x50000000 0x00 0x8000000>; + power-domains =3D <&scmi_pds 37>; + clocks =3D <&scmi_clk 147>; + clock-names =3D "fck"; + reg-names =3D "cfg", "data"; + interrupts =3D ; + gpmc,num-cs =3D <3>; + gpmc,num-waitpins =3D <2>; + interrupt-controller; + gpio-controller; + #interrupt-cells =3D <2>; + #address-cells =3D <2>; + #size-cells =3D <1>; + #gpio-cells =3D <2>; + status =3D "disabled"; + }; + + oc_sram: sram@70800000 { + compatible =3D "mmio-sram"; + reg =3D <0x00 0x70800000 0x00 0x10000>; + ranges =3D <0x0 0x00 0x70800000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + scmi_shmem: sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x100>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62l-thermal.dtsi b/arch/arm64/boot= /dts/ti/k3-am62l-thermal.dtsi new file mode 100644 index 0000000000000..55a83eaa88c94 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l-thermal.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Thermal limits for the AM62L + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive =3D <250>; /* milliSeconds */ + polling-delay =3D <500>; /* milliSeconds */ + thermal-sensors =3D <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature =3D <105000>; /* milliCelsius */ + hysteresis =3D <2000>; /* milliCelsius */ + type =3D "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62l-wakeup.dtsi new file mode 100644 index 0000000000000..1e4ca8ec7babe --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L wakeup domain peripherals + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +#include + +&cbass_wakeup { + wkup_vtm0: temperature-sensor@b00000 { + compatible =3D "ti,j7200-vtm"; + reg =3D <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains =3D <&scmi_pds 46>; + #thermal-sensor-cells =3D <1>; + }; + + pmx0: pinctrl@4084000 { + compatible =3D "pinctrl-single"; + reg =3D <0x00 0x4084000 0x00 0x8000>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0xffffffff>; + #pinctrl-cells =3D <1>; + bootph-all; + }; + + wkup_gpio0: gpio@4201000 { + compatible =3D "ti,am64-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x04201000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + power-domains =3D <&scmi_pds 36>; + clocks =3D <&scmi_clk 142>; + clock-names =3D "gpio"; + ti,ngpio =3D <7>; + ti,davinci-gpio-unbanked =3D <0>; + status =3D "disabled"; + }; + + wkup_timer0: timer@2b100000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2b100000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 85>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 19>; + ti,timer-pwm; + }; + + wkup_timer1: timer@2b110000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2b110000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 96>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 20>; + ti,timer-pwm; + }; + + wkup_i2c0: i2c@2b200000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x2b200000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&scmi_pds 57>; + clocks =3D <&scmi_clk 262>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + + target-module@2b300050 { + compatible =3D "ti,sysc-omap2", "ti,sysc"; + reg =3D <0x00 0x2b300050 0x00 0x4>, + <0x00 0x2b300054 0x00 0x4>, + <0x00 0x2b300058 0x00 0x4>; + reg-names =3D "rev", "sysc", "syss"; + ranges =3D <0x0 0x00 0x2b300000 0x100000>; + power-domains =3D <&scmi_pds 83>; + clocks =3D <&scmi_clk 324>; + clock-names =3D "fck"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ti,sysc-mask =3D <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle =3D , + , + , + ; + ti,syss-mask =3D <1>; + ti,no-reset-on-init; + status =3D "disabled"; + + wkup_uart0: serial@0 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x0 0x100>; + interrupts =3D ; + clocks =3D <&scmi_clk 324>; + assigned-clocks =3D <&scmi_clk 324>; + assigned-clock-rates =3D <48000000>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + }; + + wkup_conf: syscon@43000000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x00 0x43000000 0x00 0x20000>; + ranges =3D <0x0 0x00 0x43000000 0x20000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + chipid: chipid@14 { + compatible =3D "ti,am654-chipid"; + reg =3D <0x14 0x4>; + bootph-all; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62l.dtsi b/arch/arm64/boot/dts/ti/= k3-am62l.dtsi new file mode 100644 index 0000000000000..19e73a2267503 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree Source for AM62L SoC Family + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +#include +#include +#include + +#include "k3-pinctrl.h" + +/ { + model =3D "Texas Instruments K3 AM62L3 SoC"; + compatible =3D "ti,am62l3"; + interrupt-parent =3D <&gic500>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + psci: psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + scmi: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82004000>; + shmem =3D <&scmi_shmem>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + bootph-all; + }; + + scmi_pds: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + bootph-all; + }; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + cbass_main: bus@f0000 { + compatible =3D "simple-bus"; + ranges =3D <0x00 0x00600000 0x00 0x00600000 0x00 0x00010100>, /* GPIO */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First Peripheral= Window */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000400>, /* Timesync Router = */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x1a001400>, /* Second Periphera= l Window */ + <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x0000b000>, /* DSS */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00390000>, /* DSI Wrapper */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core W= indow */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core W= indow */ + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0 */ + <0x00 0x45810000 0x00 0x45810000 0x00 0x03170000>, /* DMSS */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS DAT1 */ + <0x00 0x70800000 0x00 0x70800000 0x00 0x00018000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x04 0x00000000 0x04 0x00000000 0x01 0x00000000>, /* FSS DAT0 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS DAT3 */ + + /* Wakeup Domain Range */ + <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDGCFG */ + <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ + <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Periphera= l Window */ + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ + #address-cells =3D <2>; + #size-cells =3D <2>; + + cbass_wakeup: bus@43000000 { + compatible =3D "simple-bus"; + ranges =3D <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDGCFG */ + <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ + <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Periphe= ral Window */ + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ + #address-cells =3D <2>; + #size-cells =3D <2>; + bootph-all; + }; + }; + + #include "k3-am62l-thermal.dtsi" +}; + +/* Now include peripherals for each bus segment */ +#include "k3-am62l-main.dtsi" +#include "k3-am62l-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi b/arch/arm64/boot/dts/ti= /k3-am62l3.dtsi new file mode 100644 index 0000000000000..da220b8515122 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L3 SoC family (Dual Core A53) + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +/dts-v1/; + +#include "k3-am62l.dtsi" + +/ { + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-unified; + cache-level =3D <2>; + cache-size =3D <0x40000>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index cac7cccc11121..0121413399d63 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -66,6 +66,8 @@ #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 +#define AM62LX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) + #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode= )) #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxm= ode)) =20 --=20 2.49.0 From nobody Mon Feb 9 05:22:19 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3515E1E25FA; Thu, 8 May 2025 03:09:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 7 May 2025 22:09:20 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 7 May 2025 22:09:19 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 7 May 2025 22:09:19 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 54839JI1020150; Wed, 7 May 2025 22:09:19 -0500 From: Bryan Brattlof Date: Wed, 7 May 2025 22:09:21 -0500 Subject: [PATCH v5 3/3] arm64: dts: ti: k3-am62l: add initial reference board file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250507-am62lx-v5-3-4b57ea878e62@ti.com> References: <20250507-am62lx-v5-0-4b57ea878e62@ti.com> In-Reply-To: <20250507-am62lx-v5-0-4b57ea878e62@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea From: Vignesh Raghavendra Add the initial board file for the AM62L3's Evaluation Module. Signed-off-by: Vignesh Raghavendra Signed-off-by: Bryan Brattlof --- Changes from v1: - switched to non-direct links so TRM updates are automatic - removed current-speed property from main_uart0 - removed empty reserved-memory{} node - removed serial2 from aliases{} node - corrected main_uart0 pinmux Changes from v2: - alphabetized phandles - corrected macros and node names for main_uart0 pinmux node Changes from v3: - added and enabled more nodes that have been validated - added link to data sheet which is now public Changes in v4: - Corrected Copyright year --- arch/arm64/boot/dts/ti/k3-am62l3-evm.dts | 294 +++++++++++++++++++++++++++= ++++ 1 file changed, 294 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62l3-evm.dts new file mode 100644 index 0000000000000..16efb60bf3260 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L3 Evaluation Module + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + * Data Sheet: https://www.ti.com/lit/pdf/sprspa1 + */ + +/dts-v1/; + +#include +#include +#include + +#include "k3-am62l3.dtsi" +#include "k3-pinctrl.h" + +/ { + compatible =3D "ti,am62l3-evm", "ti,am62l3"; + model =3D "Texas Instruments AM62L3 Evaluation Module"; + + chosen { + stdout-path =3D &uart0; + }; + + gpio_keys: gpio-keys { + compatible =3D "gpio-keys"; + autorepeat; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usr_btn_pins_default>; + + usr: button-usr { + label =3D "User Key"; + linux,code =3D ; + gpios =3D <&gpio0 90 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usr_led_pins_default>; + + led-0 { + label =3D "am62-sk:green:heartbeat"; + gpios =3D <&gpio0 123 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + function =3D LED_FUNCTION_HEARTBEAT; + default-state =3D "on"; + }; + }; + + memory@80000000 { + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type =3D "memory"; + bootph-all; + }; + + vcc_1v8: regulator-3 { + /* output of TPS6282518DMQ */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_3v3_sys>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-1 { + /* output of LM61460-Q1 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + bootph-all; + compatible =3D "regulator-fixed"; + regulator-name =3D "vmain_pd"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + bootph-all; + + eeprom@51 { + /* AT24C512C-MAHM-T or M24512-DFMC6TG */ + compatible =3D "atmel,24c512"; + reg =3D <0x51>; + }; +}; + +&i2c1 { + pinctrl-0 =3D <&i2c1_pins_default>; + pinctrl-names =3D "default"; + clock-frequency =3D <100000>; + status =3D "okay"; + bootph-all; + + exp1: gpio@22 { + compatible =3D "ti,tca6424"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "", "", + "UART1_FET_SEL", "MMC1_SD_EN", + "VPP_EN", "EXP_PS_3V3_EN", + "UART1_FET_BUF_EN", "", + "DSI_GPIO0", "DSI_GPIO1", + "", "BT_UART_WAKE_SOC_3V3", + "USB_TYPEA_OC_INDICATION", "", + "", "WLAN_ALERTn", + "HDMI_INTn", "TEST_GPIO2", + "MCASP0_FET_EN", "MCASP0_BUF_BT_EN", + "MCASP0_FET_SEL", "DSI_EDID", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + + interrupt-parent =3D <&gpio0>; + interrupts =3D <91 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells =3D <2>; + + pinctrl-0 =3D <&gpio0_ioexp_intr_pins_default>; + pinctrl-names =3D "default"; + bootph-all; + }; + + exp2: gpio@23 { + compatible =3D "ti,tca6424"; + reg =3D <0x23>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "BT_EN_SOC", "VOUT0_FET_SEL0", + "", "", + "", "", + "", "", + "WL_LT_EN", "EXP_PS_5V0_EN", + "TP45", "TP48", + "TP46", "TP49", + "TP47", "TP50", + "GPIO_QSPI_NAND_RSTn", "GPIO_HDMI_RSTn", + "GPIO_CPSW1_RST", "GPIO_CPSW2_RST", + "", "GPIO_AUD_RSTn", + "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST"; + + bootph-all; + }; +}; + +&pmx0 { + gpio0_ioexp_intr_pins_default: gpio0-ioexp-intr-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x01b0, PIN_INPUT, 7) /* (B12) SPI0_D1.GPIO0_91 */ + >; + bootph-all; + }; + + i2c0_pins_default: i2c0-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x01cc, PIN_INPUT_PULLUP, 0) /* (B7) I2C0_SCL */ + AM62LX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 0) /* (A7) I2C0_SDA */ + >; + bootph-all; + }; + + i2c1_pins_default: i2c1-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 0) /* (D7) I2C1_SCL */ + AM62LX_IOPAD(0x01d8, PIN_INPUT_PULLUP, 0) /* (A6) I2C1_SDA */ + >; + }; + + mmc0_pins_default: mmc0-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (D2) MMC0_CMD */ + AM62LX_IOPAD(0x020c, PIN_OUTPUT, 0) /* (B2) MMC0_CLK */ + AM62LX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (D3) MMC0_DAT0 */ + AM62LX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (D4) MMC0_DAT1 */ + AM62LX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (C1) MMC0_DAT2 */ + AM62LX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (C2) MMC0_DAT3 */ + AM62LX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (C4) MMC0_DAT4 */ + AM62LX_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (B3) MMC0_DAT5 */ + AM62LX_IOPAD(0x01f0, PIN_INPUT_PULLUP, 0) /* (A3) MMC0_DAT6 */ + AM62LX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B4) MMC0_DAT7 */ + >; + bootph-all; + }; + + mmc1_pins_default: mmc1-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */ + AM62LX_IOPAD(0x0228, PIN_OUTPUT, 0) /* (Y2) MMC1_CLK */ + AM62LX_IOPAD(0x0224, PIN_INPUT, 0) /* (AA1) MMC1_DAT0 */ + AM62LX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y4) MMC1_DAT1 */ + AM62LX_IOPAD(0x021c, PIN_INPUT_PULLUP, 0) /* (AA2) MMC1_DAT2 */ + AM62LX_IOPAD(0x0218, PIN_INPUT_PULLUP, 0) /* (AB2) MMC1_DAT3 */ + AM62LX_IOPAD(0x0234, PIN_INPUT, 0) /* (B6) MMC1_SDCD */ + >; + bootph-all; + }; + + uart0_pins_default: uart0-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D13) UART0_RXD */ + AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ + >; + bootph-all; + }; + + uart1_pins_default: uart1-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x0180, PIN_INPUT, 2) /* (A8) MCASP0_AXR3.UART1_CTSn */ + AM62LX_IOPAD(0x0184, PIN_OUTPUT, 2) /* (B10) MCASP0_AXR2.UART1_RTSn */ + AM62LX_IOPAD(0x0198, PIN_INPUT, 2) /* (C11) MCASP0_AFSR.UART1_RXD */ + AM62LX_IOPAD(0x019c, PIN_OUTPUT, 2) /* (A12) MCASP0_ACLKR.UART1_TXD */ + >; + bootph-all; + }; + + usb1_default_pins: usb1-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x0248, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP,= 0) /* (A5) USB1_DRVVBUS */ + >; + }; + + usr_btn_pins_default: usr-btn-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x01ac, PIN_INPUT, 7) /* (E12) SPI0_D0.GPIO0_90 */ + >; + }; + + usr_led_pins_default: usr-led-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x0238, PIN_OUTPUT, 7) /* (D24) MMC1_SDWP.GPIO0_123 */ + >; + }; +}; + +&sdhci0 { + /* eMMC */ + pinctrl-0 =3D <&mmc0_pins_default>; + pinctrl-names =3D "default"; + non-removable; + status =3D "okay"; + bootph-all; +}; + +&sdhci1 { + /* SD/MMC */ + pinctrl-0 =3D <&mmc1_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + bootph-all; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + bootph-all; +}; + +&uart1 { + pinctrl-0 =3D <&uart1_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + bootph-all; +}; + +&usb1 { + pinctrl-0 =3D <&usb1_default_pins>; + pinctrl-names =3D "default"; + dr_mode =3D "host"; +}; + +&usbss1 { + ti,vbus-divider; + status =3D "okay"; +}; --=20 2.49.0