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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4f88aa588basm2419559173.79.2025.05.06.14.06.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 May 2025 14:06:48 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org Cc: heylenay@4d2.org, inochiama@outlook.com, guodong@riscstar.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/6] reset: spacemit: add support for SpacemiT CCU resets Date: Tue, 6 May 2025 16:06:35 -0500 Message-ID: <20250506210638.2800228-5-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250506210638.2800228-1-elder@riscstar.com> References: <20250506210638.2800228-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement reset support for SpacemiT CCUs. The code is structured to handle SpacemiT resets generically, while defining the set of specific reset controllers and their resets in an SoC-specific source file. A SpacemiT reset controller device is an auxiliary device associated with a clock controller (CCU). This initial patch defines the reset controllers for the MPMU, APBC, and MPMU CCUs, which already defined clock controllers. Signed-off-by: Alex Elder --- drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/spacemit/Kconfig | 12 +++ drivers/reset/spacemit/Makefile | 7 ++ drivers/reset/spacemit/core.c | 61 +++++++++++ drivers/reset/spacemit/core.h | 39 +++++++ drivers/reset/spacemit/k1.c | 177 ++++++++++++++++++++++++++++++++ 7 files changed, 298 insertions(+) create mode 100644 drivers/reset/spacemit/Kconfig create mode 100644 drivers/reset/spacemit/Makefile create mode 100644 drivers/reset/spacemit/core.c create mode 100644 drivers/reset/spacemit/core.h create mode 100644 drivers/reset/spacemit/k1.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 99f6f9784e686..b1f1af50ca10b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -354,6 +354,7 @@ source "drivers/reset/amlogic/Kconfig" source "drivers/reset/starfive/Kconfig" source "drivers/reset/sti/Kconfig" source "drivers/reset/hisilicon/Kconfig" +source "drivers/reset/spacemit/Kconfig" source "drivers/reset/tegra/Kconfig" =20 endif diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 31f9904d13f9c..6c19fd875ff13 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -2,6 +2,7 @@ obj-y +=3D core.o obj-y +=3D amlogic/ obj-y +=3D hisilicon/ +obj-y +=3D spacemit/ obj-y +=3D starfive/ obj-y +=3D sti/ obj-y +=3D tegra/ diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig new file mode 100644 index 0000000000000..4ff3487a99eff --- /dev/null +++ b/drivers/reset/spacemit/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config RESET_SPACEMIT + bool + +config RESET_SPACEMIT_K1 + tristate "SpacemiT K1 reset driver" + depends on ARCH_SPACEMIT || COMPILE_TEST + select RESET_SPACEMIT + default ARCH_SPACEMIT + help + This enables the reset controller driver for the SpacemiT K1 SoC. diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makef= ile new file mode 100644 index 0000000000000..3a064e9d5d6b4 --- /dev/null +++ b/drivers/reset/spacemit/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_RESET_SPACEMIT) +=3D reset_spacemit.o + +reset_spacemit-y :=3D core.o + +reset_spacemit-$(CONFIG_RESET_SPACEMIT_K1) +=3D k1.o diff --git a/drivers/reset/spacemit/core.c b/drivers/reset/spacemit/core.c new file mode 100644 index 0000000000000..5cd981eb3f097 --- /dev/null +++ b/drivers/reset/spacemit/core.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* SpacemiT reset driver core */ + +#include +#include +#include +#include + +#include "core.h" + +static int spacemit_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct ccu_reset_controller *controller; + const struct ccu_reset_data *data; + u32 mask; + u32 val; + + controller =3D container_of(rcdev, struct ccu_reset_controller, rcdev); + data =3D &controller->data->reset_data[id]; + mask =3D data->assert_mask | data->deassert_mask; + val =3D assert ? data->assert_mask : data->deassert_mask; + + return regmap_update_bits(controller->regmap, data->offset, mask, val); +} + +static int spacemit_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, true); +} + +static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, false); +} + +static const struct reset_control_ops spacemit_reset_control_ops =3D { + .assert =3D spacemit_reset_assert, + .deassert =3D spacemit_reset_deassert, +}; + +/** + * spacemit_reset_controller_register() - register a reset controller + * @dev: Device that's registering the controller + * @controller: SpacemiT CCU reset controller structure + */ +int spacemit_reset_controller_register(struct device *dev, + struct ccu_reset_controller *controller) +{ + struct reset_controller_dev *rcdev =3D &controller->rcdev; + + rcdev->ops =3D &spacemit_reset_control_ops; + rcdev->owner =3D THIS_MODULE; + rcdev->of_node =3D dev->of_node; + rcdev->nr_resets =3D controller->data->count; + + return devm_reset_controller_register(dev, &controller->rcdev); +} diff --git a/drivers/reset/spacemit/core.h b/drivers/reset/spacemit/core.h new file mode 100644 index 0000000000000..a71f835ccb779 --- /dev/null +++ b/drivers/reset/spacemit/core.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* SpacemiT reset driver core */ + +#ifndef __RESET_SPACEMIT_CORE_H__ +#define __RESET_SPACEMIT_CORE_H__ + +#include +#include +#include + +struct ccu_reset_data { + u32 offset; + u32 assert_mask; + u32 deassert_mask; +}; + +#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ + { \ + .offset =3D (_offset), \ + .assert_mask =3D (_assert_mask), \ + .deassert_mask =3D (_deassert_mask), \ + } + +struct ccu_reset_controller_data { + const struct ccu_reset_data *reset_data; /* array */ + size_t count; +}; + +struct ccu_reset_controller { + struct reset_controller_dev rcdev; + const struct ccu_reset_controller_data *data; + struct regmap *regmap; +}; + +extern int spacemit_reset_controller_register(struct device *dev, + struct ccu_reset_controller *controller); + +#endif /* __RESET_SPACEMIT_CORE_H__ */ diff --git a/drivers/reset/spacemit/k1.c b/drivers/reset/spacemit/k1.c new file mode 100644 index 0000000000000..19a34f151b214 --- /dev/null +++ b/drivers/reset/spacemit/k1.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* SpacemiT reset driver data for the K1 SoC */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "core.h" + +static const struct ccu_reset_data mpmu_resets[] =3D { + [RESET_WDT] =3D RESET_DATA(MPMU_WDTPCR, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data k1_mpmu_reset_data =3D { + .reset_data =3D mpmu_resets, + .count =3D ARRAY_SIZE(mpmu_resets), +}; + +static const struct ccu_reset_data apbc_resets[] =3D { + [RESET_UART0] =3D RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0), + [RESET_UART2] =3D RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), + [RESET_GPIO] =3D RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), + [RESET_PWM0] =3D RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM1] =3D RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM2] =3D RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM3] =3D RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM4] =3D RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM5] =3D RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM6] =3D RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM7] =3D RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM8] =3D RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM9] =3D RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM10] =3D RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM11] =3D RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM12] =3D RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM13] =3D RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM14] =3D RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM15] =3D RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM16] =3D RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM17] =3D RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM18] =3D RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM19] =3D RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)), + [RESET_SSP3] =3D RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), + [RESET_UART3] =3D RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), + [RESET_RTC] =3D RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), + [RESET_TWSI0] =3D RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), + [RESET_TIMERS1] =3D RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), + [RESET_AIB] =3D RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), + [RESET_TIMERS2] =3D RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), + [RESET_ONEWIRE] =3D RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), + [RESET_SSPA0] =3D RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), + [RESET_SSPA1] =3D RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), + [RESET_DRO] =3D RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), + [RESET_IR] =3D RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0), + [RESET_TWSI1] =3D RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), + [RESET_TSEN] =3D RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), + [RESET_TWSI2] =3D RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), + [RESET_TWSI4] =3D RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), + [RESET_TWSI5] =3D RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), + [RESET_TWSI6] =3D RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), + [RESET_TWSI7] =3D RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0), + [RESET_TWSI8] =3D RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), + [RESET_IPC_AP2AUD] =3D RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), + [RESET_UART4] =3D RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), + [RESET_UART5] =3D RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), + [RESET_UART6] =3D RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), + [RESET_UART7] =3D RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), + [RESET_UART8] =3D RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), + [RESET_UART9] =3D RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), + [RESET_CAN0] =3D RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data k1_apbc_reset_data =3D { + .reset_data =3D apbc_resets, + .count =3D ARRAY_SIZE(apbc_resets), +}; + +static const struct ccu_reset_data apmu_resets[] =3D { + [RESET_CCIC_4X] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), + [RESET_CCIC1_PHY] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), + [RESET_SDH_AXI] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), + [RESET_SDH0] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH1] =3D RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH2] =3D RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_USBP1_AXI] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)), + [RESET_USB_AXI] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), + [RESET_USB3_0] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(11) | BIT(10) | BIT(9)), + [RESET_QSPI] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RESET_QSPI_BUS] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_DMA] =3D RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AES] =3D RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), + [RESET_VPU] =3D RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), + [RESET_GPU] =3D RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC] =3D RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC_X] =3D RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AUDIO] =3D RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, + BIT(3) | BIT(2) | BIT(0)), + [RESET_HDMI] =3D RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)), + [RESET_PCIE0] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE1] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE2] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_EMAC0] =3D RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMAC1] =3D RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_JPG] =3D RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)), + [RESET_CCIC2PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), + [RESET_CCIC3PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), + [RESET_CSI] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_ISP] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)), + [RESET_ISP_CPP] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)), + [RESET_ISP_BUS] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)), + [RESET_ISP_CI] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), + [RESET_DPU_MCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), + [RESET_DPU_ESC] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), + [RESET_DPU_HCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), + [RESET_DPU_SPIBUS] =3D RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)), + [RESET_DPU_SPI_HBUS] =3D RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)), + [RESET_V2D] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), + [RESET_MIPI] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)), + [RESET_MC] =3D RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), +}; + +static const struct ccu_reset_controller_data k1_apmu_reset_data =3D { + .reset_data =3D apmu_resets, + .count =3D ARRAY_SIZE(apmu_resets), +}; + +static int spacemit_k1_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct spacemit_ccu_adev *rdev =3D to_spacemit_ccu_adev(adev); + const void *data =3D (void *)id->driver_data; + struct ccu_reset_controller *controller; + struct device *dev =3D &adev->dev; + + controller =3D devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); + if (!controller) + return -ENODEV; + controller->data =3D data; + controller->regmap =3D rdev->regmap; + + return spacemit_reset_controller_register(dev, controller); +} + +#define K1_AUX_DEV_ID(_unit) \ + { \ + .name =3D "spacemit_ccu_k1." #_unit "-reset", \ + .driver_data =3D (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ + } + +static const struct auxiliary_device_id spacemit_k1_reset_ids[] =3D { + K1_AUX_DEV_ID(mpmu), + K1_AUX_DEV_ID(apbc), + K1_AUX_DEV_ID(apmu), + { }, +}; +MODULE_DEVICE_TABLE(auxiliary, spacemit_k1_reset_ids); + +#undef K1_AUX_DEV_ID + +static struct auxiliary_driver spacemit_k1_reset_driver =3D { + .probe =3D spacemit_k1_reset_probe, + .id_table =3D spacemit_k1_reset_ids, +}; +module_auxiliary_driver(spacemit_k1_reset_driver); --=20 2.45.2