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Peter Anvin" , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list Subject: [PATCH 4/6] x86/msr: Move MSR trace calls one function level up Date: Tue, 6 May 2025 11:20:13 +0200 Message-ID: <20250506092015.1849-5-jgross@suse.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250506092015.1849-1-jgross@suse.com> References: <20250506092015.1849-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_COUNT_TWO(0.00)[2]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[13]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo]; FUZZY_BLOCKED(0.00)[rspamd.com]; FROM_EQ_ENVFROM(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Level: Content-Type: text/plain; charset="utf-8" In order to prepare paravirt inlining of the MSR access instructions move the calls of MSR trace functions one function level up. Introduce helpers {read|write}_msr[_safe]() helpers allowing to have common definitions in msr.h doing the trace calls. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 102 ++++++++++++++++++++------------ arch/x86/include/asm/paravirt.h | 38 +++--------- 2 files changed, 73 insertions(+), 67 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index a9ce56fc8785..3a94cffb6a3e 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -103,14 +103,7 @@ static __always_inline u64 native_rdmsrq(u32 msr) =20 static inline u64 native_read_msr(u32 msr) { - u64 val; - - val =3D __rdmsr(msr); - - if (tracepoint_enabled(read_msr)) - do_trace_read_msr(msr, val, 0); - - return val; + return __rdmsr(msr); } =20 static inline int native_read_msr_safe(u32 msr, u64 *p) @@ -123,8 +116,6 @@ static inline int native_read_msr_safe(u32 msr, u64 *p) _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err]) : [err] "=3Dr" (err), EAX_EDX_RET(val, low, high) : "c" (msr)); - if (tracepoint_enabled(read_msr)) - do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), err); =20 *p =3D EAX_EDX_VAL(val, low, high); =20 @@ -135,9 +126,6 @@ static inline int native_read_msr_safe(u32 msr, u64 *p) static inline void notrace native_write_msr(u32 msr, u64 val) { native_wrmsrq(msr, val); - - if (tracepoint_enabled(write_msr)) - do_trace_write_msr(msr, val, 0); } =20 /* Can be uninlined because referenced by paravirt */ @@ -151,8 +139,6 @@ static inline int notrace native_write_msr_safe(u32 msr= , u64 val) : [err] "=3Da" (err) : "c" (msr), "0" ((u32)val), "d" ((u32)(val >> 32)) : "memory"); - if (tracepoint_enabled(write_msr)) - do_trace_write_msr(msr, val, err); return err; } =20 @@ -173,59 +159,96 @@ static inline u64 native_read_pmc(int counter) #include #else #include +static __always_inline u64 read_msr(u32 msr) +{ + return native_read_msr(msr); +} + +static __always_inline int read_msr_safe(u32 msr, u64 *p) +{ + return native_read_msr_safe(msr, p); +} + +static __always_inline void write_msr(u32 msr, u64 val) +{ + native_write_msr(msr, val); +} + +static __always_inline int write_msr_safe(u32 msr, u64 val) +{ + return native_write_msr_safe(msr, val); +} + +static __always_inline u64 rdpmc(int counter) +{ + return native_read_pmc(counter); +} + +#endif /* !CONFIG_PARAVIRT_XXL */ + /* * Access to machine-specific registers (available on 586 and better only) * Note: the rd* operations modify the parameters directly (without using * pointer indirection), this allows gcc to optimize better */ =20 +#define rdmsrq(msr, val) \ +do { \ + (val) =3D read_msr(msr); \ + if (tracepoint_enabled(read_msr)) \ + do_trace_read_msr(msr, val, 0); \ +} while (0) + #define rdmsr(msr, low, high) \ do { \ - u64 __val =3D native_read_msr((msr)); \ + u64 __val; \ + rdmsrq(msr, __val); \ (void)((low) =3D (u32)__val); \ (void)((high) =3D (u32)(__val >> 32)); \ } while (0) =20 -static inline void wrmsr(u32 msr, u32 low, u32 high) +/* rdmsr with exception handling */ +static inline int rdmsrq_safe(u32 msr, u64 *p) { - native_write_msr(msr, (u64)high << 32 | low); -} + int err; =20 -#define rdmsrq(msr, val) \ - ((val) =3D native_read_msr((msr))) + err =3D read_msr_safe(msr, p); =20 -static inline void wrmsrq(u32 msr, u64 val) -{ - native_write_msr(msr, val); -} + if (tracepoint_enabled(read_msr)) + do_trace_read_msr(msr, *p, err); =20 -/* wrmsr with exception handling */ -static inline int wrmsrq_safe(u32 msr, u64 val) -{ - return native_write_msr_safe(msr, val); + return err; } =20 -/* rdmsr with exception handling */ #define rdmsr_safe(msr, low, high) \ ({ \ u64 __val; \ - int __err =3D native_read_msr_safe((msr), &__val); \ + int __err =3D rdmsrq_safe((msr), &__val); \ (*low) =3D (u32)__val; \ (*high) =3D (u32)(__val >> 32); \ __err; \ }) =20 -static inline int rdmsrq_safe(u32 msr, u64 *p) +static inline void wrmsrq(u32 msr, u64 val) { - return native_read_msr_safe(msr, p); + write_msr(msr, val); + + if (tracepoint_enabled(write_msr)) + do_trace_write_msr(msr, val, 0); } =20 -static __always_inline u64 rdpmc(int counter) +/* wrmsr with exception handling */ +static inline int wrmsrq_safe(u32 msr, u64 val) { - return native_read_pmc(counter); -} + int err; =20 -#endif /* !CONFIG_PARAVIRT_XXL */ + err =3D write_msr_safe(msr, val); + + if (tracepoint_enabled(write_msr)) + do_trace_write_msr(msr, val, err); + + return err; +} =20 /* Instruction opcode for WRMSRNS supported in binutils >=3D 2.40 */ #define WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) @@ -242,6 +265,11 @@ static __always_inline void wrmsrns(u32 msr, u64 val) : : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32))); } =20 +static inline void wrmsr(u32 msr, u32 low, u32 high) +{ + wrmsrq(msr, (u64)high << 32 | low); +} + /* * Dual u32 version of wrmsrq_safe(): */ diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravir= t.h index 03f680d1057a..a463c747c780 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -195,46 +195,24 @@ static inline int paravirt_write_msr_safe(u32 msr, u6= 4 val) return PVOP_CALL2(int, cpu.write_msr_safe, msr, val); } =20 -#define rdmsr(msr, val1, val2) \ -do { \ - u64 _l =3D paravirt_read_msr(msr); \ - val1 =3D (u32)_l; \ - val2 =3D _l >> 32; \ -} while (0) - -static __always_inline void wrmsr(u32 msr, u32 low, u32 high) +static __always_inline u64 read_msr(u32 msr) { - paravirt_write_msr(msr, (u64)high << 32 | low); + return paravirt_read_msr(msr); } =20 -#define rdmsrq(msr, val) \ -do { \ - val =3D paravirt_read_msr(msr); \ -} while (0) - -static inline void wrmsrq(u32 msr, u64 val) +static __always_inline int read_msr_safe(u32 msr, u64 *p) { - paravirt_write_msr(msr, val); + return paravirt_read_msr_safe(msr, p); } =20 -static inline int wrmsrq_safe(u32 msr, u64 val) +static __always_inline void write_msr(u32 msr, u64 val) { - return paravirt_write_msr_safe(msr, val); + paravirt_write_msr(msr, val); } =20 -/* rdmsr with exception handling */ -#define rdmsr_safe(msr, a, b) \ -({ \ - u64 _l; \ - int _err =3D paravirt_read_msr_safe((msr), &_l); \ - (*a) =3D (u32)_l; \ - (*b) =3D (u32)(_l >> 32); \ - _err; \ -}) - -static __always_inline int rdmsrq_safe(u32 msr, u64 *p) +static __always_inline int write_msr_safe(u32 msr, u64 val) { - return paravirt_read_msr_safe(msr, p); + return paravirt_write_msr_safe(msr, val); } =20 static __always_inline u64 rdpmc(int counter) --=20 2.43.0