From nobody Tue Dec 16 15:29:09 2025 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 828192641EA for ; Tue, 6 May 2025 09:20:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746523238; cv=none; b=vAObxrtkAIEEE/eMzkrOVrPNGIf8d5AAr+me4ocZSXvq4T0WjCEmKHfoSRTsvCfMcNMBD7LwyMpg6LPClROxJDH2Rmdc4f+4GRrZwYI6vw3GCYmwfB8VClAPSd/h42w0f35PWrunb4Jjn8bhgBbMSbye+ol663q3rI6fjvyPkyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746523238; c=relaxed/simple; bh=mqm6FQzDmMlRON9SSlfzxRXYcHRvPocYLlKIBxCFFxc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ENqnJc74jaUBxEVKcFH7w32FRXcDC3R5oSQL2g0xDkw8W2gX6sBh+sA2bUpEIFs6/5x5jPW4gcG+hueN38C+vqSKnjO/+FRF33y1eiM0Qbbldkz26VIWSaLlUihg5rHZwK3cLE90NNzCS/qP1OdfGGIrSl0jqMC/+QmGjdzETJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=QXNxzFU0; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=DsmAEedS; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="QXNxzFU0"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="DsmAEedS" Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id EF14F1F390; Tue, 6 May 2025 09:20:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1746523229; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ScbdEJfIhZ9pRJXcXTcH6qsH3ah9e2Jo6zx2xD+lWow=; b=QXNxzFU0/3nQl1EZV/N7gJi6CPDE/OhXrPF/a6JbMPCVIWFA5meq/4qVBsof7zMhax3sKZ DYRn/MYqLet+gNk6gBrR7wT2lsUzxi+QPo+0l5GNCCqVXjuiYbCAUZzMQiPjE7Cv4+C+X8 dmYwwyun6Vuyw+9NkIUCWj1zbqY3L68= Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1746523228; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ScbdEJfIhZ9pRJXcXTcH6qsH3ah9e2Jo6zx2xD+lWow=; b=DsmAEedSjPtwi6501F++2U2O1Qd1QONqhJzYR+aV7ELS1VKKNXjJtgrg0KMY50VTXnlfvE jluUpiYixIcdXW2OTlfI7L2vTtBg1fntJUngKYPDhvena7F0NBSyjrKn1M18+i1txoZAm0 4GPVPD5E69h/f5A9vZ0M2wIMC9iAUkQ= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 9505A137CF; Tue, 6 May 2025 09:20:28 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id ng8FI1zUGWgIbAAAD6G6ig (envelope-from ); Tue, 06 May 2025 09:20:28 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-coco@lists.linux.dev Cc: xin@zytor.com, Juergen Gross , "Kirill A. Shutemov" , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH 1/6] coco/tdx: Rename MSR access helpers Date: Tue, 6 May 2025 11:20:10 +0200 Message-ID: <20250506092015.1849-2-jgross@suse.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250506092015.1849-1-jgross@suse.com> References: <20250506092015.1849-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Level: X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_COUNT_TWO(0.00)[2]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCPT_COUNT_SEVEN(0.00)[11]; FUZZY_BLOCKED(0.00)[rspamd.com]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; RCVD_TLS_ALL(0.00)[] X-Spam-Score: -6.80 X-Spam-Flag: NO Content-Type: text/plain; charset="utf-8" In order to avoid a name clash with some general MSR access helpers after a future MSR infrastructure rework, rename the TDX specific helpers. Signed-off-by: Juergen Gross Acked-by: Kirill A. Shutemov Tested-by: Michael Kelley --- arch/x86/coco/tdx/tdx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index edab6d6049be..49d79668f85f 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -428,7 +428,7 @@ static void __cpuidle tdx_safe_halt(void) raw_local_irq_enable(); } =20 -static int read_msr(struct pt_regs *regs, struct ve_info *ve) +static int tdx_read_msr(struct pt_regs *regs, struct ve_info *ve) { struct tdx_module_args args =3D { .r10 =3D TDX_HYPERCALL_STANDARD, @@ -449,7 +449,7 @@ static int read_msr(struct pt_regs *regs, struct ve_inf= o *ve) return ve_instr_len(ve); } =20 -static int write_msr(struct pt_regs *regs, struct ve_info *ve) +static int tdx_write_msr(struct pt_regs *regs, struct ve_info *ve) { struct tdx_module_args args =3D { .r10 =3D TDX_HYPERCALL_STANDARD, @@ -802,9 +802,9 @@ static int virt_exception_kernel(struct pt_regs *regs, = struct ve_info *ve) case EXIT_REASON_HLT: return handle_halt(ve); case EXIT_REASON_MSR_READ: - return read_msr(regs, ve); + return tdx_read_msr(regs, ve); case EXIT_REASON_MSR_WRITE: - return write_msr(regs, ve); + return tdx_write_msr(regs, ve); case EXIT_REASON_CPUID: return handle_cpuid(regs, ve); case EXIT_REASON_EPT_VIOLATION: --=20 2.43.0 From nobody Tue Dec 16 15:29:09 2025 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85E2C267B8D for ; Tue, 6 May 2025 09:20:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746523239; cv=none; b=rvETyWseGObh0fPwipoouVIPbkonuI2qoNqKX8yQSdL/zbrNJVnrXLLWa0piJNaOwuiF8dEpB1huFpW2FCvJqKSfiQGGBSJIaCc2JsJUNDkRK0v73FbtdK98izh6ZVGB2lsfLB22VVM3I+ISSxXT8eipq1BjGPT7C2lJ7X2mRW0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746523239; c=relaxed/simple; bh=ORAAokWZRLs1gmD8f0jM5jt9Hu7eu0t14SnarYgFl58=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=of7X/2X/yRuArUr2sxCYtyBwzRXgp06HhRcxwXv81xwRpgv75+0t8PEwqOA7/7UpDpDLZPWJeYmuyvg71M+/KrJptmIu55OfwAh4v9T6CAgA24zvf9ATAStoY/IL/KaSz6uL2P83c8SqyQHL2HTmr/IgxY6/K/9xZDbK50Sy83M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id CB6A421222; Tue, 6 May 2025 09:20:34 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 6450E137CF; Tue, 6 May 2025 09:20:34 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 5iLfFmLUGWgKbAAAD6G6ig (envelope-from ); Tue, 06 May 2025 09:20:34 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: xin@zytor.com, Juergen Gross , Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH 2/6] x86/kvm: Rename the KVM private read_msr() function Date: Tue, 6 May 2025 11:20:11 +0200 Message-ID: <20250506092015.1849-3-jgross@suse.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250506092015.1849-1-jgross@suse.com> References: <20250506092015.1849-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Level: X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Spam-Score: -4.00 X-Spam-Flag: NO X-Rspamd-Queue-Id: CB6A421222 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org Content-Type: text/plain; charset="utf-8" Avoid a name clash with a new general MSR access helper after a future MSR infrastructure rework by renaming the KVM specific read_msr() to kvm_read_msr(). Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/vmx/vmx.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 9c971f846108..308f7020dc9d 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -2275,7 +2275,7 @@ static inline void kvm_load_ldt(u16 sel) } =20 #ifdef CONFIG_X86_64 -static inline unsigned long read_msr(unsigned long msr) +static inline unsigned long kvm_read_msr(unsigned long msr) { u64 value; =20 diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 63de5f6051e5..5a5f3c57363c 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1335,8 +1335,8 @@ void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcp= u) } else { savesegment(fs, fs_sel); savesegment(gs, gs_sel); - fs_base =3D read_msr(MSR_FS_BASE); - vmx->msr_host_kernel_gs_base =3D read_msr(MSR_KERNEL_GS_BASE); + fs_base =3D kvm_read_msr(MSR_FS_BASE); + vmx->msr_host_kernel_gs_base =3D kvm_read_msr(MSR_KERNEL_GS_BASE); } =20 wrmsrq(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); --=20 2.43.0 From nobody Tue Dec 16 15:29:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=quarantine dis=quarantine) header.from=suse.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1746523257210254.8843786907346; Tue, 6 May 2025 02:20:57 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.976923.1364033 (Exim 4.92) (envelope-from ) id 1uCETj-0002mD-HS; Tue, 06 May 2025 09:20:43 +0000 Received: by outflank-mailman (output) from mailman id 976923.1364033; Tue, 06 May 2025 09:20:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uCETj-0002m6-Dt; Tue, 06 May 2025 09:20:43 +0000 Received: by outflank-mailman (input) for mailman id 976923; Tue, 06 May 2025 09:20:42 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uCETi-0002lJ-Ae for xen-devel@lists.xenproject.org; Tue, 06 May 2025 09:20:42 +0000 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 614736f9-2a5b-11f0-9eb4-5ba50f476ded; Tue, 06 May 2025 11:20:41 +0200 (CEST) Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id F06B01F391; Tue, 6 May 2025 09:20:40 +0000 (UTC) Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 49800137CF; Tue, 6 May 2025 09:20:40 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id zH5wEGjUGWggbAAAD6G6ig (envelope-from ); Tue, 06 May 2025 09:20:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 614736f9-2a5b-11f0-9eb4-5ba50f476ded Authentication-Results: smtp-out2.suse.de; none From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-hyperv@vger.kernel.org, kvm@vger.kernel.org Cc: xin@zytor.com, Juergen Gross , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Paolo Bonzini , Vitaly Kuznetsov , Sean Christopherson , Boris Ostrovsky , xen-devel@lists.xenproject.org Subject: [PATCH 3/6] x86/msr: minimize usage of native_*() msr access functions Date: Tue, 6 May 2025 11:20:12 +0200 Message-ID: <20250506092015.1849-4-jgross@suse.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250506092015.1849-1-jgross@suse.com> References: <20250506092015.1849-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Level: X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Spam-Score: -4.00 X-Spam-Flag: NO X-Rspamd-Queue-Id: F06B01F391 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-ZM-MESSAGEID: 1746523259410019000 Content-Type: text/plain; charset="utf-8" In order to prepare for some MSR access function reorg work, switch most users of native_{read|write}_msr[_safe]() to the more generic rdmsr*()/wrmsr*() variants. For now this will have some intermediate performance impact with paravirtualization configured when running on bare metal, but this is a prereq change for the planned direct inlining of the rdmsr/wrmsr instructions with this configuration. The main reason for this switch is the planned move of the MSR trace function invocation from the native_*() functions to the generic rdmsr*()/wrmsr*() variants. Without this switch the users of the native_*() functions would lose the related tracing entries. Note that the Xen related MSR access functions will not be switched, as these will be handled after the move of the trace hooks. Signed-off-by: Juergen Gross Acked-by: Sean Christopherson Acked-by: Wei Liu Tested-by: Michael Kelley --- arch/x86/hyperv/ivm.c | 2 +- arch/x86/kernel/kvmclock.c | 2 +- arch/x86/kvm/svm/svm.c | 16 ++++++++-------- arch/x86/xen/pmu.c | 4 ++-- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index 09a165a3c41e..fe177a6be581 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -319,7 +319,7 @@ int hv_snp_boot_ap(u32 cpu, unsigned long start_ip) asm volatile("movl %%ds, %%eax;" : "=3Da" (vmsa->ds.selector)); hv_populate_vmcb_seg(vmsa->ds, vmsa->gdtr.base); =20 - vmsa->efer =3D native_read_msr(MSR_EFER); + rdmsrq(MSR_EFER, vmsa->efer); =20 vmsa->cr4 =3D native_read_cr4(); vmsa->cr3 =3D __native_read_cr3(); diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c index ca0a49eeac4a..b6cd45cce5fe 100644 --- a/arch/x86/kernel/kvmclock.c +++ b/arch/x86/kernel/kvmclock.c @@ -196,7 +196,7 @@ static void kvm_setup_secondary_clock(void) void kvmclock_disable(void) { if (msr_kvm_system_time) - native_write_msr(msr_kvm_system_time, 0); + wrmsrq(msr_kvm_system_time, 0); } =20 static void __init kvmclock_init_mem(void) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 4c2a843780bf..3f0eed84f82a 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -482,12 +482,12 @@ static void svm_init_erratum_383(void) return; =20 /* Use _safe variants to not break nested virtualization */ - if (native_read_msr_safe(MSR_AMD64_DC_CFG, &val)) + if (rdmsrq_safe(MSR_AMD64_DC_CFG, &val)) return; =20 val |=3D (1ULL << 47); =20 - native_write_msr_safe(MSR_AMD64_DC_CFG, val); + wrmsrq_safe(MSR_AMD64_DC_CFG, val); =20 erratum_383_found =3D true; } @@ -650,9 +650,9 @@ static int svm_enable_virtualization_cpu(void) u64 len, status =3D 0; int err; =20 - err =3D native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &len); + err =3D rdmsrq_safe(MSR_AMD64_OSVW_ID_LENGTH, &len); if (!err) - err =3D native_read_msr_safe(MSR_AMD64_OSVW_STATUS, &status); + err =3D rdmsrq_safe(MSR_AMD64_OSVW_STATUS, &status); =20 if (err) osvw_status =3D osvw_len =3D 0; @@ -2149,7 +2149,7 @@ static bool is_erratum_383(void) if (!erratum_383_found) return false; =20 - if (native_read_msr_safe(MSR_IA32_MC0_STATUS, &value)) + if (rdmsrq_safe(MSR_IA32_MC0_STATUS, &value)) return false; =20 /* Bit 62 may or may not be set for this mce */ @@ -2160,11 +2160,11 @@ static bool is_erratum_383(void) =20 /* Clear MCi_STATUS registers */ for (i =3D 0; i < 6; ++i) - native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0); + wrmsrq_safe(MSR_IA32_MCx_STATUS(i), 0); =20 - if (!native_read_msr_safe(MSR_IA32_MCG_STATUS, &value)) { + if (!rdmsrq_safe(MSR_IA32_MCG_STATUS, &value)) { value &=3D ~(1ULL << 2); - native_write_msr_safe(MSR_IA32_MCG_STATUS, value); + wrmsrq_safe(MSR_IA32_MCG_STATUS, value); } =20 /* Flush tlb to evict multi-match entries */ diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 8f89ce0b67e3..d49a3bdc448b 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -323,7 +323,7 @@ static u64 xen_amd_read_pmc(int counter) u64 val; =20 msr =3D amd_counters_base + (counter * amd_msr_step); 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Peter Anvin" , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list Subject: [PATCH 4/6] x86/msr: Move MSR trace calls one function level up Date: Tue, 6 May 2025 11:20:13 +0200 Message-ID: <20250506092015.1849-5-jgross@suse.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250506092015.1849-1-jgross@suse.com> References: <20250506092015.1849-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_COUNT_TWO(0.00)[2]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[13]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo]; FUZZY_BLOCKED(0.00)[rspamd.com]; FROM_EQ_ENVFROM(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Level: Content-Type: text/plain; charset="utf-8" In order to prepare paravirt inlining of the MSR access instructions move the calls of MSR trace functions one function level up. Introduce helpers {read|write}_msr[_safe]() helpers allowing to have common definitions in msr.h doing the trace calls. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- arch/x86/include/asm/msr.h | 102 ++++++++++++++++++++------------ arch/x86/include/asm/paravirt.h | 38 +++--------- 2 files changed, 73 insertions(+), 67 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index a9ce56fc8785..3a94cffb6a3e 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -103,14 +103,7 @@ static __always_inline u64 native_rdmsrq(u32 msr) =20 static inline u64 native_read_msr(u32 msr) { - u64 val; - - val =3D __rdmsr(msr); - - if (tracepoint_enabled(read_msr)) - do_trace_read_msr(msr, val, 0); - - return val; + return __rdmsr(msr); } =20 static inline int native_read_msr_safe(u32 msr, u64 *p) @@ -123,8 +116,6 @@ static inline int native_read_msr_safe(u32 msr, u64 *p) _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err]) : [err] "=3Dr" (err), EAX_EDX_RET(val, low, high) : "c" (msr)); - if (tracepoint_enabled(read_msr)) - do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), err); =20 *p =3D EAX_EDX_VAL(val, low, high); =20 @@ -135,9 +126,6 @@ static inline int native_read_msr_safe(u32 msr, u64 *p) static inline void notrace native_write_msr(u32 msr, u64 val) { native_wrmsrq(msr, val); - - if (tracepoint_enabled(write_msr)) - do_trace_write_msr(msr, val, 0); } =20 /* Can be uninlined because referenced by paravirt */ @@ -151,8 +139,6 @@ static inline int notrace native_write_msr_safe(u32 msr= , u64 val) : [err] "=3Da" (err) : "c" (msr), "0" ((u32)val), "d" ((u32)(val >> 32)) : "memory"); - if (tracepoint_enabled(write_msr)) - do_trace_write_msr(msr, val, err); return err; } =20 @@ -173,59 +159,96 @@ static inline u64 native_read_pmc(int counter) #include #else #include +static __always_inline u64 read_msr(u32 msr) +{ + return native_read_msr(msr); +} + +static __always_inline int read_msr_safe(u32 msr, u64 *p) +{ + return native_read_msr_safe(msr, p); +} + +static __always_inline void write_msr(u32 msr, u64 val) +{ + native_write_msr(msr, val); +} + +static __always_inline int write_msr_safe(u32 msr, u64 val) +{ + return native_write_msr_safe(msr, val); +} + +static __always_inline u64 rdpmc(int counter) +{ + return native_read_pmc(counter); +} + +#endif /* !CONFIG_PARAVIRT_XXL */ + /* * Access to machine-specific registers (available on 586 and better only) * Note: the rd* operations modify the parameters directly (without using * pointer indirection), this allows gcc to optimize better */ =20 +#define rdmsrq(msr, val) \ +do { \ + (val) =3D read_msr(msr); \ + if (tracepoint_enabled(read_msr)) \ + do_trace_read_msr(msr, val, 0); \ +} while (0) + #define rdmsr(msr, low, high) \ do { \ - u64 __val =3D native_read_msr((msr)); \ + u64 __val; \ + rdmsrq(msr, __val); \ (void)((low) =3D (u32)__val); \ (void)((high) =3D (u32)(__val >> 32)); \ } while (0) =20 -static inline void wrmsr(u32 msr, u32 low, u32 high) +/* rdmsr with exception handling */ +static inline int rdmsrq_safe(u32 msr, u64 *p) { - native_write_msr(msr, (u64)high << 32 | low); -} + int err; =20 -#define rdmsrq(msr, val) \ - ((val) =3D native_read_msr((msr))) + err =3D read_msr_safe(msr, p); =20 -static inline void wrmsrq(u32 msr, u64 val) -{ - native_write_msr(msr, val); -} + if (tracepoint_enabled(read_msr)) + do_trace_read_msr(msr, *p, err); =20 -/* wrmsr with exception handling */ -static inline int wrmsrq_safe(u32 msr, u64 val) -{ - return native_write_msr_safe(msr, val); + return err; } =20 -/* rdmsr with exception handling */ #define rdmsr_safe(msr, low, high) \ ({ \ u64 __val; \ - int __err =3D native_read_msr_safe((msr), &__val); \ + int __err =3D rdmsrq_safe((msr), &__val); \ (*low) =3D (u32)__val; \ (*high) =3D (u32)(__val >> 32); \ __err; \ }) =20 -static inline int rdmsrq_safe(u32 msr, u64 *p) +static inline void wrmsrq(u32 msr, u64 val) { - return native_read_msr_safe(msr, p); + write_msr(msr, val); + + if (tracepoint_enabled(write_msr)) + do_trace_write_msr(msr, val, 0); } =20 -static __always_inline u64 rdpmc(int counter) +/* wrmsr with exception handling */ +static inline int wrmsrq_safe(u32 msr, u64 val) { - return native_read_pmc(counter); -} + int err; =20 -#endif /* !CONFIG_PARAVIRT_XXL */ + err =3D write_msr_safe(msr, val); + + if (tracepoint_enabled(write_msr)) + do_trace_write_msr(msr, val, err); + + return err; +} =20 /* Instruction opcode for WRMSRNS supported in binutils >=3D 2.40 */ #define WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) @@ -242,6 +265,11 @@ static __always_inline void wrmsrns(u32 msr, u64 val) : : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32))); } =20 +static inline void wrmsr(u32 msr, u32 low, u32 high) +{ + wrmsrq(msr, (u64)high << 32 | low); +} + /* * Dual u32 version of wrmsrq_safe(): */ diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravir= t.h index 03f680d1057a..a463c747c780 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -195,46 +195,24 @@ static inline int paravirt_write_msr_safe(u32 msr, u6= 4 val) return PVOP_CALL2(int, cpu.write_msr_safe, msr, val); } =20 -#define rdmsr(msr, val1, val2) \ -do { \ - u64 _l =3D paravirt_read_msr(msr); \ - val1 =3D (u32)_l; \ - val2 =3D _l >> 32; \ -} while (0) - -static __always_inline void wrmsr(u32 msr, u32 low, u32 high) +static __always_inline u64 read_msr(u32 msr) { - paravirt_write_msr(msr, (u64)high << 32 | low); + return paravirt_read_msr(msr); } =20 -#define rdmsrq(msr, val) \ -do { \ - val =3D paravirt_read_msr(msr); \ -} while (0) - -static inline void wrmsrq(u32 msr, u64 val) +static __always_inline int read_msr_safe(u32 msr, u64 *p) { - paravirt_write_msr(msr, val); + return paravirt_read_msr_safe(msr, p); } =20 -static inline int wrmsrq_safe(u32 msr, u64 val) +static __always_inline void write_msr(u32 msr, u64 val) { - return paravirt_write_msr_safe(msr, val); + paravirt_write_msr(msr, val); } =20 -/* rdmsr with exception handling */ -#define rdmsr_safe(msr, a, b) \ -({ \ - u64 _l; \ - int _err =3D paravirt_read_msr_safe((msr), &_l); \ - (*a) =3D (u32)_l; \ - (*b) =3D (u32)(_l >> 32); \ - _err; \ -}) - -static __always_inline int rdmsrq_safe(u32 msr, u64 *p) +static __always_inline int write_msr_safe(u32 msr, u64 val) { - return paravirt_read_msr_safe(msr, p); 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Peter Anvin" , Boris Ostrovsky , xen-devel@lists.xenproject.org Subject: [PATCH 5/6] x86/paravirt: Switch MSR access pv_ops functions to instruction interfaces Date: Tue, 6 May 2025 11:20:14 +0200 Message-ID: <20250506092015.1849-6-jgross@suse.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250506092015.1849-1-jgross@suse.com> References: <20250506092015.1849-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Level: X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; RCPT_COUNT_TWELVE(0.00)[15]; FUZZY_BLOCKED(0.00)[rspamd.com]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; TO_DN_SOME(0.00)[]; RCVD_TLS_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo] X-Spam-Score: -6.80 X-Spam-Flag: NO X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1746523269982116600 Content-Type: text/plain; charset="utf-8" Instead of having callback functions for rdmsr/wrmsr on native, switch to inline the respective instructions directly in order to avoid overhead with the call interface. This requires to use the instruction interfaces for rdmsr/wrmsr emulation when running as a Xen PV guest. In order to prepare support for the immediate forms of RDMSR and WRMSR when not running as a Xen PV guest, use the RDMSR and WRMSR instructions as the fallback case instead of ALT_CALL_INSTR. Note that in the Xen PV case the RDMSR/WRMSR patching must not happen even as an intermediate step, as this would clobber the indirect call information needed when patching in the direct call for the Xen case. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- arch/x86/include/asm/paravirt.h | 114 +++++++++++++++++----- arch/x86/include/asm/paravirt_types.h | 13 ++- arch/x86/include/asm/qspinlock_paravirt.h | 5 +- arch/x86/kernel/paravirt.c | 26 ++++- arch/x86/xen/enlighten_pv.c | 56 ++++++++--- 5 files changed, 167 insertions(+), 47 deletions(-) diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravir= t.h index a463c747c780..df10b0e4f7b8 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -175,24 +175,72 @@ static inline void __write_cr4(unsigned long x) PVOP_VCALL1(cpu.write_cr4, x); } =20 -static inline u64 paravirt_read_msr(u32 msr) +static __always_inline u64 paravirt_read_msr(u32 msr) { - return PVOP_CALL1(u64, cpu.read_msr, msr); + EAX_EDX_DECLARE_ARGS(val, low, high); + + PVOP_TEST_NULL(cpu.read_msr); + asm volatile("1: "ALTERNATIVE_2(PARAVIRT_CALL, + "rdmsr", ALT_NOT_XEN, + ALT_CALL_INSTR, ALT_XENPV_CALL) + "2:\n" + _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR) + : EAX_EDX_RET(val, low, high), ASM_CALL_CONSTRAINT + : paravirt_ptr(cpu.read_msr), "c" (msr)); + + return EAX_EDX_VAL(val, low, high); } =20 -static inline void paravirt_write_msr(u32 msr, u64 val) +static __always_inline void paravirt_write_msr(u32 msr, u64 val) { - PVOP_VCALL2(cpu.write_msr, msr, val); + PVOP_TEST_NULL(cpu.write_msr); + asm volatile("1: "ALTERNATIVE_2(PARAVIRT_CALL, + "wrmsr", ALT_NOT_XEN, + ALT_CALL_INSTR, ALT_XENPV_CALL) + "2:\n" + _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR) + : ASM_CALL_CONSTRAINT + : paravirt_ptr(cpu.write_msr), + "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32)) + : "memory"); } =20 -static inline int paravirt_read_msr_safe(u32 msr, u64 *val) +static __always_inline int paravirt_read_msr_safe(u32 msr, u64 *p) { - return PVOP_CALL2(int, cpu.read_msr_safe, msr, val); + int err; + EAX_EDX_DECLARE_ARGS(val, low, high); + + PVOP_TEST_NULL(cpu.read_msr_safe); + asm volatile("1: "ALTERNATIVE_2(PARAVIRT_CALL, + "rdmsr; xor %[err],%[err]", ALT_NOT_XEN, + ALT_CALL_INSTR, ALT_XENPV_CALL) + "2:\n" + _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err]) + : [err] "=3Dc" (err), EAX_EDX_RET(val, low, high), + ASM_CALL_CONSTRAINT + : paravirt_ptr(cpu.read_msr_safe), "0" (msr)); + + *p =3D EAX_EDX_VAL(val, low, high); + + return err; } =20 -static inline int paravirt_write_msr_safe(u32 msr, u64 val) +static __always_inline int paravirt_write_msr_safe(u32 msr, u64 val) { - return PVOP_CALL2(int, cpu.write_msr_safe, msr, val); + int err; + + PVOP_TEST_NULL(cpu.write_msr_safe); + asm volatile("1: "ALTERNATIVE_2(PARAVIRT_CALL, + "wrmsr; xor %[err],%[err]", ALT_NOT_XEN, + ALT_CALL_INSTR, ALT_XENPV_CALL) + "2:\n" + _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_WRMSR_SAFE, %[err]) + : [err] "=3Da" (err), ASM_CALL_CONSTRAINT + : paravirt_ptr(cpu.write_msr_safe), + "c" (msr), "0" ((u32)val), "d" ((u32)(val >> 32)) + : "memory"); + + return err; } =20 static __always_inline u64 read_msr(u32 msr) @@ -573,27 +621,43 @@ bool __raw_callee_save___native_vcpu_is_preempted(lon= g cpu); #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;" #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;" #else +/* save and restore caller-save registers, except %rax, %rcx and %rdx. */ +#define PV_SAVE_COMMON_CALLER_REGS \ + "push %rsi;" \ + "push %rdi;" \ + "push %r8;" \ + "push %r9;" \ + "push %r10;" \ + "push %r11;" +#define PV_RESTORE_COMMON_CALLER_REGS \ + "pop %r11;" \ + "pop %r10;" \ + "pop %r9;" \ + "pop %r8;" \ + "pop %rdi;" \ + "pop %rsi;" + +#define PV_PROLOGUE_MSR(func) \ + PV_SAVE_COMMON_CALLER_REGS \ + PV_PROLOGUE_MSR_##func +#define PV_EPILOGUE_MSR(func) \ + PV_EPILOGUE_MSR_##func \ + PV_RESTORE_COMMON_CALLER_REGS + /* save and restore all caller-save registers, except return value */ #define PV_SAVE_ALL_CALLER_REGS \ "push %rcx;" \ "push %rdx;" \ - "push %rsi;" \ - "push %rdi;" \ - "push %r8;" \ - "push %r9;" \ - "push %r10;" \ - "push %r11;" + PV_SAVE_COMMON_CALLER_REGS #define PV_RESTORE_ALL_CALLER_REGS \ - "pop %r11;" \ - "pop %r10;" \ - "pop %r9;" \ - "pop %r8;" \ - "pop %rdi;" \ - "pop %rsi;" \ + PV_RESTORE_COMMON_CALLER_REGS \ "pop %rdx;" \ "pop %rcx;" #endif =20 +#define PV_PROLOGUE_ALL(func) PV_SAVE_ALL_CALLER_REGS +#define PV_EPILOGUE_ALL(func) PV_RESTORE_ALL_CALLER_REGS + /* * Generate a thunk around a function which saves all caller-save * registers except for the return value. This allows C functions to @@ -607,7 +671,7 @@ bool __raw_callee_save___native_vcpu_is_preempted(long = cpu); * functions. */ #define PV_THUNK_NAME(func) "__raw_callee_save_" #func -#define __PV_CALLEE_SAVE_REGS_THUNK(func, section) \ +#define __PV_CALLEE_SAVE_REGS_THUNK(func, section, helper) \ extern typeof(func) __raw_callee_save_##func; \ \ asm(".pushsection " section ", \"ax\";" \ @@ -617,16 +681,18 @@ bool __raw_callee_save___native_vcpu_is_preempted(lon= g cpu); PV_THUNK_NAME(func) ":" \ ASM_ENDBR \ FRAME_BEGIN \ - PV_SAVE_ALL_CALLER_REGS \ + PV_PROLOGUE_##helper(func) \ "call " #func ";" \ - PV_RESTORE_ALL_CALLER_REGS \ + PV_EPILOGUE_##helper(func) \ FRAME_END \ ASM_RET \ ".size " PV_THUNK_NAME(func) ", .-" PV_THUNK_NAME(func) ";" \ ".popsection") =20 #define PV_CALLEE_SAVE_REGS_THUNK(func) \ - __PV_CALLEE_SAVE_REGS_THUNK(func, ".text") + __PV_CALLEE_SAVE_REGS_THUNK(func, ".text", ALL) +#define PV_CALLEE_SAVE_REGS_MSR_THUNK(func) \ + __PV_CALLEE_SAVE_REGS_THUNK(func, ".text", MSR) =20 /* Get a reference to a callee-save function */ #define PV_CALLEE_SAVE(func) \ diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/p= aravirt_types.h index b08b9d3122d6..f7f879319e90 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -91,15 +91,15 @@ struct pv_cpu_ops { unsigned int *ecx, unsigned int *edx); =20 /* Unsafe MSR operations. These will warn or panic on failure. */ - u64 (*read_msr)(u32 msr); - void (*write_msr)(u32 msr, u64 val); + struct paravirt_callee_save read_msr; + struct paravirt_callee_save write_msr; =20 /* * Safe MSR operations. * Returns 0 or -EIO. */ - int (*read_msr_safe)(u32 msr, u64 *val); - int (*write_msr_safe)(u32 msr, u64 val); + struct paravirt_callee_save read_msr_safe; + struct paravirt_callee_save write_msr_safe; =20 u64 (*read_pmc)(int counter); =20 @@ -520,6 +520,10 @@ unsigned long pv_native_save_fl(void); void pv_native_irq_disable(void); void pv_native_irq_enable(void); unsigned long pv_native_read_cr2(void); +void pv_native_rdmsr(void); +void pv_native_wrmsr(void); +void pv_native_rdmsr_safe(void); +void pv_native_wrmsr_safe(void); #endif =20 #define paravirt_nop ((void *)nop_func) @@ -527,6 +531,7 @@ unsigned long pv_native_read_cr2(void); #endif /* __ASSEMBLER__ */ =20 #define ALT_NOT_XEN ALT_NOT(X86_FEATURE_XENPV) +#define ALT_XENPV_CALL ALT_DIRECT_CALL(X86_FEATURE_XENPV) =20 #endif /* CONFIG_PARAVIRT */ #endif /* _ASM_X86_PARAVIRT_TYPES_H */ diff --git a/arch/x86/include/asm/qspinlock_paravirt.h b/arch/x86/include/a= sm/qspinlock_paravirt.h index 0a985784be9b..0351acb5a143 100644 --- a/arch/x86/include/asm/qspinlock_paravirt.h +++ b/arch/x86/include/asm/qspinlock_paravirt.h @@ -14,7 +14,8 @@ void __lockfunc __pv_queued_spin_unlock_slowpath(struct q= spinlock *lock, u8 lock */ #ifdef CONFIG_64BIT =20 -__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock_slowpath, ".spinlock.t= ext"); +__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock_slowpath, ".spinlock.t= ext", + ALL); #define __pv_queued_spin_unlock __pv_queued_spin_unlock =20 /* @@ -61,7 +62,7 @@ DEFINE_ASM_FUNC(__raw_callee_save___pv_queued_spin_unlock, #else /* CONFIG_64BIT */ =20 extern void __lockfunc __pv_queued_spin_unlock(struct qspinlock *lock); -__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock, ".spinlock.text"); +__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock, ".spinlock.text", ALL= ); =20 #endif /* CONFIG_64BIT */ #endif diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 015bf298434f..ff7d7fdae360 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -50,6 +50,24 @@ DEFINE_ASM_FUNC(pv_native_save_fl, "pushf; pop %rax", .n= oinstr.text); DEFINE_ASM_FUNC(pv_native_irq_disable, "cli", .noinstr.text); DEFINE_ASM_FUNC(pv_native_irq_enable, "sti", .noinstr.text); DEFINE_ASM_FUNC(pv_native_read_cr2, "mov %cr2, %rax", .noinstr.text); +DEFINE_ASM_FUNC(pv_native_rdmsr, + "1: rdmsr\n" + "2:\n" + _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR), .noinstr.text); +DEFINE_ASM_FUNC(pv_native_wrmsr, + "1: wrmsr\n" + "2:\n" + _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR), .noinstr.text); +DEFINE_ASM_FUNC(pv_native_rdmsr_safe, + "1: rdmsr; xor %ecx, %ecx\n" + "2:\n" + _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %%ecx), + .noinstr.text); +DEFINE_ASM_FUNC(pv_native_wrmsr_safe, + "1: wrmsr; xor %eax, %eax\n" + "2:\n" + _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_WRMSR_SAFE, %%eax), + .noinstr.text); #endif =20 DEFINE_STATIC_KEY_FALSE(virt_spin_lock_key); @@ -129,10 +147,10 @@ struct paravirt_patch_template pv_ops =3D { .cpu.read_cr0 =3D native_read_cr0, .cpu.write_cr0 =3D native_write_cr0, .cpu.write_cr4 =3D native_write_cr4, - .cpu.read_msr =3D native_read_msr, - .cpu.write_msr =3D native_write_msr, - .cpu.read_msr_safe =3D native_read_msr_safe, - .cpu.write_msr_safe =3D native_write_msr_safe, + .cpu.read_msr =3D __PV_IS_CALLEE_SAVE(pv_native_rdmsr), + .cpu.write_msr =3D __PV_IS_CALLEE_SAVE(pv_native_wrmsr), + .cpu.read_msr_safe =3D __PV_IS_CALLEE_SAVE(pv_native_rdmsr_safe), + .cpu.write_msr_safe =3D __PV_IS_CALLEE_SAVE(pv_native_wrmsr_safe), .cpu.read_pmc =3D native_read_pmc, .cpu.load_tr_desc =3D native_load_tr_desc, .cpu.set_ldt =3D native_set_ldt, diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 3be38350f044..c279b2bef7eb 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1160,36 +1160,66 @@ static void xen_do_write_msr(u32 msr, u64 val, int = *err) } } =20 -static int xen_read_msr_safe(u32 msr, u64 *val) -{ +/* + * Prototypes for functions called via PV_CALLEE_SAVE_REGS_THUNK() in order + * to avoid warnings with "-Wmissing-prototypes". + */ +struct xen_rdmsr_safe_ret { + u64 val; int err; +}; +struct xen_rdmsr_safe_ret xen_read_msr_safe(u32 msr); +int xen_write_msr_safe(u32 msr, u32 low, u32 high); +u64 xen_read_msr(u32 msr); +void xen_write_msr(u32 msr, u32 low, u32 high); =20 - *val =3D xen_do_read_msr(msr, &err); - return err; +__visible struct xen_rdmsr_safe_ret xen_read_msr_safe(u32 msr) +{ + struct xen_rdmsr_safe_ret ret; + + ret.val =3D xen_do_read_msr(msr, &ret.err); + return ret; } +#define PV_PROLOGUE_MSR_xen_read_msr_safe "mov %ecx, %edi;" +#define PV_EPILOGUE_MSR_xen_read_msr_safe \ + "mov %edx, %ecx; mov %rax, %rdx; mov %eax, %eax; shr $0x20, %rdx;" +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_read_msr_safe); =20 -static int xen_write_msr_safe(u32 msr, u64 val) +__visible int xen_write_msr_safe(u32 msr, u32 low, u32 high) { int err =3D 0; =20 - xen_do_write_msr(msr, val, &err); + xen_do_write_msr(msr, (u64)high << 32 | low, &err); =20 return err; } +#define PV_PROLOGUE_MSR_xen_write_msr_safe \ + "mov %ecx, %edi; mov %eax, %esi;" +#define PV_EPILOGUE_MSR_xen_write_msr_safe +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_write_msr_safe); =20 -static u64 xen_read_msr(u32 msr) +__visible u64 xen_read_msr(u32 msr) { int err; =20 return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); } +#define PV_PROLOGUE_MSR_xen_read_msr "mov %ecx, %edi;" +#define PV_EPILOGUE_MSR_xen_read_msr \ + "mov %rax, %rdx; mov %eax, %eax; shr $0x20, %rdx;" +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_read_msr); =20 -static void xen_write_msr(u32 msr, u64 val) +__visible void xen_write_msr(u32 msr, u32 low, u32 high) { int err; =20 - xen_do_write_msr(msr, val, xen_msr_safe ? &err : NULL); + xen_do_write_msr(msr, (u64)high << 32 | low, + xen_msr_safe ? &err : NULL); } +#define PV_PROLOGUE_MSR_xen_write_msr \ + "mov %ecx, %edi; mov %eax, %esi;" +#define PV_EPILOGUE_MSR_xen_write_msr +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_write_msr); =20 /* This is called once we have the cpu_possible_mask */ void __init xen_setup_vcpu_info_placement(void) @@ -1225,11 +1255,11 @@ static const typeof(pv_ops) xen_cpu_ops __initconst= =3D { =20 .write_cr4 =3D xen_write_cr4, =20 - .read_msr =3D xen_read_msr, - .write_msr =3D xen_write_msr, + .read_msr =3D PV_CALLEE_SAVE(xen_read_msr), + .write_msr =3D PV_CALLEE_SAVE(xen_write_msr), =20 - .read_msr_safe =3D xen_read_msr_safe, - .write_msr_safe =3D xen_write_msr_safe, + .read_msr_safe =3D PV_CALLEE_SAVE(xen_read_msr_safe), + .write_msr_safe =3D PV_CALLEE_SAVE(xen_write_msr_safe), =20 .read_pmc =3D xen_read_pmc, =20 --=20 2.43.0 From nobody Tue Dec 16 15:29:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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s=susede1; t=1746523258; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3vZ2K2J1ln19F+coajEe0NOzYd5qTlnxqf025hGnVDU=; b=KN5RYi3WKDf5r3VtKmNI3YmBwUzGzvePRrlML95vi4X0xhN9peoD1MOJLbxp5vLh1HRu0k Q+egWSynCrSzt014lYfd2E9PqTjhVD4ppQzcklbbLLGV3D6E8ObFKQGmNx5Nr1Hz9Sfs/q yITmmMV6OT/18+CQ/ixpOIu6S8aXeY8= From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: xin@zytor.com, Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Boris Ostrovsky , xen-devel@lists.xenproject.org Subject: [PATCH 6/6] x86/msr: reduce number of low level MSR access helpers Date: Tue, 6 May 2025 11:20:15 +0200 Message-ID: <20250506092015.1849-7-jgross@suse.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250506092015.1849-1-jgross@suse.com> References: <20250506092015.1849-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_COUNT_TWO(0.00)[2]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCPT_COUNT_SEVEN(0.00)[11]; FUZZY_BLOCKED(0.00)[rspamd.com]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Level: X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1746523277527116600 Content-Type: text/plain; charset="utf-8" Some MSR access helpers are redundant now, so remove the no longer needed ones. At the same time make the native_*_msr_safe() helpers always inline. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- arch/x86/include/asm/msr.h | 20 ++++---------------- arch/x86/xen/enlighten_pv.c | 4 ++-- 2 files changed, 6 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 3a94cffb6a3e..0e2ed1604015 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -101,12 +101,7 @@ static __always_inline u64 native_rdmsrq(u32 msr) #define native_wrmsrq(msr, val) \ __wrmsrq((msr), (val)) =20 -static inline u64 native_read_msr(u32 msr) -{ - return __rdmsr(msr); -} - -static inline int native_read_msr_safe(u32 msr, u64 *p) +static __always_inline int native_read_msr_safe(u32 msr, u64 *p) { int err; EAX_EDX_DECLARE_ARGS(val, low, high); @@ -122,14 +117,7 @@ static inline int native_read_msr_safe(u32 msr, u64 *p) return err; } =20 -/* Can be uninlined because referenced by paravirt */ -static inline void notrace native_write_msr(u32 msr, u64 val) -{ - native_wrmsrq(msr, val); -} - -/* Can be uninlined because referenced by paravirt */ -static inline int notrace native_write_msr_safe(u32 msr, u64 val) +static __always_inline int notrace native_write_msr_safe(u32 msr, u64 val) { int err; =20 @@ -161,7 +149,7 @@ static inline u64 native_read_pmc(int counter) #include static __always_inline u64 read_msr(u32 msr) { - return native_read_msr(msr); + return native_rdmsrq(msr); } =20 static __always_inline int read_msr_safe(u32 msr, u64 *p) @@ -171,7 +159,7 @@ static __always_inline int read_msr_safe(u32 msr, u64 *= p) =20 static __always_inline void write_msr(u32 msr, u64 val) { - native_write_msr(msr, val); + native_wrmsrq(msr, val); } =20 static __always_inline int write_msr_safe(u32 msr, u64 val) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index c279b2bef7eb..ea3d7d583254 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1097,7 +1097,7 @@ static u64 xen_do_read_msr(u32 msr, int *err) if (err) *err =3D native_read_msr_safe(msr, &val); else - val =3D native_read_msr(msr); + val =3D native_rdmsrq(msr); =20 switch (msr) { case MSR_IA32_APICBASE: @@ -1156,7 +1156,7 @@ static void xen_do_write_msr(u32 msr, u64 val, int *e= rr) if (err) *err =3D native_write_msr_safe(msr, val); else - native_write_msr(msr, val); + native_wrmsrq(msr, val); } } =20 --=20 2.43.0