From nobody Tue Dec 16 15:27:54 2025 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [52.229.168.213]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 016E2264A7A; Tue, 6 May 2025 09:12:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=52.229.168.213 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746522744; cv=none; b=qnC5rWFRJXBsPNewv71hQ8zb/47+swiBngpRMH0tDnNYSTVrKySmGtPN70NTLqg5lSZrC0aVYSuRcFdkpTzsdQ1O3A50vGvX8TJ+R9UXjYyCrlraQB2epBZo53W3nnRw8M2mx6sd9giZuP1jYZazfSRDXXtQhNxd7OLcDtb2/fo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746522744; c=relaxed/simple; bh=C/7pcSjSNQqOcujEiqYkXqXli82ajAO071G6czanZF0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dyxrMAnc/zmgZIfAzFLngLRNQp44d/6MAGpAhuOmYWctQfjfuYGHzMi6ZZoAUg5C5Bo3ZCYsjNzDzJFeBv4IfA7iezZGEitpmZIRtpcadJcAEU9xe84GcJeueUd6LkXgkGNM3XXGnX6NUSuPV/E0UyThYJSyvUSZltPh6PAhNAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=52.229.168.213 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0006800LT.eswin.cn (unknown [10.12.96.77]) by app1 (Coremail) with SMTP id TAJkCgBXexFV0hlozyZiAA--.24610S2; Tue, 06 May 2025 17:11:52 +0800 (CST) From: luyulin To: linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kees@kernel.org, gustavoars@kernel.org, brgl@bgdev.pl, linux-hardening@vger.kernel.org Cc: zhengyu@eswincomputing.com, ningyu@eswincomputing.com, huangyifeng@eswincomputing.com, linmin@eswincomputing.com, fenglin@eswincomputing.com, lianghujun@eswincomputing.com, luyulin , Samuel Holland Subject: [PATCH 1/2] dt-bindings: pinctrl: eswin: Document for eic7700 SoC Date: Tue, 6 May 2025 17:11:45 +0800 Message-Id: <20250506091145.1953-1-luyulin@eswincomputing.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20250506090844.1516-1-luyulin@eswincomputing.com> References: <20250506090844.1516-1-luyulin@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TAJkCgBXexFV0hlozyZiAA--.24610S2 X-Coremail-Antispam: 1UD129KBjvJXoWxKr43Ary7JFWUtw47WF43Awb_yoWxJr43pF 43W34fJFnIqF1xGa9Ivw18ur1fJan7AFsxAF1jyry3Xwn0q3WSyr4ayr15WFWDWr4kJ3sx Xayqqa40qF1DCrJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9G14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_Wrylc2xSY4AK6svPMxAIw28IcxkI7VAKI48JMx C20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAF wI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20x vE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v2 0xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxV W8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7sRRKZX5UUUUU== X-CM-SenderInfo: pox13z1lq6v25zlqu0xpsx3x1qjou0bp/ Content-Type: text/plain; charset="utf-8" This commit adds Device Tree binding documentation for the ESWIN EIC7700 pinctrl controller module. The document describes the required properties, compatible strings, and usage examples in the device tree configuration when applying this module. Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Signed-off-by: luyulin --- .../pinctrl/eswin,eic7700-pinctrl.yaml | 156 ++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/eswin,eic7700= -pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/eswin,eic7700-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/eswin,eic7700-pinctrl.ya= ml new file mode 100644 index 000000000000..d8811a8e0a51 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/eswin,eic7700-pinctrl.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/eswin,eic7700-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin Eic7700 Pinctrl + +maintainers: + - LuYuLin + +description: | + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of= the + phrase "pin configuration node". + + eic7700 pin configuration nodes act as a container for an arbitrary numb= er of + subnodes. Each of these subnodes represents some desired configuration f= or one or + more pins. This configuration can include the mux function to select on = those pin(s), + and various pin configuration parameters, such as input-enable, pull-up,= etc. + +properties: + compatible: + const: eswin,eic7700-pinctrl + + reg: + description: Specifies the base address and size of the SLCR space. + maxItems: 1 + + "vrgmii-supply": + description: + Regulator supply for the RGMII interface IO power domain. + This property should reference a regulator that provides either 1.8V= or 3.3V, + depending on the board-level voltage configuration required by the R= GMII interface. + +patternProperties: + '^(.*-)?(pins)$': + type: object + description: + Pinctrl node's client devices use subnodes for pin muxes, + which in turn use below standard properties. + + properties: + pins: + description: + For eic7700, specifies the name(s) of one or more pins to be con= figured by + this node. + items: + enum: [ chip_mode, mode_set0, mode_set1, mode_set2, mode_set3, x= in, + rst_out_n, key_reset_n, gpio0, por_sel, jtag0_tck, jtag0= _tms, + jtag0_tdi, jtag0_tdo, gpio5, spi2_cs0_n, jtag1_tck, jtag= 1_tms, + jtag1_tdi, jtag1_tdo, gpio11, spi2_cs1_n, pcie_clkreq_n, + pcie_wake_n, pcie_perst_n, hdmi_scl, hdmi_sda, hdmi_cec, + jtag2_trst, rgmii0_clk_125, rgmii0_txen, rgmii0_txclk, + rgmii0_txd0, rgmii0_txd1, rgmii0_txd2, rgmii0_txd3, i2s0= _bclk, + i2s0_wclk, i2s0_sdi, i2s0_sdo, i2s_mclk, rgmii0_rxclk, + rgmii0_rxdv, rgmii0_rxd0, rgmii0_rxd1, rgmii0_rxd2, rgmi= i0_rxd3, + i2s2_bclk, i2s2_wclk, i2s2_sdi, i2s2_sdo, gpio27, gpio28= , gpio29, + rgmii0_mdc, rgmii0_mdio, rgmii0_intb, rgmii1_clk_125, rg= mii1_txen, + rgmii1_txclk, rgmii1_txd0, rgmii1_txd1, rgmii1_txd2, rgm= ii1_txd3, + i2s1_bclk, i2s1_wclk, i2s1_sdi, i2s1_sdo, gpio34, rgmii1= _rxclk, + rgmii1_rxdv, rgmii1_rxd0, rgmii1_rxd1, rgmii1_rxd2, rgmi= i1_rxd3, + spi1_cs0_n, spi1_clk, spi1_d0, spi1_d1, spi1_d2, spi1_d3= , spi1_cs1_n, + rgmii1_mdc, rgmii1_mdio, rgmii1_intb, usb0_pwren, usb1_p= wren, + i2c0_scl, i2c0_sda, i2c1_scl, i2c1_sda, i2c2_scl, i2c2_s= da, + i2c3_scl, i2c3_sda, i2c4_scl, i2c4_sda, i2c5_scl, i2c5_s= da, + uart0_tx, uart0_rx, uart1_tx, uart1_rx, uart1_cts, uart1= _rts, + uart2_tx, uart2_rx, jtag2_tck, jtag2_tms, jtag2_tdi, jta= g2_tdo, + fan_pwm, fan_tach, mipi_csi0_xvs, mipi_csi0_xhs, mipi_cs= i0_mclk, + mipi_csi1_xvs, mipi_csi1_xhs, mipi_csi1_mclk, mipi_csi2_= xvs, + mipi_csi2_xhs, mipi_csi2_mclk, mipi_csi3_xvs, mipi_csi3_= xhs, + mipi_csi3_mclk, mipi_csi4_xvs, mipi_csi4_xhs, mipi_csi4_= mclk, + mipi_csi5_xvs, mipi_csi5_xhs, mipi_csi5_mclk, spi3_cs_n,= spi3_clk, + spi3_di, spi3_do, gpio92, gpio93, s_mode, gpio95, spi0_c= s_n, + spi0_clk, spi0_d0, spi0_d1, spi0_d2, spi0_d3, i2c10_scl, + i2c10_sda, i2c11_scl, i2c11_sda, gpio106, boot_sel0, boo= t_sel1, + boot_sel2, boot_sel3, gpio111, lpddr_ref_clk ] + + function: + description: + Specify the alternative function to be configured for the + given pins. + enum: [ disabled, boot_sel, chip_mode, emmc, fan_tach, + gpio, hdmi, i2c, i2s, jtag, ddr_ref_clk_sel, + lpddr_ref_clk, mipi_csi, osc, pcie, pwm, + rgmii, reset, sata, sdio, spi, s_mode, uart, usb ] + + input-schmitt-enable: true + + input-schmitt-disable: true + + bias-disable: true + + bias-pull-down: true + + bias-pull-up: true + + input-enable: true + + input-disable: true + + drive-strength-microamp: true + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + - if: + properties: + pins: + anyOf: + - pattern: '^rgmii' + - const: lpddr_ref_clk + then: + properties: + drive-strength-microamp: + enum: [3000, 6000, 9000, 12000, 15000, 18000, 21000, 24000] + else: + properties: + drive-strength-microamp: + enum: [6000, 9000, 12000, 15000, 18000, 21000, 24000, 27000] + + required: + - pins + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@51600080 { + compatible =3D "eswin,eic7700-pinctrl"; + reg =3D <0x51600080 0x1fff80>; + vrgmii-supply =3D <&vcc_1v8>; + gpio10_pins: gpio10-pins { + pins =3D "jtag1_tdo"; + function =3D "gpio"; + input-enable; + bias-pull-up; + }; + }; + + i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio10_pins>; + }; + +... --=20 2.25.1 From nobody Tue Dec 16 15:27:54 2025 Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net (zg8tmja5ljk3lje4ms43mwaa.icoremail.net [209.97.181.73]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B37E326E17D; Tue, 6 May 2025 09:12:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.97.181.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746522783; cv=none; b=IyZEr+pM5mwz4m0ATEySe/9Zpl/gcT91hLsuxBuY62crL9uEO4HmL1wsZY1lzM7Fga19AsyLNfVsKZxxIt6LORUEiwZDZIx/Z/FVh1dnHs7UM3XhkK7CTAKEdYaSQivbIJkC5n9jOMcqsSejt9SMIp0JYYngn0pnAvwJe+/7w5w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746522783; c=relaxed/simple; bh=FuKYerAvgUwnMi+61ynrHxZRT59ys9bGsnXKWjCKop0=; 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charset="utf-8" Add support for the pin controller in ESWIN's EIC7700 SoC, which supports pin multiplexing, pin configuration, and rgmii voltage control. Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Signed-off-by: luyulin --- drivers/pinctrl/Kconfig | 11 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-eic7700.c | 701 ++++++++++++++++++++++++++++++ 3 files changed, 713 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-eic7700.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 464cc9aca157..5e709a3f76bc 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -208,6 +208,17 @@ config PINCTRL_DIGICOLOR select PINMUX select GENERIC_PINCONF =20 +config PINCTRL_EIC7700 + tristate "EIC7700 PINCTRL driver" + depends on ARCH_ESWIN || COMPILE_TEST + select PINMUX + select GENERIC_PINCONF + help + This driver support for the pin controller in ESWIN's EIC7700 SoC, + which supports pin multiplexing, pin configuration,and rgmii voltage + control. + Say Y here to enable the eic7700 pinctrl driver + config PINCTRL_EP93XX bool depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index ac27e88677d1..82e0d4cf5045 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_CY8C95X0) +=3D pinctrl-cy8c95x0.o obj-$(CONFIG_PINCTRL_DA850_PUPD) +=3D pinctrl-da850-pupd.o obj-$(CONFIG_PINCTRL_DA9062) +=3D pinctrl-da9062.o obj-$(CONFIG_PINCTRL_DIGICOLOR) +=3D pinctrl-digicolor.o +obj-$(CONFIG_PINCTRL_EIC7700) +=3D pinctrl-eic7700.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) +=3D pinctrl-equilibrium.o obj-$(CONFIG_PINCTRL_EP93XX) +=3D pinctrl-ep93xx.o obj-$(CONFIG_PINCTRL_EYEQ5) +=3D pinctrl-eyeq5.o diff --git a/drivers/pinctrl/pinctrl-eic7700.c b/drivers/pinctrl/pinctrl-ei= c7700.c new file mode 100644 index 000000000000..32eec889949f --- /dev/null +++ b/drivers/pinctrl/pinctrl-eic7700.c @@ -0,0 +1,701 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ESWIN Pinctrl Controller Platform Device Driver + * + * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All right= s reserved. + * + * Authors: Samuel Holland + * Yulin Lu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "core.h" +#include "pinmux.h" +#include "pinconf.h" + +#define EIC7700_PIN_REG(i) (4 * (i)) +#define EIC7700_IE BIT(0) +#define EIC7700_PU BIT(1) +#define EIC7700_PD BIT(2) +#define EIC7700_DS GENMASK(6, 3) +#define EIC7700_ST BIT(7) +#define EIC7700_FUNC_SEL GENMASK(18, 16) + +#define EIC7700_BIAS (EIC7700_PD | EIC7700_PU) +#define EIC7700_PINCONF GENMASK(7, 0) + +#define EIC7700_RGMII0_SEL_MODE (0x310 - 0x80) +#define EIC7700_RGMII1_SEL_MODE (0x314 - 0x80) +#define EIC7700_MS GENMASK(1, 0) +#define EIC7700_MS_3V3 0x0 +#define EIC7700_MS_1V8 0x3 + +#define EIC7700_FUNCTIONS_PER_PIN 8 + +struct eic7700_pin { + u8 functions[EIC7700_FUNCTIONS_PER_PIN]; +}; + +struct eic7700_pinctrl { + void __iomem *base; + struct pinctrl_desc desc; + unsigned int functions_count; + struct pinfunction functions[] __counted_by(functions_count); +}; + +enum { + F_DISABLED, + F_BOOT_SEL, + F_CHIP_MODE, + F_EMMC, + F_FAN_TACH, + F_GPIO, + F_HDMI, + F_I2C, + F_I2S, + F_JTAG, + F_DDR_REF_CLK_SEL, + F_LPDDR_REF_CLK, + F_MIPI_CSI, + F_OSC, + F_PCIE, + F_PWM, + F_RGMII, + F_RESET, + F_SATA, + F_SDIO, + F_SPI, + F_S_MODE, + F_UART, + F_USB, + EIC7700_FUNCTIONS_COUNT +}; + +static const char *const eic7700_functions[EIC7700_FUNCTIONS_COUNT] =3D { + [F_DISABLED] =3D "disabled", + [F_BOOT_SEL] =3D "boot_sel", + [F_CHIP_MODE] =3D "chip_mode", + [F_EMMC] =3D "emmc", + [F_FAN_TACH] =3D "fan_tach", + [F_GPIO] =3D "gpio", + [F_HDMI] =3D "hdmi", + [F_I2C] =3D "i2c", + [F_I2S] =3D "i2s", + [F_JTAG] =3D "jtag", + [F_DDR_REF_CLK_SEL] =3D "ddr_ref_clk_sel", + [F_LPDDR_REF_CLK] =3D "lpddr_ref_clk", + [F_MIPI_CSI] =3D "mipi_csi", + [F_OSC] =3D "osc", + [F_PCIE] =3D "pcie", + [F_PWM] =3D "pwm", + [F_RGMII] =3D "rgmii", + [F_RESET] =3D "reset", + [F_SATA] =3D "sata", + [F_SDIO] =3D "sdio", + [F_SPI] =3D "spi", + [F_S_MODE] =3D "s_mode", + [F_UART] =3D "uart", + [F_USB] =3D "usb", +}; + +#define EIC7700_PIN(_number, _name, ...) \ + { \ + .number =3D _number, \ + .name =3D _name, \ + .drv_data =3D (void *)&(static const struct eic7700_pin) { { __VA_ARGS__= } } \ + } + +static const struct pinctrl_pin_desc eic7700_pins[] =3D { + EIC7700_PIN(0, "chip_mode", [0] =3D F_CHIP_MODE), + EIC7700_PIN(1, "mode_set0", [0] =3D F_SDIO, [2] =3D F_GPIO), + EIC7700_PIN(2, "mode_set1", [0] =3D F_SDIO, [2] =3D F_GPIO), + EIC7700_PIN(3, "mode_set2", [0] =3D F_SDIO, [2] =3D F_GPIO), + EIC7700_PIN(4, "mode_set3", [0] =3D F_SDIO, [2] =3D F_GPIO), + EIC7700_PIN(5, "xin", [0] =3D F_OSC), + EIC7700_PIN(6, "rtc_xin", [0] =3D F_DISABLED), + EIC7700_PIN(7, "rst_out_n", [0] =3D F_RESET), + EIC7700_PIN(8, "key_reset_n", [0] =3D F_RESET), + EIC7700_PIN(9, "rst_in_n", [0] =3D F_DISABLED), + EIC7700_PIN(10, "por_in_n", [0] =3D F_DISABLED), + EIC7700_PIN(11, "por_out_n", [0] =3D F_DISABLED), + EIC7700_PIN(12, "gpio0", [0] =3D F_GPIO), + EIC7700_PIN(13, "por_sel", [0] =3D F_RESET), + EIC7700_PIN(14, "jtag0_tck", [0] =3D F_JTAG, [1] =3D F_SPI, [2] =3D F_G= PIO), + EIC7700_PIN(15, "jtag0_tms", [0] =3D F_JTAG, [1] =3D F_SPI, [2] =3D F_G= PIO), + EIC7700_PIN(16, "jtag0_tdi", [0] =3D F_JTAG, [1] =3D F_SPI, [2] =3D F_G= PIO), + EIC7700_PIN(17, "jtag0_tdo", [0] =3D F_JTAG, [1] =3D F_SPI, [2] =3D F_G= PIO), + EIC7700_PIN(18, "gpio5", [0] =3D F_GPIO, [1] =3D F_SPI), + EIC7700_PIN(19, "spi2_cs0_n", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(20, "jtag1_tck", [0] =3D F_JTAG, [2] =3D F_GPIO), + EIC7700_PIN(21, "jtag1_tms", [0] =3D F_JTAG, [2] =3D F_GPIO), + EIC7700_PIN(22, "jtag1_tdi", [0] =3D F_JTAG, [2] =3D F_GPIO), + EIC7700_PIN(23, "jtag1_tdo", [0] =3D F_JTAG, [2] =3D F_GPIO), + EIC7700_PIN(24, "gpio11", [0] =3D F_GPIO), + EIC7700_PIN(25, "spi2_cs1_n", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(26, "pcie_clkreq_n", [0] =3D F_PCIE), + EIC7700_PIN(27, "pcie_wake_n", [0] =3D F_PCIE), + EIC7700_PIN(28, "pcie_perst_n", [0] =3D F_PCIE), + EIC7700_PIN(29, "hdmi_scl", [0] =3D F_HDMI), + EIC7700_PIN(30, "hdmi_sda", [0] =3D F_HDMI), + EIC7700_PIN(31, "hdmi_cec", [0] =3D F_HDMI), + EIC7700_PIN(32, "jtag2_trst", [0] =3D F_JTAG, [2] =3D F_GPIO), + EIC7700_PIN(33, "rgmii0_clk_125", [0] =3D F_RGMII), + EIC7700_PIN(34, "rgmii0_txen", [0] =3D F_RGMII), + EIC7700_PIN(35, "rgmii0_txclk", [0] =3D F_RGMII), + EIC7700_PIN(36, "rgmii0_txd0", [0] =3D F_RGMII), + EIC7700_PIN(37, "rgmii0_txd1", [0] =3D F_RGMII), + EIC7700_PIN(38, "rgmii0_txd2", [0] =3D F_RGMII), + EIC7700_PIN(39, "rgmii0_txd3", [0] =3D F_RGMII), + EIC7700_PIN(40, "i2s0_bclk", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(41, "i2s0_wclk", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(42, "i2s0_sdi", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(43, "i2s0_sdo", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(44, "i2s_mclk", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(45, "rgmii0_rxclk", [0] =3D F_RGMII), + EIC7700_PIN(46, "rgmii0_rxdv", [0] =3D F_RGMII), + EIC7700_PIN(47, "rgmii0_rxd0", [0] =3D F_RGMII), + EIC7700_PIN(48, "rgmii0_rxd1", [0] =3D F_RGMII), + EIC7700_PIN(49, "rgmii0_rxd2", [0] =3D F_RGMII), + EIC7700_PIN(50, "rgmii0_rxd3", [0] =3D F_RGMII), + EIC7700_PIN(51, "i2s2_bclk", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(52, "i2s2_wclk", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(53, "i2s2_sdi", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(54, "i2s2_sdo", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(55, "gpio27", [0] =3D F_GPIO, [1] =3D F_SATA), + EIC7700_PIN(56, "gpio28", [0] =3D F_GPIO), + EIC7700_PIN(57, "gpio29", [0] =3D F_RESET, [1] =3D F_EMMC, [2] =3D F_GP= IO), + EIC7700_PIN(58, "rgmii0_mdc", [0] =3D F_RGMII), + EIC7700_PIN(59, "rgmii0_mdio", [0] =3D F_RGMII), + EIC7700_PIN(60, "rgmii0_intb", [0] =3D F_RGMII), + EIC7700_PIN(61, "rgmii1_clk_125", [0] =3D F_RGMII), + EIC7700_PIN(62, "rgmii1_txen", [0] =3D F_RGMII), + EIC7700_PIN(63, "rgmii1_txclk", [0] =3D F_RGMII), + EIC7700_PIN(64, "rgmii1_txd0", [0] =3D F_RGMII), + EIC7700_PIN(65, "rgmii1_txd1", [0] =3D F_RGMII), + EIC7700_PIN(66, "rgmii1_txd2", [0] =3D F_RGMII), + EIC7700_PIN(67, "rgmii1_txd3", [0] =3D F_RGMII), + EIC7700_PIN(68, "i2s1_bclk", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(69, "i2s1_wclk", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(70, "i2s1_sdi", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(71, "i2s1_sdo", [0] =3D F_I2S, [2] =3D F_GPIO), + EIC7700_PIN(72, "gpio34", [0] =3D F_RESET, [1] =3D F_SDIO, [2] =3D F_GP= IO), + EIC7700_PIN(73, "rgmii1_rxclk", [0] =3D F_RGMII), + EIC7700_PIN(74, "rgmii1_rxdv", [0] =3D F_RGMII), + EIC7700_PIN(75, "rgmii1_rxd0", [0] =3D F_RGMII), + EIC7700_PIN(76, "rgmii1_rxd1", [0] =3D F_RGMII), + EIC7700_PIN(77, "rgmii1_rxd2", [0] =3D F_RGMII), + EIC7700_PIN(78, "rgmii1_rxd3", [0] =3D F_RGMII), + EIC7700_PIN(79, "spi1_cs0_n", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(80, "spi1_clk", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(81, "spi1_d0", [0] =3D F_SPI, [1] =3D F_I2C, [2] =3D F_GPIO,= [3] =3D F_UART), + EIC7700_PIN(82, "spi1_d1", [0] =3D F_SPI, [1] =3D F_I2C, [2] =3D F_GPIO,= [3] =3D F_UART), + EIC7700_PIN(83, "spi1_d2", [0] =3D F_SPI, [1] =3D F_SDIO, [2] =3D F_GPI= O), + EIC7700_PIN(84, "spi1_d3", [0] =3D F_SPI, [1] =3D F_PWM, [2] =3D F_GPIO= ), + EIC7700_PIN(85, "spi1_cs1_n", [0] =3D F_SPI, [1] =3D F_PWM, [2] =3D F_G= PIO), + EIC7700_PIN(86, "rgmii1_mdc", [0] =3D F_RGMII), + EIC7700_PIN(87, "rgmii1_mdio", [0] =3D F_RGMII), + EIC7700_PIN(88, "rgmii1_intb", [0] =3D F_RGMII), + EIC7700_PIN(89, "usb0_pwren", [0] =3D F_USB, [2] =3D F_GPIO), + EIC7700_PIN(90, "usb1_pwren", [0] =3D F_USB, [2] =3D F_GPIO), + EIC7700_PIN(91, "i2c0_scl", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(92, "i2c0_sda", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(93, "i2c1_scl", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(94, "i2c1_sda", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(95, "i2c2_scl", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(96, "i2c2_sda", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(97, "i2c3_scl", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(98, "i2c3_sda", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(99, "i2c4_scl", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(100, "i2c4_sda", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(101, "i2c5_scl", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(102, "i2c5_sda", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(103, "uart0_tx", [0] =3D F_UART, [2] =3D F_GPIO), + EIC7700_PIN(104, "uart0_rx", [0] =3D F_UART, [2] =3D F_GPIO), + EIC7700_PIN(105, "uart1_tx", [0] =3D F_UART, [2] =3D F_GPIO), + EIC7700_PIN(106, "uart1_rx", [0] =3D F_UART, [2] =3D F_GPIO), + EIC7700_PIN(107, "uart1_cts", [0] =3D F_UART, [1] =3D F_I2C, [2] =3D F_G= PIO), + EIC7700_PIN(108, "uart1_rts", [0] =3D F_UART, [1] =3D F_I2C, [2] =3D F_G= PIO), + EIC7700_PIN(109, "uart2_tx", [0] =3D F_UART, [1] =3D F_I2C, [2] =3D F_GP= IO), + EIC7700_PIN(110, "uart2_rx", [0] =3D F_UART, [1] =3D F_I2C, [2] =3D F_GP= IO), + EIC7700_PIN(111, "jtag2_tck", [0] =3D F_JTAG, [2] =3D F_GPIO), + EIC7700_PIN(112, "jtag2_tms", [0] =3D F_JTAG, [2] =3D F_GPIO), + EIC7700_PIN(113, "jtag2_tdi", [0] =3D F_JTAG, [2] =3D F_GPIO), + EIC7700_PIN(114, "jtag2_tdo", [0] =3D F_JTAG, [2] =3D F_GPIO), + EIC7700_PIN(115, "fan_pwm", [0] =3D F_PWM, [2] =3D F_GPIO), + EIC7700_PIN(116, "fan_tach", [0] =3D F_FAN_TACH, [2] =3D F_GPIO), + EIC7700_PIN(117, "mipi_csi0_xvs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(118, "mipi_csi0_xhs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(119, "mipi_csi0_mclk", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(120, "mipi_csi1_xvs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(121, "mipi_csi1_xhs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(122, "mipi_csi1_mclk", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(123, "mipi_csi2_xvs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(124, "mipi_csi2_xhs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(125, "mipi_csi2_mclk", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(126, "mipi_csi3_xvs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(127, "mipi_csi3_xhs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(128, "mipi_csi3_mclk", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(129, "mipi_csi4_xvs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(130, "mipi_csi4_xhs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(131, "mipi_csi4_mclk", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(132, "mipi_csi5_xvs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(133, "mipi_csi5_xhs", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(134, "mipi_csi5_mclk", [0] =3D F_MIPI_CSI, [2] =3D F_GPIO), + EIC7700_PIN(135, "spi3_cs_n", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(136, "spi3_clk", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(137, "spi3_di", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(138, "spi3_do", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(139, "gpio92", [0] =3D F_I2C, [1] =3D F_MIPI_CSI, [2] =3D F_G= PIO, [3] =3D F_UART), + EIC7700_PIN(140, "gpio93", [0] =3D F_I2C, [1] =3D F_MIPI_CSI, [2] =3D F_G= PIO, [3] =3D F_UART), + EIC7700_PIN(141, "s_mode", [0] =3D F_S_MODE, [2] =3D F_GPIO), + EIC7700_PIN(142, "gpio95", [0] =3D F_DDR_REF_CLK_SEL, [2] =3D F_GPIO), + EIC7700_PIN(143, "spi0_cs_n", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(144, "spi0_clk", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(145, "spi0_d0", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(146, "spi0_d1", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(147, "spi0_d2", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(148, "spi0_d3", [0] =3D F_SPI, [2] =3D F_GPIO), + EIC7700_PIN(149, "i2c10_scl", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(150, "i2c10_sda", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(151, "i2c11_scl", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(152, "i2c11_sda", [0] =3D F_I2C, [2] =3D F_GPIO), + EIC7700_PIN(153, "gpio106", [0] =3D F_GPIO), + EIC7700_PIN(154, "boot_sel0", [0] =3D F_BOOT_SEL, [2] =3D F_GPIO), + EIC7700_PIN(155, "boot_sel1", [0] =3D F_BOOT_SEL, [2] =3D F_GPIO), + EIC7700_PIN(156, "boot_sel2", [0] =3D F_BOOT_SEL, [2] =3D F_GPIO), + EIC7700_PIN(157, "boot_sel3", [0] =3D F_BOOT_SEL, [2] =3D F_GPIO), + EIC7700_PIN(158, "gpio111", [0] =3D F_GPIO), + EIC7700_PIN(159, "reserved0", [0] =3D F_DISABLED), + EIC7700_PIN(160, "reserved1", [0] =3D F_DISABLED), + EIC7700_PIN(161, "reserved2", [0] =3D F_DISABLED), + EIC7700_PIN(162, "reserved3", [0] =3D F_DISABLED), + EIC7700_PIN(163, "lpddr_ref_clk", [0] =3D F_LPDDR_REF_CLK), +}; + +static int eic7700_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct eic7700_pinctrl *pc =3D pinctrl_dev_get_drvdata(pctldev); + + return pc->desc.npins; +} + +static const char *eic7700_get_group_name(struct pinctrl_dev *pctldev, uns= igned int selector) +{ + struct eic7700_pinctrl *pc =3D pinctrl_dev_get_drvdata(pctldev); + + return pc->desc.pins[selector].name; +} + +static int eic7700_get_group_pins(struct pinctrl_dev *pctldev, unsigned in= t selector, + const unsigned int **pins, unsigned int *npins) +{ + struct eic7700_pinctrl *pc =3D pinctrl_dev_get_drvdata(pctldev); + + *pins =3D &pc->desc.pins[selector].number; + *npins =3D 1; + + return 0; +} + +static const struct pinctrl_ops eic7700_pinctrl_ops =3D { + .get_groups_count =3D eic7700_get_groups_count, + .get_group_name =3D eic7700_get_group_name, + .get_group_pins =3D eic7700_get_group_pins, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_pin, + .dt_free_map =3D pinconf_generic_dt_free_map, +}; + +static int eic7700_pin_config_get(struct pinctrl_dev *pctldev, unsigned in= t pin, + unsigned long *config) +{ + struct eic7700_pinctrl *pc =3D pinctrl_dev_get_drvdata(pctldev); + const struct eic7700_pin *pin_data =3D pc->desc.pins[pin].drv_data; + u32 arg, value; + int param; + + if (pin_data->functions[0] =3D=3D F_OSC || pin_data->functions[0] =3D=3D = F_DISABLED) + return -EOPNOTSUPP; + + value =3D readl_relaxed(pc->base + EIC7700_PIN_REG(pin)); + + param =3D pinconf_to_config_param(*config); + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg =3D (value & EIC7700_BIAS) =3D=3D 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg =3D (value & EIC7700_BIAS) =3D=3D EIC7700_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg =3D (value & EIC7700_BIAS) =3D=3D EIC7700_PU; + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + if (pin_data->functions[0] =3D=3D F_RGMII || + pin_data->functions[0] =3D=3D F_LPDDR_REF_CLK) + arg =3D FIELD_GET(EIC7700_DS, value) * 3000 + 3000; + else + arg =3D FIELD_GET(EIC7700_DS, value) * 3000 + 6000; + break; + case PIN_CONFIG_INPUT_ENABLE: + arg =3D value & EIC7700_IE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + arg =3D value & EIC7700_ST; + break; + default: + return -EOPNOTSUPP; + } + + *config =3D pinconf_to_config_packed(param, arg); + return arg ? 0 : -EINVAL; +} + +static int eic7700_pin_config_set(struct pinctrl_dev *pctldev, unsigned in= t pin, + unsigned long *configs, unsigned int num_configs) +{ + struct eic7700_pinctrl *pc =3D pinctrl_dev_get_drvdata(pctldev); + const struct eic7700_pin *pin_data =3D pc->desc.pins[pin].drv_data; + u32 value; + + if (pin_data->functions[0] =3D=3D F_OSC || pin_data->functions[0] =3D=3D = F_DISABLED) + return -EOPNOTSUPP; + + value =3D readl_relaxed(pc->base + EIC7700_PIN_REG(pin)); + + for (unsigned int i =3D 0; i < num_configs; i++) { + int param =3D pinconf_to_config_param(configs[i]); + u32 arg =3D pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + value &=3D ~EIC7700_BIAS; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg =3D=3D 0) + return -EOPNOTSUPP; + value &=3D ~EIC7700_BIAS; + value |=3D EIC7700_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg =3D=3D 0) + return -EOPNOTSUPP; + value &=3D ~EIC7700_BIAS; + value |=3D EIC7700_PU; + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + value &=3D ~EIC7700_DS; + if (pin_data->functions[0] =3D=3D F_RGMII || + pin_data->functions[0] =3D=3D F_LPDDR_REF_CLK) { + if (arg < 3000 || arg > 24000) + return -EOPNOTSUPP; + value |=3D FIELD_PREP(EIC7700_DS, (arg - 3000) / 3000); + } else { + if (arg < 6000 || arg > 27000) + return -EOPNOTSUPP; + value |=3D FIELD_PREP(EIC7700_DS, (arg - 6000) / 3000); + } + break; + case PIN_CONFIG_INPUT_ENABLE: + if (arg) + value |=3D EIC7700_IE; + else + value &=3D ~EIC7700_IE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (arg) + value |=3D EIC7700_ST; + else + value &=3D ~EIC7700_ST; + break; + default: + return -EOPNOTSUPP; + } + } + + writel_relaxed(value, pc->base + EIC7700_PIN_REG(pin)); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void eic7700_pin_config_dbg_show(struct pinctrl_dev *pctldev, struc= t seq_file *s, + unsigned int pin) +{ + struct eic7700_pinctrl *pc =3D pinctrl_dev_get_drvdata(pctldev); + u32 value =3D readl_relaxed(pc->base + EIC7700_PIN_REG(pin)) & EIC7700_PI= NCONF; + + seq_printf(s, " [0x%02x]", value); +} +#else +#define eic7700_pin_config_dbg_show NULL +#endif + +static const struct pinconf_ops eic7700_pinconf_ops =3D { + .is_generic =3D true, + .pin_config_get =3D eic7700_pin_config_get, + .pin_config_set =3D eic7700_pin_config_set, + .pin_config_group_get =3D eic7700_pin_config_get, + .pin_config_group_set =3D eic7700_pin_config_set, + .pin_config_dbg_show =3D eic7700_pin_config_dbg_show, + .pin_config_group_dbg_show =3D eic7700_pin_config_dbg_show, +}; + +static int eic7700_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct eic7700_pinctrl *pc =3D pinctrl_dev_get_drvdata(pctldev); + + return pc->functions_count; +} + +static const char *eic7700_get_function_name(struct pinctrl_dev *pctldev, = unsigned int selector) +{ + struct eic7700_pinctrl *pc =3D pinctrl_dev_get_drvdata(pctldev); + + return pc->functions[selector].name; +} + +static int eic7700_get_function_groups(struct pinctrl_dev *pctldev, unsign= ed int selector, + const char *const **groups, unsigned int *num_groups) +{ + struct eic7700_pinctrl *pc =3D pinctrl_dev_get_drvdata(pctldev); + + *groups =3D pc->functions[selector].groups; + *num_groups =3D pc->functions[selector].ngroups; + + return 0; +} + +static int eic7700_set_mux(struct pinctrl_dev *pctldev, unsigned int func_= selector, + unsigned int group_selector) +{ + struct eic7700_pinctrl *pc =3D pinctrl_dev_get_drvdata(pctldev); + const struct eic7700_pin *pin_data =3D pc->desc.pins[group_selector].drv_= data; + u32 fs, value; + + if (pin_data->functions[0] =3D=3D F_OSC || pin_data->functions[0] =3D=3D = F_DISABLED) + return -EOPNOTSUPP; + + for (fs =3D 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++) + if (pin_data->functions[fs] =3D=3D func_selector) + break; + + if (fs =3D=3D EIC7700_FUNCTIONS_PER_PIN) { + dev_err(pctldev->dev, "invalid mux %s for pin %s\n", + pc->functions[func_selector].name, + pc->desc.pins[group_selector].name); + return -EINVAL; + } + + value =3D readl_relaxed(pc->base + EIC7700_PIN_REG(group_selector)); + value &=3D ~EIC7700_FUNC_SEL; + value |=3D FIELD_PREP(EIC7700_FUNC_SEL, fs); + writel_relaxed(value, pc->base + EIC7700_PIN_REG(group_selector)); + + return 0; +} + +static int eic7700_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned int offset) +{ + return eic7700_set_mux(pctldev, F_GPIO, offset); +} + +static void eic7700_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned int offset) +{ + eic7700_set_mux(pctldev, F_DISABLED, offset); +} + +static int eic7700_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned int offset, + bool input) +{ + struct eic7700_pinctrl *pc =3D pinctrl_dev_get_drvdata(pctldev); + u32 value; + + value =3D readl_relaxed(pc->base + EIC7700_PIN_REG(offset)); + if (input) + value |=3D EIC7700_IE; + else + value &=3D ~EIC7700_IE; + writel_relaxed(value, pc->base + EIC7700_PIN_REG(offset)); + + return 0; +} + +static const struct pinmux_ops eic7700_pinmux_ops =3D { + .get_functions_count =3D eic7700_get_functions_count, + .get_function_name =3D eic7700_get_function_name, + .get_function_groups =3D eic7700_get_function_groups, + .set_mux =3D eic7700_set_mux, + .gpio_request_enable =3D eic7700_gpio_request_enable, + .gpio_disable_free =3D eic7700_gpio_disable_free, + .gpio_set_direction =3D eic7700_gpio_set_direction, + .strict =3D true, +}; + +static int eic7700_pinctrl_init_function_groups(struct device *dev, struct= eic7700_pinctrl *pc, + const char *const *function_names) +{ + unsigned int ngroups =3D 0; + const char **groups; + + /* Count the number of groups for each function */ + for (unsigned int pin =3D 0; pin < pc->desc.npins; pin++) { + const struct eic7700_pin *pin_data =3D pc->desc.pins[pin].drv_data; + bool found_disabled =3D false; + + for (unsigned int fs =3D 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++) { + unsigned int selector =3D pin_data->functions[fs]; + struct pinfunction *function =3D &pc->functions[selector]; + + /* Only count F_DISABLED once per pin */ + if (selector =3D=3D F_DISABLED) { + if (found_disabled) + continue; + found_disabled =3D true; + } + + function->ngroups++; + ngroups++; + } + } + + groups =3D devm_kcalloc(dev, ngroups, sizeof(*groups), GFP_KERNEL); + if (!groups) + return -ENOMEM; + + for (unsigned int selector =3D 0; selector < pc->functions_count; selecto= r++) { + struct pinfunction *function =3D &pc->functions[selector]; + + function->name =3D function_names[selector]; + function->groups =3D groups; + groups +=3D function->ngroups; + + /* Reset per-function ngroups for use as iterator below */ + function->ngroups =3D 0; + } + + /* Fill in the group pointers for each function */ + for (unsigned int pin =3D 0; pin < pc->desc.npins; pin++) { + const struct pinctrl_pin_desc *desc =3D &pc->desc.pins[pin]; + const struct eic7700_pin *pin_data =3D desc->drv_data; + bool found_disabled =3D false; + + for (unsigned int fs =3D 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++) { + unsigned int selector =3D pin_data->functions[fs]; + struct pinfunction *function =3D &pc->functions[selector]; + + /* Only count F_DISABLED once per pin */ + if (selector =3D=3D F_DISABLED) { + if (found_disabled) + continue; + found_disabled =3D true; + } + + ((const char **)function->groups)[function->ngroups++] =3D desc->name; + } + } + + return 0; +} + +static int eic7700_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pinctrl_dev *pctldev; + struct eic7700_pinctrl *pc; + struct regulator *regulator; + u32 voltage, rgmii0_mode, rgmii1_mode; + int ret; + + pc =3D devm_kzalloc(dev, struct_size(pc, functions, EIC7700_FUNCTIONS_COU= NT), GFP_KERNEL); + if (!pc) + return -ENOMEM; + + pc->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pc->base)) + return PTR_ERR(pc->base); + + regulator =3D devm_regulator_get(dev, "vrgmii"); + if (IS_ERR_OR_NULL(regulator)) { + dev_err(dev, "failed to get vrgmii regulator!\n"); + return -ENODEV; + } + + voltage =3D regulator_get_voltage(regulator); + if (voltage < 0) { + dev_err(&pdev->dev, "Failed to get voltage from regulator\n"); + return voltage; + } + + rgmii0_mode =3D readl_relaxed(pc->base + EIC7700_RGMII0_SEL_MODE); + rgmii1_mode =3D readl_relaxed(pc->base + EIC7700_RGMII1_SEL_MODE); + rgmii0_mode &=3D ~EIC7700_MS; + rgmii1_mode &=3D ~EIC7700_MS; + if (voltage =3D=3D 1800000) { + rgmii0_mode |=3D FIELD_PREP(EIC7700_MS, EIC7700_MS_1V8); + rgmii1_mode |=3D FIELD_PREP(EIC7700_MS, EIC7700_MS_1V8); + } else if (voltage =3D=3D 3300000) { + rgmii0_mode |=3D FIELD_PREP(EIC7700_MS, EIC7700_MS_3V3); + rgmii1_mode |=3D FIELD_PREP(EIC7700_MS, EIC7700_MS_3V3); + } else { + dev_err(&pdev->dev, "Invalid voltage configuration, should be either 1.8= V or 3.3V\n"); + } + + writel_relaxed(rgmii0_mode, pc->base + EIC7700_RGMII0_SEL_MODE); + writel_relaxed(rgmii1_mode, pc->base + EIC7700_RGMII1_SEL_MODE); + + pc->desc.name =3D dev_name(dev); + pc->desc.pins =3D eic7700_pins; + pc->desc.npins =3D ARRAY_SIZE(eic7700_pins); + pc->desc.pctlops =3D &eic7700_pinctrl_ops; + pc->desc.pmxops =3D &eic7700_pinmux_ops; + pc->desc.confops =3D &eic7700_pinconf_ops; + pc->desc.owner =3D THIS_MODULE; + + pc->functions_count =3D EIC7700_FUNCTIONS_COUNT; + ret =3D eic7700_pinctrl_init_function_groups(dev, pc, eic7700_functions); + if (ret) + return ret; + + ret =3D devm_pinctrl_register_and_init(dev, &pc->desc, pc, &pctldev); + if (ret) + return dev_err_probe(dev, ret, "could not register pinctrl driver\n"); + + return pinctrl_enable(pctldev); +} + +static const struct of_device_id eic7700_pinctrl_of_match[] =3D { + { .compatible =3D "eswin,eic7700-pinctrl" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, eic7700_pinctrl_of_match); + +static struct platform_driver eic7700_pinctrl_driver =3D { + .probe =3D eic7700_pinctrl_probe, + .driver =3D { + .name =3D "pinctrl-eic7700", + .of_match_table =3D eic7700_pinctrl_of_match, + }, +}; +module_platform_driver(eic7700_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for the ESWIN EIC7700 SoC"); +MODULE_AUTHOR("Samuel Holland "); +MODULE_AUTHOR("Yulin Lu "); +MODULE_LICENSE("GPL"); --=20 2.25.1