From nobody Tue Dec 16 23:11:58 2025 Received: from mail-m1973172.qiye.163.com (mail-m1973172.qiye.163.com [220.197.31.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B93F127D77F for ; Tue, 6 May 2025 12:00:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746532839; cv=none; b=g3d7Bm44FK5c2sUEpdCqGRGz4xBFK3PscCbb9T+D+pfmL1k5FzO6e6wxD5yVKlGWBOXrnMZH4XQOWbPv2Utlva0+QBx/h/iPQJuWBAercVZnKY9X9ttIw3biNhKT31cTveDRLkTyRfMDC7XRwtAzA+GJ1YOWQwEV0QzOyMM8jMQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746532839; c=relaxed/simple; bh=H3nSmQofOPbyGH9/LAxyApDbeSy3bZQ2QhgMQtZHcJY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ec+GSUwkgTCyqlemRstuyiYhJcrpXbYkUOWN8kpdwO6z8JtOJ5eO/gK+fqboJOyBqn+bz8NQtzDWzo9+Wo0Y6wI3rkfxKXUoPVrIU7/xARdiyH543cLxrhNE0DJdujTYpIU0bfk0n1OUaiQOPkdtDAEtI0FAnfMCdM9StIUwLto= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=POqrcbhW; arc=none smtp.client-ip=220.197.31.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="POqrcbhW" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 140c6eaec; Tue, 6 May 2025 10:57:22 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Rob Herring , Guenter Roeck , Jamie Iles , linux-watchdog@vger.kernel.org, Wim Van Sebroeck , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, Conor Dooley Subject: [PATCH v5 1/6] dt-bindings: watchdog: Add rk3562 compatible Date: Tue, 6 May 2025 10:57:10 +0800 Message-Id: <20250506025715.33595-2-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250506025715.33595-1-kever.yang@rock-chips.com> References: <20250506025715.33595-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQx8ZGFZKTUpMGExIQkxCGBpWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a96a386ca9703afkunm140c6eaec X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mww6Dxw6ETJRCRE6Ij4jMD8e DylPCklVSlVKTE9NTktLSU9IT0xLVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFJS0tLNwY+ DKIM-Signature: a=rsa-sha256; b=POqrcbhWPq/szZJhg5FtRNV3pU+U2EtZcabw4xkutZdrqY2EVN8+tAxVgIV8WfvIdK+G3YrIqKoFsJ8WYBc3Dhxq4sw/CZVQngIhJgHw/B8ZqwBqhC/v6Vapz3g6N5u7t0XuARFArD1RTUCDz3YHiXE5rgltCybZ8pTikKBnmZw=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=1taHNHL+bdAlejzIloZs57RLJBN6GLNLvJDGZdKJmkI=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add rockchip,rk3562-wdt for rk3562. Signed-off-by: Kever Yang Reviewed-by: Heiko Stuebner Acked-by: Rob Herring (Arm) Reviewed-by: Guenter Roeck --- Changes in v5: - Collect review tag Changes in v4: - Collect ack tag Changes in v3: - Collect reveiw tag Changes in v2: None Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml b/= Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml index 1efefd741c06..ef088e0f6917 100644 --- a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml @@ -28,6 +28,7 @@ properties: - rockchip,rk3328-wdt - rockchip,rk3368-wdt - rockchip,rk3399-wdt + - rockchip,rk3562-wdt - rockchip,rk3568-wdt - rockchip,rk3576-wdt - rockchip,rk3588-wdt --=20 2.25.1 From nobody Tue Dec 16 23:11:58 2025 Received: from mail-m1973189.qiye.163.com (mail-m1973189.qiye.163.com [220.197.31.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FF292033A for ; Tue, 6 May 2025 07:33:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746516815; cv=none; b=RYSG7uxgUguOPLiZ4pGNY6zE0Ay+VFzS9Yjv6tXang9YrRzemns3j7nbkG+kN/ZABQpola3zdzZIIJv5nj6wYcikmzrVGu7JRCUpcWhBzL3HU0LlF1v5IM2Bx6NTQnvg6mOkq7k9rUtWNpsvY1g7yxSv9pXnPXai5amvPpAVMao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746516815; c=relaxed/simple; bh=nTnT41H56NFfzfwDP6sYaJgsbM+rIFepGMFg3dvWngE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S9353fq9/iR+O18sxUvuBUasYYSf6b5l3/lvseKqxNRsNWWBpf8P2YMm5tMCypaT7GFcAmlf1GtocHb7Y4NwV33ebkCh8xod3mRpV9oUhMv4f9L+n5UzHY35H//Gw6SRxCZ3q1zuYUmaOTNzlAjNdXP3Kq1pr/mXrRWAG+bodGQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=guFMkTP0; arc=none smtp.client-ip=220.197.31.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="guFMkTP0" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 140c6eaf2; Tue, 6 May 2025 10:57:23 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Rob Herring , devicetree@vger.kernel.org, Conor Dooley , Detlev Casanova , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Elaine Zhang , linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 2/6] dt-bindings: rockchip: pmu: Add rk3562 compatible Date: Tue, 6 May 2025 10:57:11 +0800 Message-Id: <20250506025715.33595-3-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250506025715.33595-1-kever.yang@rock-chips.com> References: <20250506025715.33595-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGh5DT1YYHh1DQx5LSEwaGUJWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a96a386d0b703afkunm140c6eaf2 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NxQ6Ghw6FzJJDREpMjMNMDAv PzcKFEpVSlVKTE9NTktLSU9PQkhLVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFJS0NKNwY+ DKIM-Signature: a=rsa-sha256; b=guFMkTP0qNBxhrij+lmM2saCCfyqO7SwolRAgPKvg+uY3pdb45tYo65itycGNdj+h/8n+ruBSRZqhnQoxguoDRFV14rOEGUeujKyjGMVmOhWfrBfBqRnnzt5Wvbs6JghHnJQRcreCHD85kUdBWnqDVr/PPMo+Vbi8gNo3NlnfGU=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=LJ5LDuPoTNaHftITtU0a6AsO3YQBapk7pI5GMnaJ3Io=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add the compatible for the pmu mfd on rk3562. Signed-off-by: Kever Yang Acked-by: Rob Herring (Arm) --- Changes in v5: None Changes in v4: - Collect ack tag Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/arm/rockchip/pmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Docu= mentation/devicetree/bindings/arm/rockchip/pmu.yaml index 52016a141227..46c1af851be7 100644 --- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml @@ -25,6 +25,7 @@ select: - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu + - rockchip,rk3562-pmu - rockchip,rk3568-pmu - rockchip,rk3576-pmu - rockchip,rk3588-pmu @@ -43,6 +44,7 @@ properties: - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu + - rockchip,rk3562-pmu - rockchip,rk3568-pmu - rockchip,rk3576-pmu - rockchip,rk3588-pmu --=20 2.25.1 From nobody Tue Dec 16 23:11:58 2025 Received: from mail-m82174.xmail.ntesmail.com (mail-m82174.xmail.ntesmail.com [156.224.82.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D934C29ACF5; Tue, 6 May 2025 04:13:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.224.82.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746504787; cv=none; b=nxKiBIG7+qwBjIwnmQ0eIbH4rGlrk8fjvPAzMUQ3nlJ1EpbsXPvlVdJbXz/t8NVkyuIZh9ShS17uVlYANxsSU+nURU0mfsQaCj98Lp/NYeh9AgoZRlsJ93UuYgRCakLsn2UANptBkcDdMFhDX7c+daViozydO0HAWqXl/b9M4Rk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746504787; c=relaxed/simple; bh=uDVf/saMy4+Z9R9ojM5P/eQj0EB4phsLM7i+B38h2iE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cSQL6vrO/xuEZTzLFXeVZieg+jdeEt9QkmYnIlsN7IRwkpw6Dp8BcWNFylx77QMUiT4YpGRmCOK/jfO6nW2dpCDCKowFqWSH4mHF+QOMXjYb6Rcl/QenbMNva9d4kreEy3DqF4nU+yOJQeNdrZyP/BXhABdtgQe2XakJB2Lv+1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=EwQtZEg/; arc=none smtp.client-ip=156.224.82.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="EwQtZEg/" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 140c6eaf9; Tue, 6 May 2025 10:57:25 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Rob Herring , devicetree@vger.kernel.org, Jonas Karlman , Frank Wang , linux-kernel@vger.kernel.org, Detlev Casanova , Yao Zi , Conor Dooley , Shresth Prasad , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, Cristian Ciocaltea Subject: [PATCH v5 3/6] dt-bindings: soc: rockchip: Add rk3562 syscon compatibles Date: Tue, 6 May 2025 10:57:12 +0800 Message-Id: <20250506025715.33595-4-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250506025715.33595-1-kever.yang@rock-chips.com> References: <20250506025715.33595-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQk5NHVYYHU1MQ0hKQkkfGUNWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpKQk 1VSktLVUpCWQY+ X-HM-Tid: 0a96a386d66c03afkunm140c6eaf9 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Pwg6FCo4VjJRNxEtIjMJMD8d HC4aCTVVSlVKTE9NTktLSU9NTUtPVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFJTkNPNwY+ DKIM-Signature: a=rsa-sha256; b=EwQtZEg/JcR9X1aI3qN+lcZB8BLJGZzmogevqtBCXYTMSJ0LbLAJFcjnWqQPESUH3kmNkI/EZAUbcKEte4FPiuE3Uah8VQA0K+JXK1YYyEVymbNOlBJXzC3uVUT3d0nhvqtFSGkPKwp/C6M/TbKL86Pux1ebE1NWBWMr2fCR+ks=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=z6yuuAP3upQvCqHVAexjgMB4cGshHYyvgpiH/jTzsjM=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add all syscon compatibles for rk3562. Signed-off-by: Kever Yang Acked-by: Rob Herring (Arm) --- Changes in v5: None Changes in v4: - Collect ack tag Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Docu= mentation/devicetree/bindings/soc/rockchip/grf.yaml index 2f61c1b95fea..8cbf5b6772dd 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -18,6 +18,12 @@ properties: - rockchip,rk3528-ioc-grf - rockchip,rk3528-vo-grf - rockchip,rk3528-vpu-grf + - rockchip,rk3562-ioc-grf + - rockchip,rk3562-peri-grf + - rockchip,rk3562-pipephy-grf + - rockchip,rk3562-pmu-grf + - rockchip,rk3562-sys-grf + - rockchip,rk3562-usbphy-grf - rockchip,rk3566-pipe-grf - rockchip,rk3568-pcie3-phy-grf - rockchip,rk3568-pipe-grf @@ -82,6 +88,7 @@ properties: - rockchip,rk3368-pmugrf - rockchip,rk3399-grf - rockchip,rk3399-pmugrf + - rockchip,rk3562-pmu-grf - rockchip,rk3568-grf - rockchip,rk3568-pmugrf - rockchip,rk3576-ioc-grf --=20 2.25.1 From nobody Tue Dec 16 23:11:58 2025 Received: from mail-m1973175.qiye.163.com (mail-m1973175.qiye.163.com [220.197.31.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 906E127D783 for ; Tue, 6 May 2025 12:00:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.75 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746532840; cv=none; b=rerCx5dnqwdIpWK+EizYAmcAOdBTB/E3vlP5tc02w/PoO5u1aJBCpINTecpOegVZvnlSmRnonps7nf5CR7z1RFOtlkLG4BP43oLy+wjtydPfTv4BvIgojbjB/HaXQ1zyZIgA3IIYzDOeJkv2zj9kzTKHjtfDynnkG/1yPFsFMEs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746532840; c=relaxed/simple; bh=M3fVY4JE2ssndMcikKNz5jtjaTmrLNSAo94gMUm4VSY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Va1bzRag5Ep+8Iy+FhuEYkuw3P1nFjRMNITEZT6qdm5T6G5HSk1LC6+OL/fwPch1ILDTAykpCqsSkcMz3B82CQNVSPHdYZvE9gUabBMaMPCev0Bt0q5jmgDOJkLiZbyaPh3TbQ1ne+pIf4/NbM6PebETT7XhxXTGTJx7cjz4D54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=ibLWCwO+; arc=none smtp.client-ip=220.197.31.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="ibLWCwO+" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 140c6eb04; Tue, 6 May 2025 10:57:26 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Krzysztof Kozlowski , devicetree@vger.kernel.org, Jonas Karlman , Junhao Xie , Rob Herring , Detlev Casanova , Conor Dooley , Jimmy Hon , linux-kernel@vger.kernel.org, Marcin Juszkiewicz , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 4/6] dt-bindings: arm: rockchip: Add rk3562 evb2 board Date: Tue, 6 May 2025 10:57:13 +0800 Message-Id: <20250506025715.33595-5-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250506025715.33595-1-kever.yang@rock-chips.com> References: <20250506025715.33595-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQx1IHlZKHkweHRpMSEpCGElWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE 5VSktLVUpCS0tZBg++ X-HM-Tid: 0a96a386dcf703afkunm140c6eb04 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MTY6Mjo5FjJIMxE#ST0xMC8I LBIKFBFVSlVKTE9NTktLSU9DSE5NVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFJSkxNNwY+ DKIM-Signature: a=rsa-sha256; b=ibLWCwO+DvQPJ54po1wn0YdKD1BIipl6ONpjcncz9hdT1nV10V5c069xTyL9AZJflIUti0rqLIyzf86BTLyeprgyqweb4rVAQu8VW3qrPIa1wlA/MX+IqO5l9woKWQtOk3X+frsIwrprpRRCzwCLMuUeabHX1bY38BFHp759H5A=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=jL/nquXJOtsyOHwId91Jt8y1FMZRc7Fx/1tni3T25FY=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree documentation for rk3562-evb2-v10. Signed-off-by: Kever Yang Acked-by: Krzysztof Kozlowski --- Changes in v5: None Changes in v4: None Changes in v3: - Collect the Acked-by tag Changes in v2: - Update in sort order Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 455fbb290b77..3372aff63e4d 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1057,6 +1057,11 @@ properties: - const: rockchip,rk3399-sapphire-excavator - const: rockchip,rk3399 =20 + - description: Rockchip RK3562 Evaluation board 2 + items: + - const: rockchip,rk3562-evb2-v10 + - const: rockchip,rk3562 + - description: Rockchip RK3566 BOX Evaluation Demo board items: - const: rockchip,rk3566-box-demo --=20 2.25.1 From nobody Tue Dec 16 23:11:58 2025 Received: from mail-m19731105.qiye.163.com (mail-m19731105.qiye.163.com [220.197.31.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B9B331A0CF; Tue, 6 May 2025 03:12:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746501181; cv=none; b=Vg1PKZncfuYXnbA3LOVuqYmVweO0a9P7f87GVNv7G6jBuaCcraeCqeiu6NxLmMTS5KMBKpvmq4WsKLmh16zuPD5FCqe+BrFgVRl4TF8LfCoLb89aXX68nAmkasd4V33TPZnlsNz28zSikA2tnGPer3Msi0VMviVQPNnGEJlwhBc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746501181; c=relaxed/simple; bh=anbNopejwLK3RckU/nW8DCkV6vY43zkmY2Y01B0sei4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=imvUbEIZUMh0PNSD0Bt0+NAWSo/PBGhJc/sstVqPt0HrYnRD3SJPiIJ0QWcRKOqdWZpBYwB+InRn+5dvOZawnLyRGfP/gazFPCdn7xCu5fJVpzteAzFJuftW/qlRw0496g2GzDIj19VoLM9fQFROblxZVWZG3sfsJ/OLJrUcM88= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=TSnIMbad; arc=none smtp.client-ip=220.197.31.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="TSnIMbad" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 140c6eb14; Tue, 6 May 2025 10:57:28 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Finley Xiao , Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 5/6] arm64: dts: rockchip: add core dtsi for RK3562 SoC Date: Tue, 6 May 2025 10:57:14 +0800 Message-Id: <20250506025715.33595-6-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250506025715.33595-1-kever.yang@rock-chips.com> References: <20250506025715.33595-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQxkZGlYaSUlNH0weSE5DH0xWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a96a386e3c803afkunm140c6eb14 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PTY6Sjo*EzIBCRFIFD4DMCgD P0pPCklVSlVKTE9NTktLSU9CQkxLVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFCSExNQzcG DKIM-Signature: a=rsa-sha256; b=TSnIMbad3WczILS5vmtITQeN6vNrSRaaIDX+bgXpnXbHaMsTzuFMASA+XAbMGmOCkFEUyD5TFM3PDv7BbqDOq6F0RHnMexncTvoEjXC5ZDteOc2F1zyJkLoFZWJW9RcI28l754/Ad1+SHgOTJwMCMSCrfcXeSxLECphpPG5kRhQ=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=8C4y0J9Lr4D6COr7CIRNXkPCW/YPoFQC9fLLysS+QuQ=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" From: Finley Xiao RK3562 is a SoC from Rockchip, which embedded with quad ARM Cortex-A53. Signed-off-by: Finley Xiao Signed-off-by: Kever Yang --- Changes in v5: - Update scmi-shmem from soc to reserved memory Changes in v4: - remove gmac and otp nodes Changes in v3: - remove i2c/serial/spi alias - add soc node Changes in v2: - remove grf in cru - Update some properties order .../boot/dts/rockchip/rk3562-pinctrl.dtsi | 2352 +++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3562.dtsi | 1270 +++++++++ 2 files changed, 3622 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi b/arch/arm64/= boot/dts/rockchip/rk3562-pinctrl.dtsi new file mode 100644 index 000000000000..b311448d77a3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi @@ -0,0 +1,2352 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + cam { + /omit-if-no-ref/ + camm0_clk0_out: camm0-clk0-out { + rockchip,pins =3D + /* camm0_clk0_out */ + <3 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm0_clk1_out: camm0-clk1-out { + rockchip,pins =3D + /* camm0_clk1_out */ + <3 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm1_clk0_out: camm1-clk0-out { + rockchip,pins =3D + /* camm1_clk0_out */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm1_clk1_out: camm1-clk1-out { + rockchip,pins =3D + /* camm1_clk1_out */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clk2_out: cam-clk2-out { + rockchip,pins =3D + /* cam_clk2_out */ + <3 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clk3_out: cam-clk3-out { + rockchip,pins =3D + /* cam_clk3_out */ + <3 RK_PB5 2 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins =3D + /* can0_rx_m0 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* can0_tx_m0 */ + <3 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins =3D + /* can0_rx_m1 */ + <3 RK_PB7 6 &pcfg_pull_none>, + /* can0_tx_m1 */ + <3 RK_PB6 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m2_pins: can0m2-pins { + rockchip,pins =3D + /* can0_rx_m2 */ + <0 RK_PC7 2 &pcfg_pull_none>, + /* can0_tx_m2 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins =3D + /* can1_rx_m0 */ + <1 RK_PB7 4 &pcfg_pull_none>, + /* can1_tx_m0 */ + <1 RK_PC0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins =3D + /* can1_rx_m1 */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* can1_tx_m1 */ + <0 RK_PC0 4 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clk_32k_in: clk-32k-in { + rockchip,pins =3D + /* clk_32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + clk0 { + /omit-if-no-ref/ + clk0_32k_out: clk0-32k-out { + rockchip,pins =3D + /* clk0_32k_out */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + clk1 { + /omit-if-no-ref/ + clk1_32k_out: clk1-32k-out { + rockchip,pins =3D + /* clk1_32k_out */ + <2 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins =3D + /* cpu_avs */ + <0 RK_PB7 3 &pcfg_pull_none>; + }; + }; + + dsm { + /omit-if-no-ref/ + dsm_pins: dsm-pins { + rockchip,pins =3D + /* dsm_aud_ln */ + <1 RK_PB4 5 &pcfg_pull_none>, + /* dsm_aud_lp */ + <1 RK_PB3 5 &pcfg_pull_none>, + /* dsm_aud_rn */ + <1 RK_PB6 6 &pcfg_pull_none>, + /* dsm_aud_rp */ + <1 RK_PB5 6 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins =3D + /* emmc_d0 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins =3D + /* emmc_clk */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins =3D + /* emmc_cmd */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_strb: emmc-strb { + rockchip,pins =3D + /* emmc_strb */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + eth { + /omit-if-no-ref/ + ethm0_pins: ethm0-pins { + rockchip,pins =3D + /* eth_clk_25m_out_m0 */ + <4 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ethm1_pins: ethm1-pins { + rockchip,pins =3D + /* eth_clk_25m_out_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins =3D + /* fspi_clk */ + <1 RK_PB1 2 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PA0 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PA1 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PA2 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_csn0: fspi-csn0 { + rockchip,pins =3D + /* fspi_csn0 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + fspi_csn1: fspi-csn1 { + rockchip,pins =3D + /* fspi_csn1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins =3D + /* gpu_avs */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins =3D + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins =3D + /* i2c1_scl_m0 */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins =3D + /* i2c1_scl_m1 */ + <4 RK_PB4 5 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <4 RK_PB5 5 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins =3D + /* i2c2_scl_m0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins =3D + /* i2c2_scl_m1 */ + <3 RK_PD2 5 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <3 RK_PD3 5 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins =3D + /* i2c3_scl_m0 */ + <3 RK_PA0 1 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <3 RK_PA1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins =3D + /* i2c3_scl_m1 */ + <4 RK_PA5 5 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <4 RK_PA6 5 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins =3D + /* i2c4_scl_m0 */ + <3 RK_PB6 5 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <3 RK_PB7 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins =3D + /* i2c4_scl_m1 */ + <0 RK_PA5 2 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <0 RK_PA4 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins =3D + /* i2c5_scl_m0 */ + <3 RK_PC2 1 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <3 RK_PC3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins =3D + /* i2c5_scl_m1 */ + <1 RK_PC7 4 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <1 RK_PD0 4 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0m0_lrck: i2s0m0-lrck { + rockchip,pins =3D + /* i2s0_lrck_m0 */ + <3 RK_PA4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_mclk: i2s0m0-mclk { + rockchip,pins =3D + /* i2s0_mclk_m0 */ + <3 RK_PA2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sclk: i2s0m0-sclk { + rockchip,pins =3D + /* i2s0_sclk_m0 */ + <3 RK_PA3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi0: i2s0m0-sdi0 { + rockchip,pins =3D + /* i2s0_sdi0_m0 */ + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi1: i2s0m0-sdi1 { + rockchip,pins =3D + /* i2s0_sdi1_m0 */ + <3 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi2: i2s0m0-sdi2 { + rockchip,pins =3D + /* i2s0_sdi2_m0 */ + <3 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi3: i2s0m0-sdi3 { + rockchip,pins =3D + /* i2s0_sdi3_m0 */ + <3 RK_PA6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo0: i2s0m0-sdo0 { + rockchip,pins =3D + /* i2s0_sdo0_m0 */ + <3 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo1: i2s0m0-sdo1 { + rockchip,pins =3D + /* i2s0_sdo1_m0 */ + <3 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo2: i2s0m0-sdo2 { + rockchip,pins =3D + /* i2s0_sdo2_m0 */ + <3 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo3: i2s0m0-sdo3 { + rockchip,pins =3D + /* i2s0_sdo3_m0 */ + <3 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_lrck: i2s0m1-lrck { + rockchip,pins =3D + /* i2s0_lrck_m1 */ + <1 RK_PC4 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_mclk: i2s0m1-mclk { + rockchip,pins =3D + /* i2s0_mclk_m1 */ + <1 RK_PC6 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sclk: i2s0m1-sclk { + rockchip,pins =3D + /* i2s0_sclk_m1 */ + <1 RK_PC5 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi0: i2s0m1-sdi0 { + rockchip,pins =3D + /* i2s0_sdi0_m1 */ + <1 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi1: i2s0m1-sdi1 { + rockchip,pins =3D + /* i2s0_sdi1_m1 */ + <1 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi2: i2s0m1-sdi2 { + rockchip,pins =3D + /* i2s0_sdi2_m1 */ + <1 RK_PD3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi3: i2s0m1-sdi3 { + rockchip,pins =3D + /* i2s0_sdi3_m1 */ + <1 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo0: i2s0m1-sdo0 { + rockchip,pins =3D + /* i2s0_sdo0_m1 */ + <1 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo1: i2s0m1-sdo1 { + rockchip,pins =3D + /* i2s0_sdo1_m1 */ + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo2: i2s0m1-sdo2 { + rockchip,pins =3D + /* i2s0_sdo2_m1 */ + <1 RK_PD2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo3: i2s0m1-sdo3 { + rockchip,pins =3D + /* i2s0_sdo3_m1 */ + <2 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins =3D + /* i2s1_lrck_m0 */ + <3 RK_PC6 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins =3D + /* i2s1_mclk_m0 */ + <3 RK_PC4 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins =3D + /* i2s1_sclk_m0 */ + <3 RK_PC5 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins =3D + /* i2s1_sdi0_m0 */ + <3 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins =3D + /* i2s1_sdi1_m0 */ + <3 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins =3D + /* i2s1_sdi2_m0 */ + <3 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins =3D + /* i2s1_sdi3_m0 */ + <3 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins =3D + /* i2s1_sdo0_m0 */ + <3 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins =3D + /* i2s1_sdo1_m0 */ + <4 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins =3D + /* i2s1_sdo2_m0 */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins =3D + /* i2s1_sdo3_m0 */ + <4 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins =3D + /* i2s1_lrck_m1 */ + <3 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins =3D + /* i2s1_mclk_m1 */ + <3 RK_PB2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins =3D + /* i2s1_sclk_m1 */ + <3 RK_PB3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins =3D + /* i2s1_sdi0_m1 */ + <3 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins =3D + /* i2s1_sdi1_m1 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins =3D + /* i2s1_sdi2_m1 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins =3D + /* i2s1_sdi3_m1 */ + <3 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins =3D + /* i2s1_sdo0_m1 */ + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins =3D + /* i2s1_sdo1_m1 */ + <3 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins =3D + /* i2s1_sdo2_m1 */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins =3D + /* i2s1_sdo3_m1 */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins =3D + /* i2s2_lrck_m0 */ + <1 RK_PD6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins =3D + /* i2s2_mclk_m0 */ + <2 RK_PA1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins =3D + /* i2s2_sclk_m0 */ + <1 RK_PD5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins =3D + /* i2s2_sdi_m0 */ + <2 RK_PA0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins =3D + /* i2s2_sdo_m0 */ + <1 RK_PD7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins =3D + /* i2s2_lrck_m1 */ + <4 RK_PA1 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins =3D + /* i2s2_mclk_m1 */ + <3 RK_PD6 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins =3D + /* i2s2_sclk_m1 */ + <4 RK_PB1 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins =3D + /* i2s2_sdi_m1 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins =3D + /* i2s2_sdo_m1 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins =3D + /* isp_flash_trigin */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* isp_flash_trigout */ + <3 RK_PC3 2 &pcfg_pull_none>, + /* isp_prelight_trigout */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins =3D + /* jtag_cpu_mcu_tck_m0 */ + <0 RK_PD1 2 &pcfg_pull_none>, + /* jtag_cpu_mcu_tms_m0 */ + <0 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins =3D + /* jtag_cpu_mcu_tck_m1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* jtag_cpu_mcu_tms_m1 */ + <1 RK_PB6 2 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins =3D + /* npu_avs */ + <0 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins =3D + /* pcie20_clkreqn_m0 */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* pcie20_perstn_m0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* pcie20_waken_m0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins =3D + /* pcie20_clkreqn_m1 */ + <3 RK_PA6 4 &pcfg_pull_none>, + /* pcie20_perstn_m1 */ + <3 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_waken_m1 */ + <3 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins =3D + /* pcie20_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk0: pdmm0-clk0 { + rockchip,pins =3D + /* pdm_clk0_m0 */ + <3 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins =3D + /* pdm_clk1_m0 */ + <3 RK_PA2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins =3D + /* pdm_sdi0_m0 */ + <3 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins =3D + /* pdm_sdi1_m0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins =3D + /* pdm_sdi2_m0 */ + <3 RK_PA7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins =3D + /* pdm_sdi3_m0 */ + <3 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk0: pdmm1-clk0 { + rockchip,pins =3D + /* pdm_clk0_m1 */ + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins =3D + /* pdm_clk1_m1 */ + <4 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins =3D + /* pdm_sdi0_m1 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins =3D + /* pdm_sdi1_m1 */ + <4 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins =3D + /* pdm_sdi2_m1 */ + <4 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins =3D + /* pdm_sdi3_m1 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_int: pmic-int { + rockchip,pins =3D + <0 RK_PA3 0 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + soc_slppin_gpio: soc-slppin-gpio { + rockchip,pins =3D + <0 RK_PA2 0 &pcfg_output_low>; + }; + + /omit-if-no-ref/ + soc_slppin_slp: soc-slppin-slp { + rockchip,pins =3D + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins =3D + /* pmu_debug */ + <0 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins =3D + /* pwm0_m0 */ + <0 RK_PC3 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins =3D + /* pwm0_m1 */ + <1 RK_PC5 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins =3D + /* pwm1_m0 */ + <0 RK_PC4 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins =3D + /* pwm1_m1 */ + <1 RK_PC6 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins =3D + /* pwm2_m0 */ + <0 RK_PC5 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins =3D + /* pwm2_m1 */ + <1 RK_PC7 3 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins =3D + /* pwm3_m0 */ + <0 RK_PA7 1 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins =3D + /* pwm3_m1 */ + <1 RK_PD0 3 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins =3D + /* pwm4_m0 */ + <0 RK_PB7 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins =3D + /* pwm4_m1 */ + <1 RK_PD1 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins =3D + /* pwm5_m0 */ + <0 RK_PC2 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins =3D + /* pwm5_m1 */ + <1 RK_PD2 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins =3D + /* pwm6_m0 */ + <0 RK_PC1 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins =3D + /* pwm6_m1 */ + <1 RK_PD3 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins =3D + /* pwm7_m0 */ + <0 RK_PC0 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins =3D + /* pwm7_m1 */ + <1 RK_PD4 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins =3D + /* pwm8_m0 */ + <3 RK_PA4 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins =3D + /* pwm8_m1 */ + <1 RK_PC1 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins =3D + /* pwm9_m0 */ + <3 RK_PA5 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins =3D + /* pwm9_m1 */ + <1 RK_PC2 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins =3D + /* pwm10_m0 */ + <1 RK_PB5 5 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins =3D + /* pwm10_m1 */ + <1 RK_PC3 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins =3D + /* pwm11_m0 */ + <1 RK_PB6 5 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins =3D + /* pwm11_m1 */ + <1 RK_PC4 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins =3D + /* pwm12_m0 */ + <4 RK_PA1 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins =3D + /* pwm12_m1 */ + <3 RK_PB4 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins =3D + /* pwm13_m0 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins =3D + /* pwm13_m1 */ + <3 RK_PB5 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins =3D + /* pwm14_m0 */ + <3 RK_PC5 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins =3D + /* pwm14_m1 */ + <1 RK_PD7 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins =3D + /* pwm15_m0 */ + <3 RK_PC6 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins =3D + /* pwm15_m1 */ + <2 RK_PA0 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr_pins: pwr-pins { + rockchip,pins =3D + /* pwr_ctrl0 */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + ref { + /omit-if-no-ref/ + ref_pins: ref-pins { + rockchip,pins =3D + /* ref_clk_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + rgmii { + /omit-if-no-ref/ + rgmiim0_miim: rgmiim0-miim { + rockchip,pins =3D + /* rgmii_mdc_m0 */ + <4 RK_PB2 2 &pcfg_pull_none>, + /* rgmii_mdio_m0 */ + <4 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rx_er: rgmiim0-rx_er { + rockchip,pins =3D + /* rgmii_rxer_m0 */ + <4 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rx_bus2: rgmiim0-rx_bus2 { + rockchip,pins =3D + /* rgmii_rxd0_m0 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_rxdv_m0 */ + <4 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_tx_bus2: rgmiim0-tx_bus2 { + rockchip,pins =3D + /* rgmii_txd0_m0 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* rgmii_txd1_m0 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* rgmii_txen_m0 */ + <4 RK_PA4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rgmii_clk: rgmiim0-rgmii_clk { + rockchip,pins =3D + /* rgmii_rxclk_m0 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* rgmii_txclk_m0 */ + <3 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rgmii_bus: rgmiim0-rgmii_bus { + rockchip,pins =3D + /* rgmii_rxd2_m0 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m0 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* rgmii_txd2_m0 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* rgmii_txd3_m0 */ + <3 RK_PD5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_clk: rgmiim0-clk { + rockchip,pins =3D + /* rgmiim0_clk */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_miim: rgmiim1-miim { + rockchip,pins =3D + /* rgmii_mdc_m1 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <1 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rx_er: rgmiim1-rx_er { + rockchip,pins =3D + /* rgmii_rxer_m1 */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rx_bus2: rgmiim1-rx_bus2 { + rockchip,pins =3D + /* rgmii_rxd0_m1 */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <1 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_tx_bus2: rgmiim1-tx_bus2 { + rockchip,pins =3D + /* rgmii_txd0_m1 */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* rgmii_txd1_m1 */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* rgmii_txen_m1 */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rgmii_clk: rgmiim1-rgmii_clk { + rockchip,pins =3D + /* rgmii_rxclk_m1 */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rgmii_bus: rgmiim1-rgmii_bus { + rockchip,pins =3D + /* rgmii_rxd2_m1 */ + <1 RK_PC4 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* rgmii_txd2_m1 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* rgmii_txd3_m1 */ + <1 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_clk: rgmiim1-clk { + rockchip,pins =3D + /* rgmiim1_clk */ + <1 RK_PD5 2 &pcfg_pull_none>; + }; + }; + + rmii { + /omit-if-no-ref/ + rmii_pins: rmii-pins { + rockchip,pins =3D + /* rmii_clk */ + <1 RK_PD5 5 &pcfg_pull_none>, + /* rmii_mdc */ + <1 RK_PC7 5 &pcfg_pull_none>, + /* rmii_mdio */ + <1 RK_PD0 5 &pcfg_pull_none>, + /* rmii_rxd0 */ + <1 RK_PD4 5 &pcfg_pull_none>, + /* rmii_rxd1 */ + <1 RK_PD7 6 &pcfg_pull_none>, + /* rmii_rxdv_crs */ + <1 RK_PD6 5 &pcfg_pull_none>, + /* rmii_rxer */ + <2 RK_PA0 6 &pcfg_pull_none>, + /* rmii_txd0 */ + <1 RK_PD1 5 &pcfg_pull_none>, + /* rmii_txd1 */ + <1 RK_PD2 5 &pcfg_pull_none>, + /* rmii_txen */ + <1 RK_PD3 5 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins =3D + /* sdmmc0_d0 */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins =3D + /* sdmmc0_clk */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins =3D + /* sdmmc0_cmd */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins =3D + /* sdmmc0_detn */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins =3D + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins =3D + /* sdmmc1_d0 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins =3D + /* sdmmc1_clk */ + <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins =3D + /* sdmmc1_cmd */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins =3D + /* sdmmc1_detn */ + <1 RK_PD0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins =3D + /* sdmmc1_pwren */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_pins: spdifm0-pins { + rockchip,pins =3D + /* spdif_tx_m0 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_pins: spdifm1-pins { + rockchip,pins =3D + /* spdif_tx_m1 */ + <0 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_pins: spdifm2-pins { + rockchip,pins =3D + /* spdif_tx_m2 */ + <1 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins =3D + /* spi0_clk_m0 */ + <0 RK_PC3 3 &pcfg_pull_none_drv_level_3>, + /* spi0_miso_m0 */ + <0 RK_PC5 3 &pcfg_pull_none_drv_level_3>, + /* spi0_mosi_m0 */ + <0 RK_PC4 3 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m0_csn0: spi0m0-csn0 { + rockchip,pins =3D + /* spi0m0_csn0 */ + <0 RK_PC2 3 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi0m0_csn1: spi0m0-csn1 { + rockchip,pins =3D + /* spi0m0_csn1 */ + <0 RK_PB7 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins =3D + /* spi0_clk_m1 */ + <3 RK_PB5 4 &pcfg_pull_none_drv_level_3>, + /* spi0_miso_m1 */ + <3 RK_PC0 4 &pcfg_pull_none_drv_level_3>, + /* spi0_mosi_m1 */ + <3 RK_PB4 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m1_csn0: spi0m1-csn0 { + rockchip,pins =3D + /* spi0m1_csn0 */ + <3 RK_PB7 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi0m1_csn1: spi0m1-csn1 { + rockchip,pins =3D + /* spi0m1_csn1 */ + <3 RK_PB6 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins =3D + /* spi1_clk_m0 */ + <3 RK_PD6 4 &pcfg_pull_none_drv_level_3>, + /* spi1_miso_m0 */ + <4 RK_PA3 4 &pcfg_pull_none_drv_level_3>, + /* spi1_mosi_m0 */ + <4 RK_PA2 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m0_csn0: spi1m0-csn0 { + rockchip,pins =3D + /* spi1m0_csn0 */ + <3 RK_PD7 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi1m0_csn1: spi1m0-csn1 { + rockchip,pins =3D + /* spi1m0_csn1 */ + <4 RK_PA0 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins =3D + /* spi1_clk_m1 */ + <1 RK_PC0 4 &pcfg_pull_none_drv_level_3>, + /* spi1_miso_m1 */ + <1 RK_PB4 4 &pcfg_pull_none_drv_level_3>, + /* spi1_mosi_m1 */ + <1 RK_PB3 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m1_csn0: spi1m1-csn0 { + rockchip,pins =3D + /* spi1m1_csn0 */ + <1 RK_PB6 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi1m1_csn1: spi1m1-csn1 { + rockchip,pins =3D + /* spi1m1_csn1 */ + <1 RK_PB5 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins =3D + /* spi2_clk_m0 */ + <4 RK_PB6 4 &pcfg_pull_none_drv_level_3>, + /* spi2_miso_m0 */ + <3 RK_PD2 4 &pcfg_pull_none_drv_level_3>, + /* spi2_mosi_m0 */ + <3 RK_PD3 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m0_csn0: spi2m0-csn0 { + rockchip,pins =3D + /* spi2m0_csn0 */ + <4 RK_PB5 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi2m0_csn1: spi2m0-csn1 { + rockchip,pins =3D + /* spi2m0_csn1 */ + <4 RK_PB4 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins =3D + /* spi2_clk_m1 */ + <2 RK_PA1 4 &pcfg_pull_none_drv_level_3>, + /* spi2_miso_m1 */ + <2 RK_PA0 4 &pcfg_pull_none_drv_level_3>, + /* spi2_mosi_m1 */ + <1 RK_PD7 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m1_csn0: spi2m1-csn0 { + rockchip,pins =3D + /* spi2m1_csn0 */ + <1 RK_PD6 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi2m1_csn1: spi2m1-csn1 { + rockchip,pins =3D + /* spi2m1_csn1 */ + <1 RK_PD5 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_pins: tsadcm0-pins { + rockchip,pins =3D + /* tsadc_shut_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_pins: tsadcm1-pins { + rockchip,pins =3D + /* tsadc_shut_m1 */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut_org: tsadc-shut-org { + rockchip,pins =3D + /* tsadc_shut_org */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins =3D + /* uart0_rx_m0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins =3D + /* uart0_rx_m1 */ + <1 RK_PB3 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <1 RK_PB4 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins =3D + /* uart1_rx_m0 */ + <1 RK_PD1 1 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <1 RK_PD2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins =3D + /* uart1m0_ctsn */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins =3D + /* uart1m0_rtsn */ + <1 RK_PD3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins =3D + /* uart1_rx_m1 */ + <4 RK_PA6 3 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <4 RK_PA5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins =3D + /* uart1m1_ctsn */ + <4 RK_PB0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins =3D + /* uart1m1_rtsn */ + <4 RK_PA7 3 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins =3D + /* uart2_rx_m0 */ + <0 RK_PC1 1 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PC0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins =3D + /* uart2m0_ctsn */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins =3D + /* uart2m0_rtsn */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins =3D + /* uart2_rx_m1 */ + <3 RK_PA1 2 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA0 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins =3D + /* uart2m1_ctsn */ + <3 RK_PA2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins =3D + /* uart2m1_rtsn */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins =3D + /* uart3_rx_m0 */ + <4 RK_PB5 6 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <4 RK_PB4 6 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins =3D + /* uart3m0_ctsn */ + <4 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins =3D + /* uart3m0_rtsn */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins =3D + /* uart3_rx_m1 */ + <3 RK_PC0 3 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <3 RK_PB7 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_ctsn: uart3m1-ctsn { + rockchip,pins =3D + /* uart3m1_ctsn */ + <3 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3m1_rtsn: uart3m1-rtsn { + rockchip,pins =3D + /* uart3m1_rtsn */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins =3D + /* uart4_rx_m0 */ + <3 RK_PD1 3 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PD0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins =3D + /* uart4m0_ctsn */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins =3D + /* uart4m0_rtsn */ + <3 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins =3D + /* uart4_rx_m1 */ + <1 RK_PD5 3 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <1 RK_PD6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m1_ctsn: uart4m1-ctsn { + rockchip,pins =3D + /* uart4m1_ctsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4m1_rtsn: uart4m1-rtsn { + rockchip,pins =3D + /* uart4m1_rtsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins =3D + /* uart5_rx_m0 */ + <1 RK_PB7 3 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <1 RK_PC0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins =3D + /* uart5m0_ctsn */ + <1 RK_PB5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins =3D + /* uart5m0_rtsn */ + <1 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins =3D + /* uart5_rx_m1 */ + <3 RK_PA7 5 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <3 RK_PA6 5 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins =3D + /* uart5m1_ctsn */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins =3D + /* uart5m1_rtsn */ + <3 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins =3D + /* uart6_rx_m0 */ + <0 RK_PC7 1 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <0 RK_PC6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins =3D + /* uart6m0_ctsn */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins =3D + /* uart6m0_rtsn */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins =3D + /* uart6_rx_m1 */ + <4 RK_PB0 5 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <4 RK_PA7 5 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_ctsn: uart6m1-ctsn { + rockchip,pins =3D + /* uart6m1_ctsn */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6m1_rtsn: uart6m1-rtsn { + rockchip,pins =3D + /* uart6m1_rtsn */ + <4 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins =3D + /* uart7_rx_m0 */ + <3 RK_PC7 3 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <3 RK_PC4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins =3D + /* uart7m0_ctsn */ + <3 RK_PD2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins =3D + /* uart7m0_rtsn */ + <3 RK_PD3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins =3D + /* uart7_rx_m1 */ + <1 RK_PB3 3 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <1 RK_PB4 3 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins =3D + /* uart8_rx_m0 */ + <3 RK_PB3 3 &pcfg_pull_up>, + /* uart8_tx_m0 */ + <3 RK_PB2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins =3D + /* uart8m0_ctsn */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins =3D + /* uart8m0_rtsn */ + <3 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins =3D + /* uart8_rx_m1 */ + <3 RK_PD5 3 &pcfg_pull_up>, + /* uart8_tx_m1 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m1_ctsn: uart8m1-ctsn { + rockchip,pins =3D + /* uart8m1_ctsn */ + <3 RK_PD7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8m1_rtsn: uart8m1-rtsn { + rockchip,pins =3D + /* uart8m1_rtsn */ + <4 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins =3D + /* uart9_rx_m0 */ + <4 RK_PB3 3 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <4 RK_PB2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins =3D + /* uart9m0_ctsn */ + <4 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins =3D + /* uart9m0_rtsn */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins =3D + /* uart9_rx_m1 */ + <3 RK_PC3 3 &pcfg_pull_up>, + /* uart9_tx_m1 */ + <3 RK_PC2 3 &pcfg_pull_up>; + }; + }; + + vo { + /omit-if-no-ref/ + vo_pins: vo-pins { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d0 */ + <4 RK_PA4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d1 */ + <4 RK_PA5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d2 */ + <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d8 */ + <4 RK_PA6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d9 */ + <4 RK_PA7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d16 */ + <4 RK_PB0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d17 */ + <4 RK_PB1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d18 */ + <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + vo { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + bt656_pins: bt656-pins { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb3x8_pins_m0: rgb3x8-pins-m0 { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb3x8_pins_m1: rgb3x8-pins-m1 { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb565_pins: rgb565-pins { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb666_pins: rgb666-pins { + rockchip,pins =3D + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d2 */ + <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d18 */ + <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts= /rockchip/rk3562.dtsi new file mode 100644 index 000000000000..95ace4ddc2b5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -0,0 +1,1270 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible =3D "rockchip,rk3562"; + + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + gpio0 =3D &gpio0; + gpio1 =3D &gpio1; + gpio2 =3D &gpio2; + gpio3 =3D &gpio3; + gpio4 =3D &gpio4; + }; + + xin32k: clock-xin32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "xin32k"; + }; + + xin24m: clock-xin24m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "xin24m"; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + clocks =3D <&scmi_clk ARMCLK>; + cpu-idle-states =3D <&CPU_SLEEP>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + dynamic-power-coefficient =3D <138>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x1>; + enable-method =3D "psci"; + clocks =3D <&scmi_clk ARMCLK>; + cpu-idle-states =3D <&CPU_SLEEP>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + dynamic-power-coefficient =3D <138>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x2>; + enable-method =3D "psci"; + clocks =3D <&scmi_clk ARMCLK>; + cpu-idle-states =3D <&CPU_SLEEP>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + dynamic-power-coefficient =3D <138>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x3>; + enable-method =3D "psci"; + clocks =3D <&scmi_clk ARMCLK>; + cpu-idle-states =3D <&CPU_SLEEP>; + operating-points-v2 =3D <&cpu0_opp_table>; + #cooling-cells =3D <2>; + dynamic-power-coefficient =3D <138>; + }; + + idle-states { + entry-method =3D "psci"; + CPU_SLEEP: cpu-sleep { + compatible =3D "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param =3D <0x0010000>; + entry-latency-us =3D <120>; + exit-latency-us =3D <250>; + min-residency-us =3D <900>; + }; + }; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz =3D /bits/ 64 <408000000>; + opp-microvolt =3D <825000 825000 1150000>; + clock-latency-ns =3D <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <825000 825000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-816000000 { + opp-hz =3D /bits/ 64 <816000000>; + opp-microvolt =3D <825000 825000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-1008000000 { + opp-hz =3D /bits/ 64 <1008000000>; + opp-microvolt =3D <850000 850000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <925000 925000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <1000000 1000000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-1608000000 { + opp-supported-hw =3D <0xf9 0xffff>; + opp-hz =3D /bits/ 64 <1608000000>; + opp-microvolt =3D <1037500 1037500 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <1125000 1125000 1150000>; + clock-latency-ns =3D <40000>; + }; + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-microvolt =3D <1150000 1150000 1150000>; + clock-latency-ns =3D <40000>; + }; + + }; + + gpu_opp_table: opp-table-gpu { + compatible =3D "operating-points-v2"; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-microvolt =3D <825000 825000 1000000>; + }; + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <825000 825000 1000000>; + }; + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <825000 825000 1000000>; + }; + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <825000 825000 1000000>; + }; + opp-700000000 { + opp-hz =3D /bits/ 64 <700000000>; + opp-microvolt =3D <900000 900000 1000000>; + }; + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <950000 950000 1000000>; + }; + opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + }; + }; + + arm_pmu: arm-pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + firmware { + scmi: scmi { + compatible =3D "arm,scmi-smc"; + shmem =3D <&scmi_shmem>; + arm,smc-id =3D <0x82000010>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + usbdrd_dwc3: usb@fe500000 { + compatible =3D "rockchip,rk3562-dwc3", "snps,dwc3"; + reg =3D <0x0 0xfe500000 0x0 0x400000>; + clocks =3D <&cru CLK_USB3OTG_REF>, <&cru CLK_USB3OTG_SUSPEND>, + <&cru ACLK_USB3OTG>, <&cru PCLK_PHP>; + clock-names =3D "ref_clk", "suspend_clk", "bus_clk", "pipe"; + interrupts =3D ; + power-domains =3D <&power RK3562_PD_PHP>; + resets =3D <&cru SRST_USB3OTG>; + dr_mode =3D "otg"; + phys =3D <&u2phy_otg>; + phy-names =3D "usb2-phy"; + phy_type =3D "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status =3D "disabled"; + }; + + gic: interrupt-controller@fe901000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + reg =3D <0x0 0xfe901000 0 0x1000>, + <0x0 0xfe902000 0 0x2000>, + <0x0 0xfe904000 0 0x2000>, + <0x0 0xfe906000 0 0x2000>; + interrupts =3D ; + }; + + usb_host0_ehci: usb@fed00000 { + compatible =3D "generic-ehci"; + reg =3D <0x0 0xfed00000 0x0 0x40000>; + interrupts =3D ; + clocks =3D <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, + <&u2phy>; + phys =3D <&u2phy_host>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + usb_host0_ohci: usb@fed40000 { + compatible =3D "generic-ohci"; + reg =3D <0x0 0xfed40000 0x0 0x40000>; + interrupts =3D ; + clocks =3D <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, + <&u2phy>; + phys =3D <&u2phy_host>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + qos_dma2ddr: qos@fee03800 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee03800 0x0 0x20>; + }; + + qos_mcu: qos@fee10000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee10000 0x0 0x20>; + }; + + qos_dft_apb: qos@fee10100 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee10100 0x0 0x20>; + }; + + qos_gmac: qos@fee10200 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee10200 0x0 0x20>; + }; + + qos_mac100: qos@fee10300 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee10300 0x0 0x20>; + }; + + qos_dcf: qos@fee10400 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee10400 0x0 0x20>; + }; + + qos_cpu: qos@fee20000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee20000 0x0 0x20>; + }; + + qos_gpu: qos@fee30000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee30000 0x0 0x20>; + }; + + qos_npu: qos@fee40000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee40000 0x0 0x20>; + }; + + qos_rkvdec: qos@fee50000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee50000 0x0 0x20>; + }; + + qos_vepu: qos@fee60000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee60000 0x0 0x20>; + }; + + qos_isp: qos@fee70000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee70000 0x0 0x20>; + }; + + qos_vicap: qos@fee70100 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee70100 0x0 0x20>; + }; + + qos_vop: qos@fee80000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee80000 0x0 0x20>; + }; + + qos_jpeg: qos@fee90000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee90000 0x0 0x20>; + }; + + qos_rga_rd: qos@fee90100 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee90100 0x0 0x20>; + }; + + qos_rga_wr: qos@fee90200 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfee90200 0x0 0x20>; + }; + + qos_pcie: qos@feea0000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeea0000 0x0 0x20>; + }; + + qos_usb3: qos@feea0100 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeea0100 0x0 0x20>; + }; + + qos_crypto_apb: qos@feeb0000 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0000 0x0 0x20>; + }; + + qos_crypto: qos@feeb0100 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0100 0x0 0x20>; + }; + + qos_dmac: qos@feeb0200 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0200 0x0 0x20>; + }; + + qos_emmc: qos@feeb0300 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0300 0x0 0x20>; + }; + + qos_fspi: qos@feeb0400 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0400 0x0 0x20>; + }; + + qos_rkdma: qos@feeb0500 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0500 0x0 0x20>; + }; + + qos_sdmmc0: qos@feeb0600 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0600 0x0 0x20>; + }; + + qos_sdmmc1: qos@feeb0700 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0700 0x0 0x20>; + }; + + qos_usb2: qos@feeb0800 { + compatible =3D "rockchip,rk3562-qos", "syscon"; + reg =3D <0x0 0xfeeb0800 0x0 0x20>; + }; + + pmu_grf: syscon@ff010000 { + compatible =3D "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd"; + reg =3D <0x0 0xff010000 0x0 0x10000>; + + reboot_mode: reboot-mode { + compatible =3D "syscon-reboot-mode"; + offset =3D <0x220>; + mode-normal =3D ; + mode-loader =3D ; + mode-recovery =3D ; + mode-bootloader =3D ; + }; + }; + + sys_grf: syscon@ff030000 { + compatible =3D "rockchip,rk3562-sys-grf", "syscon"; + reg =3D <0x0 0xff030000 0x0 0x10000>; + }; + + peri_grf: syscon@ff040000 { + compatible =3D "rockchip,rk3562-peri-grf", "syscon"; + reg =3D <0x0 0xff040000 0x0 0x10000>; + }; + + ioc_grf: syscon@ff060000 { + compatible =3D "rockchip,rk3562-ioc-grf", "syscon"; + reg =3D <0x0 0xff060000 0x0 0x30000>; + }; + + usbphy_grf: syscon@ff090000 { + compatible =3D "rockchip,rk3562-usbphy-grf", "syscon"; + reg =3D <0x0 0xff090000 0x0 0x8000>; + }; + + pipephy_grf: syscon@ff098000 { + compatible =3D "rockchip,rk3562-pipephy-grf", "syscon"; + reg =3D <0x0 0xff098000 0x0 0x8000>; + }; + + cru: clock-controller@ff100000 { + compatible =3D "rockchip,rk3562-cru"; + reg =3D <0x0 0xff100000 0x0 0x40000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + assigned-clocks =3D <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_HPLL>; + assigned-clock-rates =3D <1188000000>, <1000000000>, + <983040000>; + }; + + i2c0: i2c@ff200000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xff200000 0x0 0x1000>; + clocks =3D <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart0: serial@ff210000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff210000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + spi0: spi@ff220000 { + compatible =3D "rockchip,rk3562-spi", "rockchip,rk3066-spi"; + reg =3D <0x0 0xff220000 0x0 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac 13>, <&dmac 12>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; + status =3D "disabled"; + }; + + pwm0: pwm@ff230000 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff230000 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm0m0_pins>; + clocks =3D <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm1: pwm@ff230010 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff230010 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm1m0_pins>; + clocks =3D <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm2: pwm@ff230020 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff230020 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm2m0_pins>; + clocks =3D <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm3: pwm@ff230030 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff230030 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm3m0_pins>; + clocks =3D <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pmu: power-management@ff258000 { + compatible =3D "rockchip,rk3562-pmu", "syscon", "simple-mfd"; + reg =3D <0x0 0xff258000 0x0 0x1000>; + + power: power-controller { + compatible =3D "rockchip,rk3562-power-controller"; + #power-domain-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + + power-domain@RK3562_PD_GPU { + reg =3D ; + pm_qos =3D <&qos_gpu>; + #power-domain-cells =3D <0>; + }; + + power-domain@RK3562_PD_NPU { + reg =3D ; + pm_qos =3D <&qos_npu>; + #power-domain-cells =3D <0>; + }; + + power-domain@RK3562_PD_VDPU { + reg =3D ; + pm_qos =3D <&qos_rkvdec>; + #power-domain-cells =3D <0>; + }; + + power-domain@RK3562_PD_VI { + reg =3D ; + #power-domain-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + pm_qos =3D <&qos_isp>, + <&qos_vicap>; + + power-domain@RK3562_PD_VEPU { + reg =3D ; + pm_qos =3D <&qos_vepu>; + #power-domain-cells =3D <0>; + }; + }; + + power-domain@RK3562_PD_VO { + reg =3D ; + #power-domain-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + pm_qos =3D <&qos_vop>; + + power-domain@RK3562_PD_RGA { + reg =3D ; + pm_qos =3D <&qos_rga_rd>, + <&qos_rga_wr>, + <&qos_jpeg>; + #power-domain-cells =3D <0>; + }; + }; + + power-domain@RK3562_PD_PHP { + reg =3D ; + pm_qos =3D <&qos_pcie>, + <&qos_usb3>; + #power-domain-cells =3D <0>; + }; + }; + }; + + gpu: gpu@ff320000 { + compatible =3D "rockchip,rk3562-mali", "arm,mali-bifrost"; + reg =3D <0x0 0xff320000 0x0 0x4000>; + clocks =3D <&cru CLK_GPU>, <&cru CLK_GPU_BRG>, + <&cru ACLK_GPU_PRE>; + clock-names =3D "clk_gpu", "clk_gpu_brg", "aclk_gpu"; + dynamic-power-coefficient =3D <820>; + interrupts =3D , + , + ; + interrupt-names =3D "job", "mmu", "gpu"; + operating-points-v2 =3D <&gpu_opp_table>; + power-domains =3D <&power RK3562_PD_GPU>; + #cooling-cells =3D <2>; + status =3D "disabled"; + }; + + pcie2x1: pcie@ff500000 { + compatible =3D "rockchip,rk3562-pcie", "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + clocks =3D <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2x1_intc 0>, + <0 0 0 2 &pcie2x1_intc 1>, + <0 0 0 3 &pcie2x1_intc 2>, + <0 0 0 4 &pcie2x1_intc 3>; + linux,pci-domain =3D <0>; + max-link-speed =3D <2>; + num-ib-windows =3D <8>; + num-viewport =3D <8>; + num-ob-windows =3D <2>; + num-lanes =3D <1>; + phys =3D <&combphy_pu PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3562_PD_PHP>; + ranges =3D <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 + 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 + 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; + reg =3D <0x0 0xfe000000 0x0 0x400000>, + <0x0 0xff500000 0x0 0x10000>, + <0x0 0xfc000000 0x0 0x100000>; + reg-names =3D "dbi", "apb", "config"; + resets =3D <&cru SRST_PCIE20_POWERUP>; + reset-names =3D "pipe"; + status =3D "disabled"; + + pcie2x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + + spi1: spi@ff640000 { + compatible =3D "rockchip,rk3066-spi"; + reg =3D <0x0 0xff640000 0x0 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac 15>, <&dmac 14>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; + status =3D "disabled"; + }; + + spi2: spi@ff650000 { + compatible =3D "rockchip,rk3066-spi"; + reg =3D <0x0 0xff650000 0x0 0x1000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names =3D "spiclk", "apb_pclk"; + dmas =3D <&dmac 17>, <&dmac 16>; + dma-names =3D "tx", "rx"; + num-cs =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; + status =3D "disabled"; + }; + + uart1: serial@ff670000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff670000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart2: serial@ff680000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff680000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart3: serial@ff690000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff690000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart4: serial@ff6a0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6a0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart5: serial@ff6b0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6b0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart6: serial@ff6c0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6c0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart7: serial@ff6d0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6d0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart8: serial@ff6e0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6e0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart9: serial@ff6f0000 { + compatible =3D "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xff6f0000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names =3D "baudclk", "apb_pclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + pwm4: pwm@ff700000 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff700000 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm4m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm5: pwm@ff700010 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff700010 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm5m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm6: pwm@ff700020 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff700020 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm6m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm7: pwm@ff700030 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff700030 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm7m0_pins>; + clocks =3D <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm8: pwm@ff710000 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff710000 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm8m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm9: pwm@ff710010 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff710010 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm9m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm10: pwm@ff710020 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff710020 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm10m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm11: pwm@ff710030 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff710030 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm11m0_pins>; + clocks =3D <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm12: pwm@ff720000 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff720000 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm12m0_pins>; + clocks =3D <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm13: pwm@ff720010 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff720010 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm13m0_pins>; + clocks =3D <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm14: pwm@ff720020 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff720020 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm14m0_pins>; + clocks =3D <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + pwm15: pwm@ff720030 { + compatible =3D "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg =3D <0x0 0xff720030 0x0 0x10>; + #pwm-cells =3D <3>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&pwm15m0_pins>; + clocks =3D <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names =3D "pwm", "pclk"; + status =3D "disabled"; + }; + + saradc0: adc@ff730000 { + compatible =3D "rockchip,rk3562-saradc"; + reg =3D <0x0 0xff730000 0x0 0x100>; + interrupts =3D ; + #io-channel-cells =3D <1>; + clocks =3D <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names =3D "saradc", "apb_pclk"; + resets =3D <&cru SRST_P_SARADC>; + reset-names =3D "saradc-apb"; + status =3D "disabled"; + }; + + u2phy: usb2-phy@ff740000 { + compatible =3D "rockchip,rk3562-usb2phy"; + reg =3D <0x0 0xff740000 0x0 0x10000>; + clocks =3D <&cru CLK_USB2PHY_REF>; + clock-names =3D "phyclk"; + #clock-cells =3D <0>; + clock-output-names =3D "usb480m_phy"; + rockchip,usbgrf =3D <&usbphy_grf>; + status =3D "disabled"; + + u2phy_otg: otg-port { + #phy-cells =3D <0>; + interrupts =3D , + , + ; + interrupt-names =3D "otg-bvalid", "otg-id", "linestate"; + status =3D "disabled"; + }; + + u2phy_host: host-port { + #phy-cells =3D <0>; + interrupts =3D ; + interrupt-names =3D "linestate"; + status =3D "disabled"; + }; + }; + + combphy_pu: phy@ff750000 { + compatible =3D "rockchip,rk3562-naneng-combphy"; + reg =3D <0x0 0xff750000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>, + <&cru PCLK_PHP>; + clock-names =3D "ref", "apb", "pipe"; + assigned-clocks =3D <&cru CLK_PIPEPHY_REF>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_PIPEPHY>; + reset-names =3D "phy"; + rockchip,pipe-grf =3D <&peri_grf>; + rockchip,pipe-phy-grf =3D <&pipephy_grf>; + status =3D "disabled"; + }; + + sfc: spi@ff860000 { + compatible =3D "rockchip,sfc"; + reg =3D <0x0 0xff860000 0x0 0x10000>; + interrupts =3D ; + clocks =3D <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names =3D "clk_sfc", "hclk_sfc"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + sdhci: mmc@ff870000 { + compatible =3D "rockchip,rk3562-dwcmshc", "rockchip,rk3588-dwcmshc"; + reg =3D <0x0 0xff870000 0x0 0x10000>; + interrupts =3D ; + assigned-clocks =3D <&cru BCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates =3D <200000000>, <200000000>; + clocks =3D <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names =3D "core", "bus", "axi", "block", "timer"; + resets =3D <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names =3D "core", "bus", "axi", "block", "timer"; + max-frequency =3D <200000000>; + status =3D "disabled"; + }; + + sdmmc0: mmc@ff880000 { + compatible =3D "rockchip,rk3562-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg =3D <0x0 0xff880000 0x0 0x10000>; + interrupts =3D ; + max-frequency =3D <200000000>; + clocks =3D <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names =3D "biu", "ciu", "ciu-drive", "ciu-sample"; + resets =3D <&cru SRST_H_SDMMC0>; + reset-names =3D "reset"; + fifo-depth =3D <0x100>; + status =3D "disabled"; + }; + + sdmmc1: mmc@ff890000 { + compatible =3D "rockchip,rk3562-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg =3D <0x0 0xff890000 0x0 0x10000>; + interrupts =3D ; + max-frequency =3D <200000000>; + clocks =3D <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names =3D "biu", "ciu", "ciu-drive", "ciu-sample"; + resets =3D <&cru SRST_H_SDMMC1>; + reset-names =3D "reset"; + fifo-depth =3D <0x100>; + status =3D "disabled"; + }; + + dmac: dma-controller@ff990000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0xff990000 0x0 0x4000>; + arm,pl330-periph-burst; + clocks =3D <&cru ACLK_DMAC>; + clock-names =3D "apb_pclk"; + interrupts =3D , + ; + #dma-cells =3D <1>; + }; + + i2c1: i2c@ffa00000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xffa00000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1m0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@ffa10000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xffa10000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2m0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@ffa20000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xffa20000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3m0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@ffa30000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xffa30000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4m0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@ffa40000 { + compatible =3D "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg =3D <0x0 0xffa40000 0x0 0x1000>; + clocks =3D <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names =3D "i2c", "pclk"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5m0_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + wdt: watchdog@ffa60000 { + compatible =3D "rockchip,rk3562-wdt", "snps,dw-wdt"; + reg =3D <0x0 0xffa60000 0x0 0x100>; + clocks =3D <&cru CLK_WDTNS>, <&cru PCLK_WDTNS>; + clock-names =3D "tclk", "pclk"; + interrupts =3D ; + status =3D "disabled"; + }; + + saradc1: adc@ffaa0000 { + compatible =3D "rockchip,rk3562-saradc"; + reg =3D <0x0 0xffaa0000 0x0 0x100>; + interrupts =3D ; + #io-channel-cells =3D <1>; + clocks =3D <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>; + clock-names =3D "saradc", "apb_pclk"; + resets =3D <&cru SRST_P_SARADC_VCCIO156>; + reset-names =3D "saradc-apb"; + status =3D "disabled"; + }; + + pinctrl: pinctrl { + compatible =3D "rockchip,rk3562-pinctrl"; + rockchip,grf =3D <&ioc_grf>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gpio0: gpio@ff260000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xff260000 0x0 0x100>; + clocks =3D <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 0 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio1: gpio@ff620000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xff620000 0x0 0x100>; + clocks =3D <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 32 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio2: gpio@ff630000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xff630000 0x0 0x100>; + clocks =3D <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 64 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio3: gpio@ffac0000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xffac0000 0x0 0x100>; + clocks =3D <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 96 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + + gpio4: gpio@ffad0000 { + compatible =3D "rockchip,gpio-bank"; + reg =3D <0x0 0xffad0000 0x0 0x100>; + clocks =3D <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; + gpio-controller; + gpio-ranges =3D <&pinctrl 0 128 32>; + interrupts =3D ; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; + }; + }; +}; + +#include "rk3562-pinctrl.dtsi" --=20 2.25.1 From nobody Tue Dec 16 23:11:58 2025 Received: from mail-m8188.xmail.ntesmail.com (mail-m8188.xmail.ntesmail.com [156.224.81.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A9C222DF8D; Tue, 6 May 2025 03:33:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="Bbd2kagB" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 140c6eb23; Tue, 6 May 2025 10:57:30 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Finley Xiao , Kever Yang , devicetree@vger.kernel.org, Conor Dooley , Rob Herring , FUKAUMI Naoki , Dragan Simic , Jonas Karlman , linux-kernel@vger.kernel.org, Diederik de Haas , Quentin Schulz , Johan Jonker , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 6/6] arm64: dts: rockchip: Add RK3562 evb2 devicetree Date: Tue, 6 May 2025 10:57:15 +0800 Message-Id: <20250506025715.33595-7-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250506025715.33595-1-kever.yang@rock-chips.com> References: <20250506025715.33595-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGh8YGVZCHxgYS0MZQh8dHU5WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a96a386ea2603afkunm140c6eb23 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NDo6IQw5EjJJLxEMST41MCMs Ki4aFC9VSlVKTE9NTktLSU5KQk5JVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKT09DQzcG DKIM-Signature: a=rsa-sha256; b=Bbd2kagBxh8YJEBDu04pYhlJv8cjhwLgg0DLz7cwSPgRfMpoOsvNYYaYkq6P0mP8W06bwBYfaNkaQTkX4CxXVR1Q1UsNaLgiQ3ZUoso+QQ+2w8RZPifK2XRQPDfSGj4NyyxB0f8YpEjVuIpLN7hXZ2XMXJsku5gXAhocN2GN1mg=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=2wOvY6LoPKXLh4TcDTfWpyFQGSltxZqhMXHFIDv5Qnw=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" From: Finley Xiao DRAM: DDR4 Storage: eMMC PMIC: RK809 Audio: Headphone and speaker Interface: - USB3.0 HOST - USB2.0 HOST - PCIe x4 slot(pcie2x1 available) - SD card slot - GMAC - debug UART0 NOTE: the USB3.0 and the PCIe reuse the comboPHY, so the USB3.0 work in USB2 only mode. Signed-off-by: Finley Xiao Signed-off-by: Kever Yang --- Changes in v5: None Changes in v4: - remove gmac nodes Changes in v3: None Changes in v2: None arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3562-evb2-v10.dts | 488 ++++++++++++++++++ 2 files changed, 489 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 7948522cb225..faf6264a772c 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3528-radxa-e20c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3562-evb2-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-anbernic-rg-arc-d.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-anbernic-rg-arc-s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-anbernic-rg353p.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3562-evb2-v10.dts new file mode 100644 index 000000000000..b7e01cfe2f5a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3562.dtsi" + +/ { + model =3D "Rockchip RK3562 EVB V20 Board"; + compatible =3D "rockchip,rk3562-evb2-v10", "rockchip,rk3562"; + + chosen: chosen { + stdout-path =3D "serial0:1500000n8"; + }; + + adc_keys: adc-keys { + compatible =3D "adc-keys"; + io-channels =3D <&saradc0 1>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-vol-up { + linux,code =3D ; + label =3D "volume up"; + press-threshold-microvolt =3D <17000>; + }; + + button-vol-down { + linux,code =3D ; + label =3D "volume down"; + press-threshold-microvolt =3D <414000>; + }; + + button-menu { + linux,code =3D ; + label =3D "menu"; + press-threshold-microvolt =3D <800000>; + }; + + button-back { + linux,code =3D ; + label =3D "back"; + press-threshold-microvolt =3D <1200000>; + }; + }; + + leds: leds { + compatible =3D "gpio-leds"; + work_led: led-0 { + gpios =3D <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + dc_12v: dc-12v { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rk809 1>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms =3D <200>; + reset-gpios =3D <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie20"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + gpios =3D <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <5000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc5v0_usb>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_host_pwren>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_otg"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc5v0_usb>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_otg_pwren>; + }; + + vcc3v3_clk: vcc3v3-clk { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_clk"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&dc_12v>; + }; +}; + +&combphy_pu { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 =3D <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells =3D <1>; + clock-output-names =3D "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG1 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-name =3D "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-name =3D "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG9 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pcie2x1 { + reset-gpios =3D <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie20>; + status =3D "okay"; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins =3D <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins =3D <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc0 { + status =3D "okay"; + vref-supply =3D <&vcc_1v8>; +}; + +&sdhci { + bus-width =3D <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status =3D "okay"; +}; + +&sdmmc0 { + no-sdio; + no-mmc; + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status =3D "okay"; +}; + +&sdmmc1 { + no-sd; + no-mmc; + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status =3D "okay"; +}; + +&u2phy { + status =3D "okay"; +}; + +&u2phy_host { + status =3D "okay"; + phy-supply =3D <&vcc5v0_usb_host>; +}; + +&u2phy_otg { + status =3D "okay"; + phy-supply =3D <&vcc5v0_usb_otg>; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usbdrd_dwc3 { + status =3D "okay"; + dr_mode =3D "host"; + extcon =3D <&u2phy>; + maximum-speed =3D "high-speed"; + phys =3D <&u2phy_otg>; + phy-names =3D "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; --=20 2.25.1