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[87.8.31.78]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-441d4351abdsm6794475e9.23.2025.05.06.14.05.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 May 2025 14:05:20 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Tue, 06 May 2025 23:03:47 +0200 Subject: [PATCH v3 1/5] Documentation: ABI: IIO: add calibconv_delay documentation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250506-wip-bl-ad7606-calibration-v3-1-6eb7b6e72307@baylibre.com> References: <20250506-wip-bl-ad7606-calibration-v3-0-6eb7b6e72307@baylibre.com> In-Reply-To: <20250506-wip-bl-ad7606-calibration-v3-0-6eb7b6e72307@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1880; i=adureghello@baylibre.com; h=from:subject:message-id; bh=oTr2y1KzI44sJPbPH4SmBsKovzD+NKhk9SBNTTYhjpc=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiQqnT/5zg79e//urexjcsPrzU7UmXRvdBHa/dT5WlRd 1Ot76YXdJSyMIhxMciKKbLUJUaYhN4OlVJewDgbZg4rE8gQBi5OAZiI3QGGP7w6jXO9/NPfbXN9 sWHJzuQ7f+afWbf/8Cv5yObz13S5zn5gZNj9dMclxYqJIV+PszkEdu6Om1Jg7H7M3OjUj/MeQSU rvDkA X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add new IIO calibconv_delay documentation. The ad7606 implements a phase calibation feature, in nanoseconds. Being this a time delay, using the conv_delay suffix. Signed-off-by: Angelo Dureghello --- Documentation/ABI/testing/sysfs-bus-iio | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index 190bfcc1e836b69622692d7c056c0092e00f1a9b..9ced916895fbef146d46d17b5fd= c932784b4c1df 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -559,6 +559,30 @@ Description: - a small discrete set of values like "0 2 4 6 8" - a range specified as "[min step max]" =20 +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_convdelay +KernelVersion: 6.16 +Contact: linux-iio@vger.kernel.org +Description: + Delay of start of conversion in seconds from common reference + point shared by all channels. Can be writable when used to + compensate for delay variation introduced by external filters + feeding a simultaneous sampling ADC. + + I.e., for the ad7606 ADC series, this value is intended as a + configurable time delay in seconds, to correct delay introduced + by an optional external filtering circuit. + +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_convdelay_available +KernelVersion: 6.16 +Contact: linux-iio@vger.kernel.org +Description: + Available values of convdelay. Maybe expressed as: + + - a range specified as "[min step max]" + + If shared across all channels, _calibconv_delay_available + is used. + What: /sys/bus/iio/devices/iio:deviceX/in_accel_x_calibscale What: /sys/bus/iio/devices/iio:deviceX/in_accel_y_calibscale What: /sys/bus/iio/devices/iio:deviceX/in_accel_z_calibscale --=20 2.49.0 From nobody Tue Dec 16 07:31:46 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A91F3215F7D for ; Tue, 6 May 2025 21:05:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746565526; cv=none; b=ED3W/+o/4s6IHWMGprxjPCUKC722TKDrAtnVTUixBzq11e3JT9wFI1OfFgaDAjB/zGr8apu7qMaYofk6oqLUw8r/hZoviwFLWgXCzUunsPElYF94x+nMrL9lspc5y6tZCgyVBqxxiFEruhOySCsvcIugm4j4/cX8wQZc6Cp9eDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746565526; c=relaxed/simple; bh=8DecWNX9a+g7ci97Vv7IU6U85+eTrGoiJDNqhMLAwD0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o7MFSGPqTM8p+hUQWILz/SO2bZdN9S6YhvyPAgwuQY+BKQfCc9hQLhpwASYgAb4yd3HnccKDfGtVYAXdzhYm0kjCf0RpeAHPZND6j+e6NqGuQtts6aNyVg5OOIunK04HBLTUith8Gvl1f++gszJc2tI6aWxHNISfjO30VqxSduA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=BOysUuBm; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="BOysUuBm" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-43cfba466b2so52424085e9.3 for ; Tue, 06 May 2025 14:05:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1746565523; x=1747170323; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gQIoahuutc2qqjFxwM4CJBJC7cg2fQ/5cUj9Q0XSXuA=; b=BOysUuBmSoAEMOyH+RVIb0Pvh11HJ3xEGkP88oGtGf5uAixPvY86fTJwZ9xn6RC04t cWlTLWozS0d5l7ykVZQfjblN/GRR4NDqktJ1Bks3V9oM6AT0cvJ7iAr0pH/P131LOY/c 4YCy530NQPyL/W0qEBMoOannqil6mfPbLbex7W2cKcrp6svIHQaPKM/6RBTKkOPI7n+O 70CB/DIlM8pVPAqy93tsXfslt9EXAhOMBCmGHBtsvtylybpPOGK/Nh8qPuemBiBiBlFr PQiy7I6Vnk4dZlAbin7tY875sGnKLjkyv2VDXidxbJgMcYABkrFhLEnHmEKFw+LG+eNl ybbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746565523; x=1747170323; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gQIoahuutc2qqjFxwM4CJBJC7cg2fQ/5cUj9Q0XSXuA=; b=wK63aPe3Osrr8ztDpsknjwaG1UmXAMQwNQbq84pT7kFi21M5/iUmD7MNlhhg/pLdUR +VjcFSQWfWfE4+k0aT1MmMlcC4S+CAXpJ96ftY1R15JGkiIx+ehYu0KxjFTALjxw32Tb 2zqjU991pDjUBwE0lFPFJrHpkTJTRPshDjDEfcQ80nQ+snmLXns36SfXijoG5MrhTQku Cytdl8Uce5thnYNquqfKFm9p+Bb+zvJbnXTUV/crp3GvLSNHGXRcIqfG/u3YJWcmbZgD jS0M1Yx8gKzat8Ycu5vfPMvZyCHU2cDTZx1JA/B8w1//nIU6CYfcI4AazD7Sg/FsyQ7r 2INQ== X-Forwarded-Encrypted: i=1; AJvYcCVR8O4nTNEC18CH0CK/NIl44dqZcxlKcEcqSsDANQ4PH2UV6N8p/JF3UCIJBVcyHnd8tmEtzOf1KrBHZn0=@vger.kernel.org X-Gm-Message-State: AOJu0Yz7qgBHbxk3KoqJuxkusfd6z99Ev7tE3ABotBFjHBRFJ0wSXrbk yDMM6XgO5zLyopPD0utcwAb5wGnTbzHW8HZReswa7nQXfTeFbdjqSar0K82I/88= X-Gm-Gg: ASbGncsVVl+2oOo6134dHvDxK5hKgihgIiS5sjC20qCMVIx85c+UUEpBoirLPVMgWRO rnNixYdnL0B7Gx2Sc1qhGodp6PpsnCAk6vFIpTlOLWP5dFI4qVpn4eOyHyScFahB1Xd15IJd/uy BZBrfrGP/fMdmKt9KcroUnMdBDtanU5r50bLjgtwRFRn2zHLGr7pkiKQvgsCtGRK/KYxwgwxsj+ DrDx1N83PaOyjqlSMcNM9+E5/C9IknOm10it+Yt/JfqSeKF7oHqOVZMikdLkV3i3ZoitLdECFBX lWAlod+Fgx3kRG/xdv3TNA+DbaHKRn+g+j1H8SsRZKK4/N1D3pPOHBDfB5/4yXGdCG29zrQd6u+ fyGfrMZddMvmLoEHOs238zZg= X-Google-Smtp-Source: AGHT+IE0lNn0nT2i13dUfcqq/tEEHU4n3DZAgcrz6Oy4DZvTBDhpwmaW+VV7h81wiw+2Az3EYbCpFg== X-Received: by 2002:a05:600c:37c6:b0:43d:1b74:e89a with SMTP id 5b1f17b1804b1-441d44c3933mr3684925e9.9.1746565523006; Tue, 06 May 2025 14:05:23 -0700 (PDT) Received: from [192.168.0.2] (host-87-8-31-78.retail.telecomitalia.it. [87.8.31.78]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-441d4351abdsm6794475e9.23.2025.05.06.14.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 May 2025 14:05:22 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Tue, 06 May 2025 23:03:48 +0200 Subject: [PATCH v3 2/5] iio: core: add ADC delay calibration definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250506-wip-bl-ad7606-calibration-v3-2-6eb7b6e72307@baylibre.com> References: <20250506-wip-bl-ad7606-calibration-v3-0-6eb7b6e72307@baylibre.com> In-Reply-To: <20250506-wip-bl-ad7606-calibration-v3-0-6eb7b6e72307@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1303; i=adureghello@baylibre.com; h=from:subject:message-id; bh=4Hb5fAw6wk9UOyjGvMGWLBgqM5yKlaYwdF7azoNoMts=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiQqnQ3KT7w9NWpH9PZpfu5Yz+6RB9VY8lekhEqm5rIV 2dnkfqso5SFQYyLQVZMkaUuMcIk9HaolPICxtkwc1iZQIYwcHEKwEQ4rjP8032+bJ5MgIzJlhtz Zp1nV65mXhgq9kPi2YrPPWfvpPHaFDP8leabnfws1/gip23dg6dTBSVm11Uts/PXP+EiukNj08I YZgA= X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello ADCs as ad7606 implement a phase calibration as a delay. Add such definition, needed for ad7606. Signed-off-by: Angelo Dureghello --- drivers/iio/industrialio-core.c | 1 + include/linux/iio/types.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-cor= e.c index 178e99b111debc59a247fcc3a6037e429db3bebf..f13c3aa470d774bfe655d6a9fb0= 0c263789db637 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -188,6 +188,7 @@ static const char * const iio_chan_info_postfix[] =3D { [IIO_CHAN_INFO_CALIBAMBIENT] =3D "calibambient", [IIO_CHAN_INFO_ZEROPOINT] =3D "zeropoint", [IIO_CHAN_INFO_TROUGH] =3D "trough_raw", + [IIO_CHAN_INFO_CONVDELAY] =3D "convdelay", }; /** * iio_device_id() - query the unique ID for the device diff --git a/include/linux/iio/types.h b/include/linux/iio/types.h index d89982c98368cf72c0fc30fa66ab001e48af4e8b..ad2761efcc8315e1f9907d2a715= 9447fb463333e 100644 --- a/include/linux/iio/types.h +++ b/include/linux/iio/types.h @@ -69,6 +69,7 @@ enum iio_chan_info_enum { IIO_CHAN_INFO_CALIBAMBIENT, IIO_CHAN_INFO_ZEROPOINT, IIO_CHAN_INFO_TROUGH, + IIO_CHAN_INFO_CONVDELAY, }; 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[87.8.31.78]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-441d4351abdsm6794475e9.23.2025.05.06.14.05.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 May 2025 14:05:24 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Tue, 06 May 2025 23:03:49 +0200 Subject: [PATCH v3 3/5] iio: adc: ad7606: add offset and phase calibration support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250506-wip-bl-ad7606-calibration-v3-3-6eb7b6e72307@baylibre.com> References: <20250506-wip-bl-ad7606-calibration-v3-0-6eb7b6e72307@baylibre.com> In-Reply-To: <20250506-wip-bl-ad7606-calibration-v3-0-6eb7b6e72307@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9430; i=adureghello@baylibre.com; h=from:subject:message-id; bh=3PXmVxCz6657mCdpDOhkR+/JCD3hi9i1/g3nOKo+7HM=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiQqnSfxJ2xoPf2uvcnOHYe0Y1nEPhZdlB+Z8npR03Kd 2p4t+qZdpSyMIhxMciKKbLUJUaYhN4OlVJewDgbZg4rE8gQBi5OAZiI5FZGhj3396tMec062SCj 2WL63cn5O34lJl1YGewhu9NsabnIxTJGhs8MKyXtvjnuSKmwZDsQcdZh4qXGzbMtf/xZ5MErPMV SkwcA X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add support for offset and phase calibration, only for devices that support software mode, that are: ad7606b ad7606c-16 ad7606c-18 Tested-by: David Lechner Reviewed-by: Nuno S=C3=A1 Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 160 +++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/iio/adc/ad7606.h | 9 +++ 2 files changed, 169 insertions(+) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 2aa59481c52c07537110e7fc1fd1aedbab6b098d..a986eb1284106da4980ac36cb0b= 5990e4e3bd948 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -95,6 +95,22 @@ static const unsigned int ad7616_oversampling_avail[8] = =3D { 1, 2, 4, 8, 16, 32, 64, 128, }; =20 +static const int ad7606_calib_offset_avail[3] =3D { + -128, 1, 127, +}; + +static const int ad7606c_18bit_calib_offset_avail[3] =3D { + -512, 4, 508, +}; + +static const int ad7606b_calib_phase_avail[][2] =3D { + { 0, 0 }, { 0, 1250 }, { 0, 318750 }, +}; + +static const int ad7606c_calib_phase_avail[][2] =3D { + { 0, 0 }, { 0, 1000 }, { 0, 255000 }, +}; + static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan); static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev, @@ -164,6 +180,8 @@ const struct ad7606_chip_info ad7606b_info =3D { .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606_calib_offset_avail, + .calib_phase_avail =3D ad7606b_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606"); =20 @@ -177,6 +195,8 @@ const struct ad7606_chip_info ad7606c_16_info =3D { .scale_setup_cb =3D ad7606c_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606_calib_offset_avail, + .calib_phase_avail =3D ad7606c_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606"); =20 @@ -226,6 +246,8 @@ const struct ad7606_chip_info ad7606c_18_info =3D { .scale_setup_cb =3D ad7606c_18bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606c_18bit_calib_offset_avail, + .calib_phase_avail =3D ad7606c_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606"); =20 @@ -683,6 +705,40 @@ static int ad7606_scan_direct(struct iio_dev *indio_de= v, unsigned int ch, return ret; } =20 +static int ad7606_get_calib_offset(struct ad7606_state *st, int ch, int *v= al) +{ + int ret; + + ret =3D st->bops->reg_read(st, AD7606_CALIB_OFFSET(ch)); + if (ret < 0) + return ret; + + *val =3D st->chip_info->calib_offset_avail[0] + ret * + st->chip_info->calib_offset_avail[1]; + + return 0; +} + +static int ad7606_get_calib_phase(struct ad7606_state *st, int ch, int *va= l, + int *val2) +{ + int ret; + + ret =3D st->bops->reg_read(st, AD7606_CALIB_PHASE(ch)); + if (ret < 0) + return ret; + + *val =3D 0; + + /* + * ad7606b: phase delay from 0 to 318.75 =CE=BCs in steps of 1.25 =CE=BCs. + * ad7606c-16/18: phase delay from 0 =C2=B5s to 255 =C2=B5s in steps of 1= =C2=B5s. + */ + *val2 =3D ret * st->chip_info->calib_phase_avail[1][1]; + + return 0; +} + static int ad7606_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, @@ -717,6 +773,22 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); *val =3D DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period); return IIO_VAL_INT; + case IIO_CHAN_INFO_CALIBBIAS: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_get_calib_offset(st, chan->scan_index, val); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_get_calib_phase(st, chan->scan_index, val, val2); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + return IIO_VAL_INT_PLUS_NANO; } return -EINVAL; } @@ -767,6 +839,64 @@ static int ad7606_write_os_hw(struct iio_dev *indio_de= v, int val) return 0; } =20 +static int ad7606_set_calib_offset(struct ad7606_state *st, int ch, int va= l) +{ + int start_val, step_val, stop_val; + + start_val =3D st->chip_info->calib_offset_avail[0]; + step_val =3D st->chip_info->calib_offset_avail[1]; + stop_val =3D st->chip_info->calib_offset_avail[2]; + + if (val < start_val || val > stop_val) + return -EINVAL; + + val -=3D start_val; + val /=3D step_val; + + return st->bops->reg_write(st, AD7606_CALIB_OFFSET(ch), val); +} + +static int ad7606_set_calib_phase(struct ad7606_state *st, int ch, int val, + int val2) +{ + int wreg, start_ns, step_ns, stop_ns; + + if (val !=3D 0) + return -EINVAL; + + start_ns =3D st->chip_info->calib_phase_avail[0][1]; + step_ns =3D st->chip_info->calib_phase_avail[1][1]; + stop_ns =3D st->chip_info->calib_phase_avail[2][1]; + + /* + * ad7606b: phase delay from 0 to 318.75 =CE=BCs in steps of 1.25 =CE=BCs. + * ad7606c-16/18: phase delay from 0 =C2=B5s to 255 =C2=B5s in steps of 1= =C2=B5s. + */ + if (val2 < start_ns || val2 > stop_ns) + return -EINVAL; + + wreg =3D val2 / step_ns; + + return st->bops->reg_write(st, AD7606_CALIB_PHASE(ch), wreg); +} + +static int ad7606_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long info) +{ + switch (info) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_SAMP_FREQ: + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + case IIO_CHAN_INFO_CALIBBIAS: + return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: + return IIO_VAL_INT_PLUS_NANO; + default: + return -EINVAL; + } +} + static int ad7606_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, @@ -820,6 +950,18 @@ static int ad7606_write_raw(struct iio_dev *indio_dev, if (val < 0 && val2 !=3D 0) return -EINVAL; return ad7606_set_sampling_freq(st, val); + case IIO_CHAN_INFO_CALIBBIAS: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_set_calib_offset(st, chan->scan_index, val); + iio_device_release_direct(indio_dev); + return ret; + case IIO_CHAN_INFO_CONVDELAY: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_set_calib_phase(st, chan->scan_index, val, val2); + iio_device_release_direct(indio_dev); + return ret; default: return -EINVAL; } @@ -998,6 +1140,14 @@ static int ad7606_read_avail(struct iio_dev *indio_de= v, *type =3D IIO_VAL_INT_PLUS_MICRO; =20 return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_CALIBBIAS: + *vals =3D st->chip_info->calib_offset_avail; + *type =3D IIO_VAL_INT; + return IIO_AVAIL_RANGE; + case IIO_CHAN_INFO_CONVDELAY: + *vals =3D (const int *)st->chip_info->calib_phase_avail; + *type =3D IIO_VAL_INT_PLUS_NANO; + return IIO_AVAIL_RANGE; } return -EINVAL; } @@ -1060,6 +1210,7 @@ static const struct iio_info ad7606_info_sw_mode =3D { .read_raw =3D &ad7606_read_raw, .write_raw =3D &ad7606_write_raw, .read_avail =3D &ad7606_read_avail, + .write_raw_get_fmt =3D ad7606_write_raw_get_fmt, .debugfs_reg_access =3D &ad7606_reg_access, .validate_trigger =3D &ad7606_validate_trigger, .update_scan_mode =3D &ad7606_update_scan_mode, @@ -1252,6 +1403,15 @@ static int ad7606_probe_channels(struct iio_dev *ind= io_dev) chan->info_mask_separate_available |=3D BIT(IIO_CHAN_INFO_SCALE); =20 + if (st->chip_info->calib_offset_avail) { + chan->info_mask_separate |=3D + BIT(IIO_CHAN_INFO_CALIBBIAS) | + BIT(IIO_CHAN_INFO_CONVDELAY); + chan->info_mask_separate_available |=3D + BIT(IIO_CHAN_INFO_CALIBBIAS) | + BIT(IIO_CHAN_INFO_CONVDELAY); + } + /* * All chips with software mode support oversampling, * so we skip the oversampling_available check. And the diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 441e62c521bcbea69b4f70bb2d55f65334d22276..f613583a7fa4095115b0b28e3f8= e51cd32b93524 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -40,6 +40,11 @@ #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) #define AD7606_OS_MODE 0x08 =20 +#define AD7606_CALIB_GAIN(ch) (0x09 + (ch)) +#define AD7606_CALIB_GAIN_MASK GENMASK(5, 0) +#define AD7606_CALIB_OFFSET(ch) (0x11 + (ch)) +#define AD7606_CALIB_PHASE(ch) (0x19 + (ch)) + struct ad7606_state; =20 typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, @@ -61,6 +66,8 @@ typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio= _dev); * @init_delay_ms: required delay in milliseconds for initialization * after a restart * @offload_storagebits: storage bits used by the offload hw implementation + * @calib_offset_avail: pointer to offset calibration range/limits array + * @calib_phase_avail: pointer to phase calibration range/limits array */ struct ad7606_chip_info { unsigned int max_samplerate; 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[87.8.31.78]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-441d4351abdsm6794475e9.23.2025.05.06.14.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 May 2025 14:05:25 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Tue, 06 May 2025 23:03:50 +0200 Subject: [PATCH v3 4/5] dt-bindings: iio: adc: adi,ad7606: add gain calibration support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250506-wip-bl-ad7606-calibration-v3-4-6eb7b6e72307@baylibre.com> References: <20250506-wip-bl-ad7606-calibration-v3-0-6eb7b6e72307@baylibre.com> In-Reply-To: <20250506-wip-bl-ad7606-calibration-v3-0-6eb7b6e72307@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2030; i=adureghello@baylibre.com; h=from:subject:message-id; bh=mK1GoQiX2hS20/yC/1czrPjfc5t1uAwSltJDkMx72Mc=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiQqvR4o7TAXEehyJWnqy/bu73gB/+SjYkHbt4VeXWo5 NWX3d38HaUsDGJcDLJiiix1iREmobdDpZQXMM6GmcPKBDKEgYtTACbSys/wV/ztIrf1U7ZaCpR+ mr+poNwt9WX8KplXL309zaMkl4RkWzIybCyIXpOtlGreZpl/NSPFQu25vf7q52/3WMys2Xb44Ht PDgA= X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add gain calibration support by a per-channel resistor value. Acked-by: Conor Dooley Signed-off-by: Angelo Dureghello --- .../devicetree/bindings/iio/adc/adi,ad7606.yaml | 29 ++++++++++++++++++= ++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 29f12d650442b8ff2eb455306ce59a0e87867ddd..6926f5f090ad6bbbe7bfd9327dc= 5ae17dafcd1fd 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -204,6 +204,15 @@ patternProperties: considered a bipolar differential channel. Otherwise it is bipol= ar single-ended. =20 + adi,rfilter-ohms: + description: + For ADCs that supports gain calibration, this property must be s= et to + the value of the external RFilter resistor. Proper gain error + correction is applied based on this value. + default: 0 + minimum: 0 + maximum: 64512 + required: - reg - bipolar @@ -256,6 +265,25 @@ allOf: properties: adi,oversampling-ratio-gpios: false =20 + - if: + properties: + compatible: + contains: + enum: + - adi,ad7605-4 + - adi,ad7606-4 + - adi,ad7606-6 + - adi,ad7606-8 + - adi,ad7607 + - adi,ad7608 + - adi,ad7609 + - adi,ad7616 + then: + patternProperties: + "^channel@[0-9a-f]+$": + properties: + adi,rfilter-ohms: false + - if: properties: compatible: @@ -398,6 +426,7 @@ examples: reg =3D <8>; diff-channels =3D <8 8>; bipolar; + adi,rfilter-ohms =3D <2048>; }; =20 }; --=20 2.49.0 From nobody Tue Dec 16 07:31:46 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A391E2153DA for ; Tue, 6 May 2025 21:05:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746565532; cv=none; b=NVJKFQArpwmX7p60CATCulhq6yF725TpT3mb4/jtb0ImDO9YcGH0EaG0cEGN9v3VJo9UhPBG6uQX437deI1a3WMxla/pY7q7HJB30MCbJOEsK7FFOoEqsEjhlPwOtVE45oj1UfS06rVM809HOCif6CkWnZ1RUnOpz66D/dsAn9w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746565532; c=relaxed/simple; bh=z7O+cJ2s2VXn/7thHiJDbQY7RdvV9lwOOzqK+FZqCpw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EVHs1bf2PlucdTbvil+gpdknKzTIV0BFf9NvYnX/EeQptsb42bLEHqYGPsotbWnQCA+vGWTFJTB3T4R1+Rzw+coWs+fA8qMClothoIdtnlUqATn9EgPq0grR4zNOp2s6afcrb4jjMwucaFrXhvOFa8AF42RDPxKla5xsXKFqqgo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=tuFG8mL8; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="tuFG8mL8" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-43cf06eabdaso50763835e9.2 for ; Tue, 06 May 2025 14:05:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1746565528; x=1747170328; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IxjDKD+JKSiLqw8gK8zG+KrBnxfs5SYwuaGv7cdl5fk=; b=tuFG8mL84FquZoOheVVBWxOFQasfvzWViWkaacoMAJyXImsAIJQrTDp9ow8oSf3ZeM cpQpVs1Jak/bo1BBSkTEgyf9qmS401GUmcND2oByYzbTfa9JdkzB4+5+QBa5PXLraczV vxnKPBD0Aw4I1CG3nhwI8XLtKyFs2Zg9Tn1UJcMdoeZii2jfBeNHK/J5HHobQlOgUyj8 YmrOboTw+wUlWhTWlfKidYQU5O39yhtxUOjX4ZRTjZs3PPxhpI8J7NKskuG1XUOtvGC0 gfSvw1vRw6Lni3O8C8ig7lsJzcpPt0ofO5THHvCs28PSm4uazrHFIi9ziWuxvFT1PRhD +jwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746565528; x=1747170328; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IxjDKD+JKSiLqw8gK8zG+KrBnxfs5SYwuaGv7cdl5fk=; b=fqHq/dCOXzOkDAFSPIMV7nN9xaJqLO7mlGcThenn8XA6Gb/mRCHtWTi7P1kFXn1jxt u/Adq7HyizcCn3wrIAhbdfiAySjs5tMTpJw4yM7rsQCcuI5Sn6Db+2YezyHUMfHnQits SoAYZzawsgsw9g09YaYOIDiQenY8DGa/lVsIQkLYnDPejPMOOE/EHpXFVcWaNIqJ7g5d I4FdXKFM4kM1aJG2+eAw1D334lQEssDykSwxxRH7KMVPBv0NtFhxMYZ0fjmghBHJVYcW b14ctqgqMZJWQ63P1Jedp+E2z58JSPLKjTqO9oiRxwvh9tXJF9uqlYh4IQU4daQ8FmSv 1Luw== X-Forwarded-Encrypted: i=1; AJvYcCXQnsQ29lI9JbM9++7XWHyce6V18/PaTEAhhjqq2fqAfZR7UOIoMSdWqaAukBHfVEqi18JktimX6kYXLa0=@vger.kernel.org X-Gm-Message-State: AOJu0YyYnaoFaEXr73Jyq/K5MkFXHR83uIaVu5rsxkl6veF1eGyrGpWS UtHAKe3Y6r0s1m1nrt69dTcj/WbxQXqWmY47CXEtpM8ZK91Z+S0YHgY1tvhmVic= X-Gm-Gg: ASbGncsAl1Zp1T3crvUYD9b3rAtHBEOAGLc0giTQN/jOGj6r+XXljTMfDzxt8/SU9Yy v/u2pbPzTByM7jCfGCtnb6WpNV2HqcpQonHoEXVc84fwNNzQ5+/qHvihoHHDcRXqvRe3GOnQqx5 obW2wg6d2eAk6cLMCXlcmzrducSH2WL5LmvyPLq0grn+i3U03HljUm4/FuDI1nE0jIpDLQTFupt ZbO5nZ/ASeuvq8HML4hoWzzsliDuzwidZSTOubLGN61DtgqW8VcSANcwJ/V3nX+oZbhH+h9CPiv UzQcC0UOorFAnvPfrI1siS4O7DLHvnkrBHPTAtKaIwSVFha2Po04vt15mLIJSNDVXgmURCletWe kyu5M451FMMLqzg1TPNc6F1M= X-Google-Smtp-Source: AGHT+IH/I6vCXS+EzMw3gIbUrM+QZJy17d3GmYqQtggUh+d00T+nsunpp1HkxxkyT/ZZ+4Ldp/Ngiw== X-Received: by 2002:a05:600c:5006:b0:43c:ea36:9840 with SMTP id 5b1f17b1804b1-441d44de12dmr3049785e9.22.1746565527940; Tue, 06 May 2025 14:05:27 -0700 (PDT) Received: from [192.168.0.2] (host-87-8-31-78.retail.telecomitalia.it. [87.8.31.78]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-441d4351abdsm6794475e9.23.2025.05.06.14.05.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 May 2025 14:05:27 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Tue, 06 May 2025 23:03:51 +0200 Subject: [PATCH v3 5/5] iio: adc: ad7606: add gain calibration support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250506-wip-bl-ad7606-calibration-v3-5-6eb7b6e72307@baylibre.com> References: <20250506-wip-bl-ad7606-calibration-v3-0-6eb7b6e72307@baylibre.com> In-Reply-To: <20250506-wip-bl-ad7606-calibration-v3-0-6eb7b6e72307@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5739; i=adureghello@baylibre.com; h=from:subject:message-id; bh=P/FuxJZA+9kES7o8SpZCT2TnVHvYO5j9LvTN2jJFlis=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiQqvSYb7upmDlGwPPAjCt+jzb1+BmrOz3byPtZXjL22 xdt5d08HaUsDGJcDLJiiix1iREmobdDpZQXMM6GmcPKBDKEgYtTACZiKM/w39XKa/n7HcWltiHn 3DYW79QLWLLIjffi7mmB6gmCEU2pbxn+B+twGNwW4WFwFilxef0w4veF/t6tPT3noo+nbmB93vm BHQA= X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add gain calibration support, using resistor values set on devicetree, values to be set accordingly with ADC external RFilter, as explained in the ad7606c-16 datasheet, rev0, page 37. Usage example in the fdt yaml documentation. Tested-by: David Lechner Reviewed-by: Nuno S=C3=A1 Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 56 ++++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/iio/adc/ad7606.h | 4 ++++ 2 files changed, 60 insertions(+) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index a986eb1284106da4980ac36cb0b5990e4e3bd948..049fd8616769d32778aa238b348= b2fb82fa83745 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -33,6 +33,10 @@ =20 #include "ad7606.h" =20 +#define AD7606_CALIB_GAIN_MIN 0 +#define AD7606_CALIB_GAIN_STEP 1024 +#define AD7606_CALIB_GAIN_MAX (63 * AD7606_CALIB_GAIN_STEP) + /* * Scales are computed as 5000/32768 and 10000/32768 respectively, * so that when applied to the raw values they provide mV values. @@ -125,6 +129,8 @@ static int ad7609_chan_scale_setup(struct iio_dev *indi= o_dev, struct iio_chan_spec *chan); static int ad7616_sw_mode_setup(struct iio_dev *indio_dev); static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev); +static int ad7606_chan_calib_gain_setup(struct iio_dev *indio_dev, + struct iio_chan_spec *chan); =20 const struct ad7606_chip_info ad7605_4_info =3D { .max_samplerate =3D 300 * KILO, @@ -180,6 +186,7 @@ const struct ad7606_chip_info ad7606b_info =3D { .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606_calib_offset_avail, .calib_phase_avail =3D ad7606b_calib_phase_avail, }; @@ -195,6 +202,7 @@ const struct ad7606_chip_info ad7606c_16_info =3D { .scale_setup_cb =3D ad7606c_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606_calib_offset_avail, .calib_phase_avail =3D ad7606c_calib_phase_avail, }; @@ -246,6 +254,7 @@ const struct ad7606_chip_info ad7606c_18_info =3D { .scale_setup_cb =3D ad7606c_18bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606c_18bit_calib_offset_avail, .calib_phase_avail =3D ad7606c_calib_phase_avail, }; @@ -357,6 +366,49 @@ static int ad7606_get_chan_config(struct iio_dev *indi= o_dev, int ch, return 0; } =20 +static int ad7606_chan_calib_gain_setup(struct iio_dev *indio_dev, + struct iio_chan_spec *chan) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + unsigned int num_channels =3D st->chip_info->num_adc_channels; + struct device *dev =3D st->dev; + int ret; + + device_for_each_child_node_scoped(dev, child) { + u32 reg, r_gain; + + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret) + return ret; + + /* channel number (here) is from 1 to num_channels */ + if (reg < 1 || reg > num_channels) { + dev_warn(dev, "wrong ch number (ignoring): %d\n", reg); + continue; + } + + ret =3D fwnode_property_read_u32(child, "adi,rfilter-ohms", + &r_gain); + if (ret =3D=3D -EINVAL) + /* Keep the default register value. */ + continue; + if (ret) + return ret; + + if (r_gain > AD7606_CALIB_GAIN_MAX) + return dev_err_probe(st->dev, -EINVAL, + "wrong gain calibration value."); + + /* Chan reg is 1-based index. */ + ret =3D st->bops->reg_write(st, AD7606_CALIB_GAIN(reg - 1), + DIV_ROUND_CLOSEST(r_gain, AD7606_CALIB_GAIN_STEP)); + if (ret) + return ret; + } + + return 0; +} + static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan) { @@ -1410,6 +1462,10 @@ static int ad7606_probe_channels(struct iio_dev *ind= io_dev) chan->info_mask_separate_available |=3D BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_CONVDELAY); + ret =3D st->chip_info->calib_gain_setup_cb( + indio_dev, chan); + if (ret) + return ret; } =20 /* diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index f613583a7fa4095115b0b28e3f8e51cd32b93524..94165d217b69d54cbce9109b8c0= f9dc0237cf304 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -50,6 +50,8 @@ struct ad7606_state; typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, struct iio_chan_spec *chan); typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio_dev); +typedef int (*ad7606_calib_gain_setup_cb_t)(struct iio_dev *indio_dev, + struct iio_chan_spec *chan); =20 /** * struct ad7606_chip_info - chip specific information @@ -66,6 +68,7 @@ typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio= _dev); * @init_delay_ms: required delay in milliseconds for initialization * after a restart * @offload_storagebits: storage bits used by the offload hw implementation + * @calib_gain_setup_cb: callback to setup of gain calibration for each ch= annel * @calib_offset_avail: pointer to offset calibration range/limits array * @calib_phase_avail: pointer to phase calibration range/limits array */ @@ -81,6 +84,7 @@ struct ad7606_chip_info { bool os_req_reset; unsigned long init_delay_ms; u8 offload_storagebits; + ad7606_calib_gain_setup_cb_t calib_gain_setup_cb; const int *calib_offset_avail; const int (*calib_phase_avail)[2]; }; --=20 2.49.0