From nobody Tue Dec 16 23:07:18 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DB4C27FD72; Tue, 6 May 2025 12:25:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746534306; cv=none; b=gq5iKm6d6XX6SxrI4oTuSnKUpBoa/EfZxxaKU+LgrWSqK5+h6Ql+mT8pvCxHeilnRHqdjN1lBygtoxiI56kqq6Q3OPiDR/1k2a2Ywe/+DtUEkjdD1sU41bKnMKTPB1RT0f3OJpqseDSGDo5wxrAWykpBxRidRPATVlAt4HAraAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746534306; c=relaxed/simple; bh=gRWN4/WxQNgzKjCuCmcZKjoQVmfMZVTNU54WEek8EP4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iOqEH/kyRfB/wdaoEWduUr6QeGoms+wWysZ/080u7ywqktrLe8Fk6dvXGT1jQoo3z6Q1x6hGnzkwBv67v63OKDPTRBVOQw5kt4cS37XlA3FAeN+MGzPzLKnnTCBXEjAA6BKNY0ac+eMwjimfN2Z++X+dZN0NRUPdlNwfuNochpo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EHZHs+9d; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EHZHs+9d" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F1B6C4CEEE; Tue, 6 May 2025 12:25:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746534306; bh=gRWN4/WxQNgzKjCuCmcZKjoQVmfMZVTNU54WEek8EP4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EHZHs+9dVLolSMYcjh0g1FsSEzoa2/wxNl//whlVTNpE+Y5748T+TOuLOgvPqjjz0 NsBF+q6c6hGPU7MSOnUFMFq6b3uP70XSGLrMVTwtYrAO4/OI688eYCYGfuE0Aepb5U /j5y6ij1uRK0q5XjI3V0wVgJOmQRfBlUHe1iCG6Wh2b4yDNZyR9K53ou+IUcCIAsfY Z9pcZENwv5eU8WnivOgfKxjMI2BRHpEdPk7N2rPhVVXSMwPHxwqwdwcw4I+wolYqeI gv7c+WiY662+Jef9VX5EYIMPvIak53v9cAVdvR4PkW7Quz5m7I9DUvsD90q+gSsiOD RKC+L+hR90QVw== From: Lorenzo Pieralisi Date: Tue, 06 May 2025 14:23:44 +0200 Subject: [PATCH v3 15/25] arm64: Disable GICv5 read/write/instruction traps Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250506-gicv5-host-v3-15-6edd5a92fd09@kernel.org> References: <20250506-gicv5-host-v3-0-6edd5a92fd09@kernel.org> In-Reply-To: <20250506-gicv5-host-v3-0-6edd5a92fd09@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 GICv5 trap configuration registers value is UNKNOWN at reset. Initialize GICv5 EL2 trap configuration registers to prevent trapping GICv5 instruction/register access upon entering the kernel. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/include/asm/el2_setup.h | 45 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index ebceaae3c749b84395c9c5eccf0caf874697ad11..109b72b657d2fbb6d39e0446c10= d1b62e0a780b3 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -165,6 +165,50 @@ .Lskip_gicv3_\@: .endm =20 +/* GICv5 system register access */ +.macro __init_el2_gicv5 + mrs_s x0, SYS_ID_AA64PFR2_EL1 + ubfx x0, x0, #ID_AA64PFR2_EL1_GCIE_SHIFT, #4 + cbz x0, .Lskip_gicv5_\@ + + mov x0, #(ICH_HFGITR_EL2_GICRCDNMIA | \ + ICH_HFGITR_EL2_GICRCDIA | \ + ICH_HFGITR_EL2_GICCDDI | \ + ICH_HFGITR_EL2_GICCDEOI | \ + ICH_HFGITR_EL2_GICCDHM | \ + ICH_HFGITR_EL2_GICCRDRCFG | \ + ICH_HFGITR_EL2_GICCDPEND | \ + ICH_HFGITR_EL2_GICCDAFF | \ + ICH_HFGITR_EL2_GICCDPRI | \ + ICH_HFGITR_EL2_GICCDDIS | \ + ICH_HFGITR_EL2_GICCDEN) + msr_s SYS_ICH_HFGITR_EL2, x0 // Disable instruction traps + mov_q x0, (ICH_HFGRTR_EL2_ICC_PPI_ACTIVERn_EL1 | \ + ICH_HFGRTR_EL2_ICC_PPI_PRIORITYRn_EL1 | \ + ICH_HFGRTR_EL2_ICC_PPI_PENDRn_EL1 | \ + ICH_HFGRTR_EL2_ICC_PPI_ENABLERn_EL1 | \ + ICH_HFGRTR_EL2_ICC_PPI_HMRn_EL1 | \ + ICH_HFGRTR_EL2_ICC_IAFFIDR_EL1 | \ + ICH_HFGRTR_EL2_ICC_ICSR_EL1 | \ + ICH_HFGRTR_EL2_ICC_PCR_EL1 | \ + ICH_HFGRTR_EL2_ICC_HPPIR_EL1 | \ + ICH_HFGRTR_EL2_ICC_HAPR_EL1 | \ + ICH_HFGRTR_EL2_ICC_CR0_EL1 | \ + ICH_HFGRTR_EL2_ICC_IDRn_EL1 | \ + ICH_HFGRTR_EL2_ICC_APR_EL1) + msr_s SYS_ICH_HFGRTR_EL2, x0 // Disable reg read traps + mov_q x0, (ICH_HFGWTR_EL2_ICC_PPI_ACTIVERn_EL1 | \ + ICH_HFGWTR_EL2_ICC_PPI_PRIORITYRn_EL1 | \ + ICH_HFGWTR_EL2_ICC_PPI_PENDRn_EL1 | \ + ICH_HFGWTR_EL2_ICC_PPI_ENABLERn_EL1 | \ + ICH_HFGWTR_EL2_ICC_ICSR_EL1 | \ + ICH_HFGWTR_EL2_ICC_PCR_EL1 | \ + ICH_HFGWTR_EL2_ICC_CR0_EL1 | \ + ICH_HFGWTR_EL2_ICC_APR_EL1) + msr_s SYS_ICH_HFGWTR_EL2, x0 // Disable reg write traps +.Lskip_gicv5_\@: +.endm + .macro __init_el2_hstr msr hstr_el2, xzr // Disable CP15 traps to EL2 .endm @@ -323,6 +367,7 @@ __init_el2_lor __init_el2_stage2 __init_el2_gicv3 + __init_el2_gicv5 __init_el2_hstr __init_el2_mpam __init_el2_nvhe_idregs --=20 2.48.0